ECE3030 Physical Foundations of Computer Engineering, Fall 2015
Homework 12 - Solutions
1) (30 pts.) In this question you are asked to analyze how wire delay changes as the dimensions
of a wire change. The wire delay depends on both the resistance and capacitance of the wire
per unit length.
For this problem, we are concerned with two types of capacitance: Cground and Cx. Cground is
the capacitance to ground; it is formed by the parallel plate of the bottom of the wire.
Cx is the capacitance to an adjacent wire; it is formed by the parallel plate of the vertical
wall of the wire.
Assumptions given in the lecture:





Substrate is connected to ground
Resistivity of wires 1 and 2 is 
Distance between wire 1 and substrate: S𝑔
Distance between wire 1 and wire 2: S𝑥
Permittivity of the medium between wires and substrates: 𝜀𝑟 𝜀𝑜 = 𝜀𝑆𝑖𝑂2
𝑅1 = 𝜌
𝐿1
Wwire1 ∗ Hwire1
Parallel plate approximation for capacitances (neglecting fringing effects)
𝐶𝑔𝑟𝑜𝑢𝑛𝑑 = 𝜀𝑜 𝜀𝑟
𝐶𝑥 = 𝜀𝑜 𝜀𝑟
Wwire1 ∗ 𝐿1
S𝑔
Hwire1 ∗ 𝐿1
S𝑔
Delay Ground
𝜏ground = 𝑅1 ∗ 𝐶𝑔𝑟𝑜𝑢𝑛𝑑 = 𝜌
Wwire1 ∗ 𝐿1
𝐿1
1
∗ 𝜀𝑜 𝜀𝑟
= 𝜌𝜀𝑜 𝜀𝑟 𝐿1 2
S
S
Wwire1 ∗ Hwire1
g
g ∗ Hwire1
Delay X
𝜏x = 𝑅1 ∗ Cx = 𝜌
Hwire1 ∗ 𝐿1
𝐿1
1
2
∗ 𝜀𝑜 𝜀𝑟
=
𝜌𝜀
𝜀
𝐿
𝑜
𝑟
1
Sx
Wwire1 ∗ Hwire1
Wwire1 ∗ Sx
Parallel Total Delay (considering capacitances in parallel)
𝜏𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙 = 𝜏𝑔𝑟𝑜𝑢𝑛𝑑 + 𝜏x = 𝜌𝜀𝑜 𝜀𝑟 𝐿1 2 (S
1
1
+
)=
Wwire1 ∗ Sx
g ∗ Hwire1
a) (15 pts.) Assuming that Hwire1 = Hwire2 and that the ratio Wwire1/Hwire1 varies from 1 to
4 (by steps of one, i.e., the ratio is 1, 2, 3 and then 4), how does wire delay change for
a constant length as the ratio Wwire1/Hwire1 increases from 1 to 4?
Wwire1
=𝑥
Hwire1
where x = {1, 2, 3, 4}. Therefore Wwire1 = x ∗ Hwire1
𝜏𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙 = 𝜏𝑔𝑟𝑜𝑢𝑛𝑑 + 𝜏x = 𝜌𝜀𝑜 𝜀𝑟 𝐿1 2 (S
1
1
+ ∗
)=
H
x
H
∗
wire1
wire1
∗ Sx
g
As x increases, 𝜏𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙 decreases.
b) (15 pts.) Assuming that Hwire1 = Hwire2 and that the ratio Hwire1/Wwire1 varies from 1 to
4 (by steps of one, i.e., the ratio is 1, 2, 3 and then 4), how does wire delay change for
a constant length as the ratio Hwire1/Wwire1 increases from 1 to 4?
Hwire1
=𝑦
Wwire1
where y = {1, 2, 3, 4}. Therefore Hwire1 = y ∗ Wwire1
𝜏𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙 = 𝜏𝑔𝑟𝑜𝑢𝑛𝑑 + 𝜏x = 𝜌𝜀𝑜 𝜀𝑟 𝐿1 2 (S
As y increases, 𝜏𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙 decreases.
1
1
+
)=
Wwire1 ∗ Sx
g ∗ y ∗ Wwire1
2) (15 pts.) We require our chip to have a probability of error Perr,chip = 10-9. Your transistor
has a probability of error Perr,xtor = 10-12. What is the largest number of transistors you can
put on one chip?
Perr,sys = 1 - (1-Perr,xtor)n
10-9 = 1-(1- 10-12)n
(1- 10-12)n = 1- 10-9
n*log(1- 10-12) = log(1- 10-9 )
n = 1000
Note: In general, the probability of error of one component is less than the whole
system.
3) (15 pts.) One logic gate consumes 10 A of current. Your power supply voltage is 1V.
What is the maximum allowable power supply resistance to give a 10% drop in voltage
for 100,000 gates switching simultaneously?
Any power source has a maximum amount of power (Pmax) that can supply. A voltage
source, for example, will keep load the nominal voltage in the terminals of the load while the
power required by the load (Pload = Vload*Iload) is less than Pmax. In this case, Pload <
Pmax.
When the load requires a high amount of current such that calculated power in the load
Pload (assuming nominal voltage in the load) is greater than Pmax, we would violate physical
principles. Therefore, the source might be able to provide the required current by the load
but the circuit will compensate in a manner that the voltage in the load is less than the
nominal voltage and then Pload = Pmax. The remaining voltage is dropped in the internal
resistance of the source Rs (power supply of the source).
For 100,000 gates switching the total current = 10 A * 100,000 gates = 1 A. It can be inferred
of the problem that if we calculate Pload with nominal voltage (1 V) in the load, it would be
greater than Pmax. Therefore, the circuit will decrease the voltage in the load to compensate
this situation.
Drop in voltage w.r.t. the nominal of voltage is 10% of 1V. Then the voltage in the load is 0.9
V and the remaining voltage (0.1 V) is dropped in the internal resistance of the source Rs.
Invoking Ohm’s law
0.1 V = 1 A * Rs
Rs = 0.1 Ω
4) (30 pts.) A clock network drives 50,000 registers. The clock input to a register connects
to two transistor gates, each with Cg = 0.9 fF.
𝐶𝑡𝑜𝑡𝑎𝑙 = NumberRegisters ∗ CL, register = NumberRegisters ∗ (2 ∗ Cg) =
𝐶𝑡𝑜𝑡𝑎𝑙 = 50,000 ∗ 1.8 fF = 90 pF
a) (15 pts.) How many stages are in the clock tree if each driver drives 4 loads?
4𝑛 = 50000
𝑛=
ln(50000)
= 7.8
ln(4)
Therefore, 8 stages are required.
Note: You can use logarithm in any basis (exponential, 10) to find n.
b) (15 pts.) Assuming a 1 V swing each clock edge, how much current is drawn by the
clock network for a rise time of 0.2 ns?
Assume ∆𝑉 = 1 V of swing of clock signal. Charge required to drive register capacitance:
𝑞𝐶 = 𝐶𝑡𝑜𝑡𝑎𝑙 ∗ ∆𝑉 = 90 pF ∗ 1 V = 90 ∗ pC
𝑞𝐶 90 ∗ 10−12
𝐼=
=
= 450 ∗ 10−3 = 450 mA
𝜏𝑟
0.2 ∗ 10−9
5) (20 pts.) Plot the value of Np for Rent’s Rule for 1,000 ≤ Ng ≤ 100,000 for two sets of
parameters:
Remember Np is the number of pines required as a function of the number of
components Ng.  = and k p are parameters of the model that are related to the type
of technology and that allow a correct prediction.
a) (10 pts.) Rent’s classic parameters  = 0.6, k p = 2.5.
Code written to plot:
Ng = 1000:1000:100000;
b =0.6;
Kp= 2.5;
Np = Kp*(Ng.^b);
plot(Ng, Np);
xlabel('No.of gates');
ylabel('No of pins');
title('Np vs. Ng');
b) (10 pts.) Microprocessor parameters  = 0.45, k p = 0.82.
Code written to implement this:
Ng = 1000:1000:100000;
b =0.45;
Kp= 0.82;
Np = Kp*(Ng.^b);
plot(Ng, Np);
xlabel('No.of gates');
ylabel('No of pins');
title('Np vs. Ng');
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