Kumar Venkat
14388 NW Eagleridge Lane
Portland, Oregon 97229
(503) 716-8440
kvenkat@cleanmetrics.com
Highlights
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25+ years in engineering, software development, project leadership and management.
Extensive experience developing EDA tools for IC design (including timing and noise analysis)
and analytical tools in other domains.
Prior experience as IC and hardware design engineer.
Demonstrated ability to conceive, deliver and support complex technical solutions.
Master's degree in electrical and computer engineering. Graduate certificate in computer
modeling and simulation.
Experience
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12/07 - present: President & CTO, CleanMetrics Corp., Portland, OR
o Providing environmental analysis solutions to customers in diverse economic sectors.
Served nearly three dozen customers to-date.
o Solutions include innovative software tools and consulting for: product life cycle
assessment, carbon footprinting, greenhouse gas emissions inventories, supplychain/value-chain analysis including scope 3 emissions, and resource efficiency.
o Software tools written in C# (for sophisticated ASP.NET web apps) and C++ (for
Windows desktop apps).
09/95 – 12/07: President & CTO, Surya Technologies, Inc., Cupertino, CA & Portland, OR
o Provided electronic design automation (EDA) solutions for analysis, optimization and
verification of large integrated circuit designs.
o Software tools and technologies delivered to customers include: static timing analyzer,
design rules/constraints verifier, signal coupling and noise analyzer, timing optimizer,
and timing-driven design partitioner.
o Software tools written in C/C++ (with additional code in Yacc/Lex and Perl) for
UNIX/Linux platforms.
o Customers in the US, Japan and India included: Advanced Micro Devices, Equator
Technologies, C-Cube Microsystems, Seiko Instruments, 3Dfx Interactive, Fujitsu
Microelectronics, CadMOS Design Technology (now part of Cadence), Procket Networks,
ReShape, SII EDA Technologies/JEDAT Innovation, and Atrenta.
06/91 - 8/95: Member of Technical Staff/Project Leader, Silicon Graphics, Mountain View, CA
o Led a software R&D team in the development of a new gate-and-transistor-level static
timing verifier that includes a number of innovative features. Developed detailed timing
models for electronic circuits at the transistor and gate levels. Directed and participated
in a 2-year software development project. This tool has been used to analyze/verify
large standard-cell and custom integrated circuit designs.
o Led a hardware design team in the development of a high-bandwidth memory
subsystem for SGI's Challenge multiprocessor server systems. Responsible for two large
ASICs and complex system design. Also, developed CAD methodology and tools to
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support/enhance testability, timing analysis and design rule checking. Received a US
patent for part of this work (US patent # 5,272,664).
06/89 - 06/91: Member of Technical Staff, Sun Microsystems, Mountain View, CA
o Designed a secondary cache-controller chip for Sun's SuperSparc microprocessor. Also,
designed the scan/JTAG test logic for the chip. Contributed to CAD methodology
including timing analysis, synthesis and circuit verification. Received a US patent for part
of this work (US patent # 5,987,570).
03/88 - 06/89: Senior Design Engineer, Intel Corp., Santa Clara, CA
o Member of the 486 microprocessor design team. Responsible for processor architecture
issues, microcode development, architecture/microcode verification, and verification
tools.
03/85 - 03/88: Systems Engineer, Reflectone Inc., Tampa, FL
06/84 - 02/85: Design Engineer, Dynamic Computer Architecture, St. Petersburg, FL
Education
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1/05 – 3/06: Portland State University, Portland, OR
o Graduate Certificate in Computer Modeling and Simulation. Focus: System dynamics,
discrete-event simulation, agent-based simulation, optimization, and statistical analysis.
Used software tools such as Vensim, Arena, NetLogo, and MATLAB. GPA: 4.0.
9/88 – 3/90: Stanford University, Stanford, CA
o Graduate courses in electrical/computer engineering. Focus: VLSI design and parallel
computer architectures. Grades: A's.
8/85 – 12/87: University of South Florida, Tampa, FL
o Graduate courses in electrical engineering. Focus: Digital communication systems and
digital signal processing. GPA: 4.0.
1/83 – 8/84: University of Texas, El Paso, TX
o MS in Electrical Engineering. Focus: Computer engineering. Thesis: Performance
Analysis of Three Interconnection Networks for Large Multimicrocomputer Systems.
Graduate teaching assistant and recipient of university president's scholarship award.
GPA: 4.0.
7/77 – 5/82: University of Madras, India
o BS in Electrical Engineering. Senior project: Stability Analysis of Electric Grids. Grade:
Honors.
Selected Publications
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Timing Verification of Dynamic Circuits, IEEE Journal of Solid-state Circuits, 1996.
Timing Verification of Dynamic Circuits, Custom Integrated Circuits Conference, 1995.
Follow these guidelines to design testable ASICs, boards and systems, EDN, 1993.
Generalized Delay Optimization of Resistive Interconnections Through an Extension of Logical
Effort, IEEE International Symposium on Circuits and Systems, 1993.
A Structured Design for Test Methodology, 11th IEEE VLSI Test Symposium, 1993.
ATPG Tools are a Varied Lot, Electronic Engineering Times, 1992.
Analysis of Ring, Cube and Tree Multimicrocomputer Systems, IEEE Region 5 Conference, 1986.
A Monitor for a Dynamic Multicomputer System, Int’l Conf. on Supercomputing Systems, 1985.
Link to recent publications on environmental modeling, analysis and performance metrics.