Progress report on development of the Low Power LVDS Receiver in 0.25u CMOS
technology for the ALICE Silicon Strip Detector (SSD).
20 January 2003.
V. Gromov (vgromov@nikhef.nl), R. Kluit.
ET NIKHEF, Amsterdam.
Abstract.
A new LVDS Receiver circuit in 0.25u CMOS
technology has been developed to satisfy severe
constraints on power dissipation made for the ALICE
SSD front-end control electronics.
The LVDS Receiver is focused on consuming the
least power while being expected to operate under
relatively low data speed (10MHz).
The circuit description along with test results are
presented and compared to the simulations.
Introduction.
The ALICE SSD electronics includes several ASICs
(application-specific integrated circuits) designed in
0.25u CMOS technology. The chips will operate in a
closed area where dissipated power cannot be easily
taken aside. Therefore it is important to keep the total
power consumption as low as possible.
LVDS Signaling Standard is used throughout the
system as an interface between the chips. The LVDS
receiver has been one of the most common cells on the
chips. By making the cell less power consuming we can
save a lot of power overall.
Although the expected data speed is 10MHz at the
most, the low power cell must be fast enough to cope
with the speed.
Some of the chips will be AC-coupled, as long as
they will work at different ground potentials. That means
the receiver needs a self-biasing capability.
It is reasonable to switch the receiver off while data
transmission is not on. For this purpose an
enable/disable functionality is necessary to implement.
On the basis of the arguments listed above a Low
Power self-biased LVDS Receiver with enable/disable
function, capable to operate at 10MHz data speed is
designed in 0.25u CMOS technology.
Inputs for the receiver design.
Main specifications of LVDS Signaling Standard
and operation conditions of ALICE SSD read-out
determine inputs for the receiver design:
. characteristic impedance of the transmission cable
(equal to the value of the terminating resistor)  110.
. differential voltage swing:
350mV  80mV
. power dissipation in the terminating resistor:
(350mV)2 /110 = 1.1mW.
.common mode offset:
1.25V0.5V.
.maximum required data speed :
10MHz.
.the circuit has to operate in a noisy environment,
therefore special measures should be taken to suppress
common mode disturbances and avoid noise triggering.
Specifications of the receiver.
1. Technology.
The receiver cell must be compatible with any
design in 0.25u CMOS technology and hence it has to
be developed in this technology.
2. Speed.
The receiver should be fast enough to handle
10MHz data speed with 50% duty cycle.
3. Power consumption.
Since terminating resistor dissipates 1.1mW, it does
not makes sense to require the receiver to consume much
less power than 1.1mW because further cut-backs will
not lead to visible power savings in total.
4.Common mode range of operation.
A rail-to-rail differential stage at the input of the
receiver is needed to ensure reliable operation and high
common mode noise suppression in the range:
1.25V  0.5V.
4. Hysteresis.
To avoid multiple noise triggering at the moment
when both inputs approaching turn-off point a hysteresis
is necessary. The level of hysteresis needs to be larger
than the noise peak-to-peak value. By estimating the
noise level we suggest a hysteresis of  25mV will be
enough.
5. Self-biasing capability.
As the receiver will be AC-coupled to the LVDS
driver, self-biasing at the inputs is necessary. The input
voltage levels must comply with following conditions:
VH - VL =350mV  70mV
(VH + VL)/2 =1.25V  150mV
6. Enable/disable functionality.
To avoid unnecessary power dissipation when the
receiver is out of use, a disabling function should be
implemented into the circuit.
2
Coupling to the receiver inputs.
There are two ways to couple the receiver to the
transmission cable (see Fig.1). We use DC-coupling
when the driver and the receiver operate at the same
ground potential. If it is not the case, AC-coupling is
necessary. The difference between these modes of
operation is described in Fig.2.
correct quiescent voltage levels at the inputs (see C in
Fig.2).
Otherwise it can happen that the swing is just not
enough to give an overdrive sufficient to switch the
receiver (see D in Fig.2). Therefore range of deviation
of voltage levels at the inputs needs to be consistent
with range of deviation of the driver current in order to
avoid the odd situation where data transmission does
not occur.
Fig.1. Principal diagram of DC-coupling to the
receiver and principal diagram of AC-coupling to the
receiver.
The LVDS driver is a current source pulling the
current through the terminating resistor (R=110 Ohm).
The current runs clockwise or other way around
according to the logic state. It also controls common
mode voltage level. Differential voltage swing is set by
the current value and the value of the terminating
resistor. Due to fabrication process variation it can
happen that the current deviate from the nominal value
(3mA  0.7mA). Moreover the common mode voltage
value can shift in the range 1.25V  0.5V.
The receiver must be capable to operate within the
range of the deviations.
In DC-coupling mode the driver is direct coupled
to the receiver. In order to set the receiver into a certain
logic state the differential swing (which is voltage
overdrive in this case) must be at least 100mV. That
means it is not critical if due to fabrication process
variation the driver delivers current slightly lower than
the nominal (see A and B in Fig.2).
In contrast to that, in AC-coupling mode the driver
determines differential swing but not the quiescent
voltage levels at the receiver inputs and hence the
overdrive. It makes no problem if the driver delivers
nominal current and the receiver self-biasing chain sets
Fig.2. Signals at the LVDS Driver output and LVDS
Receiver input in DC-coupling mode and AC-coupling
mode of operation.
The circuit.
The principal diagram of the receiver is given in
Fig.3. The comparator converts low-voltage differential
signals at the inputs into a CMOS level signal at the
output. The positive feedback chain is to provide proper
bias voltages at the inputs when the receiver operates in
AC-coupling mode. It includes Level adaptor and
feedback resistors. The reset circuit sets the receiver into
initial logic state right after the start-up. It consists of
two CMOS transistors bypassing the feedback resistors,
a NAND gate and an inverter gate. A reference voltage
(Vref= +1.25V) along with biases for the current sources
(Ib_Nch, Ib_Pch) come from the build-in Reference
3
source. The Enable input controls the state of the
receiver.
Fig.3. Principal diagram of the receiver.
The design.
1. Rail-to-rail differential comparator with
hysteresis.
The comparator is the key component of the design
(see Fig.4). Two complementary principal differential
pairs (M479, M488 and M210, M218) form a rail-to-rail
structure at the input. It is followed by cascode stages
(M217, M481) loaded with transistors in the diode
configuration (D1, D2). Drains of the transistors have
been biased to 1.25V (Vref1=Vref2). That sets voltage
swing at the Out1 point (VL=1.25V-0.8V=0.45V and
VH=+1.25V+0.8V=2.05V). Inverters at the output
convert these levels into CMOS ones (VH=Vdd,
VH=Vss) and besides make the level transition process
much faster.
With the purpose to introduce hysteresis, two
additional complementary differential pairs (M492,
M478 and M211, M63) operate in parallel to the main
input differential pair. Output voltages (Out1, Out2)
control the additional differential pairs. This solution
makes the turn-off voltage dependant on the present
logic state of the comparator. The comparator turns off
not exactly at the moment when voltages at the inputs
(InPlus, InMinus) are equal, but when the overdrive
reaches 25mV. The overdrive value and hence the
hysteresis level is set with the proportionality between
currents coming through the main and additional
differential pairs.
Fig.4. Schematic of the
comparator with hysteresis.
rail-to-rail
differential
2. Level Adaptor.
The main function of the level adaptor is to deliver
quiescent LVDS logic levels to the comparator input
when the receiver is used in AC-coupling mode (see
Fig.5). Gate I318 convert single input signal into
complementary output signals. These direct the current
either to the route M88, M83, M71, M72, M73, M53
(stripped line) or to the route M88, M82, M84, M85,
M86, M53 (dotted line). As middle point of the circuit is
biased to +1.25V, output levels (OutP, OutN) have been
set by voltage drop on zero-voltage threshold transistors
in diode configuration (M71,M72 and M84,M85) as
follows:
VL= +1.25V-0.2V=1.05V,
VH= +1.25V+0.2V=1.45V.
4
Ratio of areas of transistors M67 and M70
(W67/W70=0.33) together with value of resistor R1 (1k)
determine current value in the circuit (42uA). The value
is almost not sensitive to the supply voltage fluctuations.
When disabled (Enable1 = GND) the current path is
broken and the bias voltages drift to the power supply
rails (Ib_Pch = VDD, Ib_Nch = GND).
A voltage follower represents the reference voltage
source (+1.25V) (see Fig.7). The output transistor M502
drives 49uA and has output impedance 1k.
+1.25V
Fig.5. Schematic of Level Adaptor.
Reference source.
The current reference circuit is used to generate bias
voltages (Ib_Nch, Ib_Pch) for current sources of the
receiver (see Fig.6).
Fig.7 Schematic of the reference voltage source
(+1.25V).
Test results.
Fig.8 shows experimental set-up used for the testing
of the receiver.
Fig.8 Experimental set-up for testing of the
receiver.
Fig.6. Schematic of the current reference circuit.
Pulse generator PM 5786 feeds the receiver with
differential input signals and sets common mode voltage
5
level. The programmable pulse generator controls
Enable and ResetAC functions of the chip while the
Tektronix Scope does the measurements.
DC-coupling mode.
Fig.9 demonstrates operation of the receiver in DCcoupling mode under following conditions: common
mode voltage is 1.25V, duty cycle is 50%, differential
swing at the inputs is 270mV (that is what the LVDS
driver delivers in the worst case). The receiver easily
runs at data speed as high as 30MHz. If the data speed
goes up to 60MHz the receiver starts to fizzle out as the
duty cycle at its output declines from 50% level. The
measurements are in good agreement with the HSPICE
simulations.
Diff. Swing = 270mV
LVDS_InP
LVDS_InN
receiver is not capable to handle the data speed.
Maximum data speed is then:
Fmax  0.5 / Internal delay
The receiver response to the input differential
signals taken on various common mode levels are given
in Fig. 10 (data speed is 10MHz, differential swing is
270mV). Figure 10 demonstrates that the receiver can
operate in range 1.25V0.5V with almost no change of
its speed properties.
LVDS_InP
LVDS_InN
Com . mode = 0.75V
Internal delay = 8.6ns
Fmax  60MHz
Com .mode = 1.25V
LVDS_InP
LVDS_InN
OutCMOS
Freq = 10 MHz
LVDS_InP
LVDS_InN
OutCMOS
Com . mode = 1.25V
Internal delay = 8.6ns
Fmax  60MHz
LVDS_InP
LVDS_InN
OutCMOS
OutCMOS
Freq = 33 MHz
Duty cycle is not
kept at 50 %
level
Freq = 67 MHz
Fig.9 Operation of the receiver in DC-coupling
mode. Common mode voltage is 1.25V, duty cycle is
50%, differential input swing is 270mV. Data speed is
10MHz, 33MHz, 67MHz.
There is a different way to estimate the maximum
data speed of the receiver. The internal delay is caused
by the fact that it takes some time for the circuit to get to
the turn-off point. The circuit does not respond properly
if the input signal jumps to adjacent logic state and
returns back faster than the internal delay time. Thus the
OutCMOS
LVDS_InP
LVDS_InN
Com . mode = 1.75V
Internal delay = 9.4ns
Fmax  50MHz
OutCMOS
Fig.10 Operation of the receiver in DC-coupling
mode. Data speed is 10MHz, duty cycle is 50%,
differential input swing is 270mV, common mode voltage
is 0.75V, 1.25V and 1.75V.
Figure 11 shows the receiver behavior when
differential swing at the input is getting lower (data
speed is 10MHz, common mode voltage is 1.25V). We
notice some worsening of the high-speed properties
down to 45MHz at the swing value of 100mV.
6
Diff. Swing = 270mV
LVDS_InP
LVDS_InN
Com . mode = 1.25V
Internal delay = 8.6ns
Fmax  60MHz
+26mV
LVDS_InP - LVDS_InN
-23mV
OutCMOS
OutCMOS
Diff. Swing = 150mV
LVDS_InP
LVDS_InN
Internal delay= 10.4ns
Fmax  50MHz
AC-coupling mode.
OutCMOS
Diff. Swing = 100mV
LVDS_InP
LVDS_InN
Internal delay= 11.6ns
Fmax  45MHz
Fig.12 Operation of the receiver in DC-coupling
mode. DC hysteresis is 25mV.
High-speed properties of the receiver in ACcoupling mode are quite similar to those in DC-coupling
mode (see Fig.13) (Cin=240pF, duty cycle is 50%,
differential input swing is 360mV). The circuit can
operate at 50MHz data speed.
Diff. Swing = 360mV
LVDS_InP
LVDS_InN
Freq = 20 MHz
OutCMOS
OutCMOS
Fig.11 Operation of the receiver in DC-coupling
mode. Data speed is 10MHz, duty cycle is 50%, common
mode voltage is 1.25V. Differential input swing is
270mV,150mV, 100mV.
Input differential overdrive at the moment when
the output turns off give magnitude of DC hysteresis
(see Fig.12). The DC hysteresis have been found as deep
as  25mV (simulations gave slightly different value
30mV).
LVDS_InP
LVDS_InN
Freq = 52 MHz
OutCMOS
Fig.13 Operation of the receiver in AC-coupling
mode. Duty cycle is 50%, differential input swing is
270mV. Data speed is 20MHz, 50MHz.
7
As already mentioned, in AC-coupling mode, the
differential swing needs to be consistent with the
quiescent voltage levels at the inputs of the receiver to
make it switch (see Fig.14) (Cin=240pF, duty cycle is
50%, data speed is 10MHz). The minimum value if the
swing is 220mV. With such a swing the receiver can
operate at most at 30MHz data speed.
LVDS_InP
LVDS_InN
Initial state
Minimum Diff. Swing = 220mV
OutCMOS
LVDS_InP
LVDS_InN
ResetAC INV
min 1us
Internal delay= 16ns
Fmax  30MHz
Fig.15 Operation of the receiver in AC-coupling
mode. Testing of the reset functionality.
OutCMOS
Fig.14 Operation of the receiver in AC-coupling
mode. Duty cycle is 50%, data speed is 10MHz.
Minimum differential input swing is 220mV
Table1 presents values of the quiescent voltage
levels at the inputs of the receivers. They characterize
performance of the self-biasing chain. The levels are
good matching although for a definite conclusion
statistics is low.
V(LVDS_InP)=1.41V0.02V
V(LVDS_InP)=1.07V0.03V.
Chip
number
1
4
Table 1.
Channel
LVDS_InP
TMS
TCK
TRST
TMS
TCK
TRST
1.43V
1.43V
1.42V
1.43V
1.39V
1.43V
The receiver demonstrates sound operation under
different supply voltages (see Fig.16) (data speed is
10MHz, differential swing 360mV).
VDD=2.2V
LVDS_InP
LVDS_InN
OutCMOS
Internal delay  8ns
Fmax  60MHz
VDD=2.5V
LVDS_InN
1.08V
1.09V
1.04V
1.09V
1.04V
1.07V
LVDS_InP
LVDS_InN
OutCMOS
Internal delay  8 ns
Fmax  60MHz
VDD=2.8V
Tests of the reset functionality have been described
in Figure 15. An extra inverter in front of ResetAC input
makes the low state active. With Cin=240pF it takes at
least 1us to set the receiver into the initial logic state.
LVDS_InP
LVDS_InN
OutCMOS
Internal delay  8 ns
Fmax  60MHz
Fig.16 Operation of the receiver in AC-coupling
mode. Duty cycle is 50%, data speed is 10MHz. Supply
voltage (VDD) is 2.2V, 2.5V, 2.8V.
8
Ripples on the supply voltage do not seem to be a
matter for concern as long as they do not influence the
operation properties. (see Fig.17) (VDD is 2.5V 
100mV).
has the maximum value and differential sweep is the
minimum the overdrive is 280mV. That is sufficient to
make the receiver to switch.
0.92V+(1.31V-0.98V)-[1.3V-(1.31V-0.98V)]=280mV.
Table 2.
VDD=2.5  100mV
LVDS_InP
LVDS_InN
Process
deviation
+1.5
0
-1.5
LVDS Driver with
a N-well reference
resistor
LVDS Driver with
a Polysilicon
reference resistor
LVDS Receiver (modified)
UoutP
UoutN
UoutP
UoutN
1.44V
1.00V
1.41V
1.01V
LVDS_
InP
1.26V
LVDS
_InN
1.49V
48ua
1.34V
1.01V
1.36V
1.00V
1.1V
1.4V
47ua
1.28V
1.03V
1.31V
0.98V
0.92V
1.3V
46ua
Iref
OutCMOS
Conclusion
Fig.16 Operation of the receiver in AC-coupling
mode with 200mV ripples on the power supply rail.
Effect of the fabrication process variations.
High yield of the chips is one of the main objectives
to fulfill. Fabrication process instability spoils
performance of the circuit in some cases even so far that
it has no use. We have carried out corner analysis to
make sure that the circuit is fully operational in the range
1.5 (yield 86%).
Both LVDS Driver and LVDS Receiver are
involved into data transfer. As was found, the Driver
output current deviates a lot within from the nominal
value. This caused by a variation of value of the N-well
resistor that is a reference component for the output
current. The stability is much better if the OP (P+ poly)
resistor is used instead of the N-well resistor. (see Table
2).
The Gate-to-source voltage of MOS transistors
heavily depends on the process variation. That can put
current reference circuit of the receiver out of the normal
operation. After a modification of the circuit it will
deliver a steady current across the mentioned process
variation (see Table2). Nevertheless, the quiescent
voltage levels at the receiver inputs are not completely
stable (see Table 2). This occurs due to variation of
voltage drop in ZVT MOS transistors in the Level
Adaptor block (see Fig.5).
In the worst case of AC-coupling mode when the
gap between the quiescent voltages at the receiver input
We have designed and tested a Low Power LVDS
Receiver capable to operate in both AC-coupling mode
and DC-coupling mode. The following specifications
have been disclosed (see Table 3).
Table3.
Specifications.
Power consumption
429uA 2.5V
(simulation)
=1.073mW
Nominal data rate
10MHz
Maximum data rate
50MHz
Common mode range of
1.25V0.5V
operation
Single power supply (VDD)
2.5V
Differential swing in DC100mV
coupling mode.
DC-hysteresis
25mV
Precision of the input voltage
VH - VL =350mV
level setting in AC-coupling
 70mV
mode.
(VH + VL)/2 =1.25V 
150mV
Differential swing in AC220mV
coupling mode.
Enable/disable functionality
yes
In the forthcoming submission we are going to
modify the circuit in order to avoid improper operation
within expected range of the fabrication process
variation (1.5, yield 86%).
Besides, it seems reasonable to design a separate DC
version of the receiver as long as self-biasing chain is
not needed in this case. We can save power and
eliminate destruction of the input impedance by the
positive feedback.
9