Multiprocessor Architecture
for Image processing
Under the guidance of
Dr.Anshul Kumar
Mayank Kumar – 2006EE10331
Pushpendre Rastogi – 2006EE50412
Objectives
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To learn to work on FPGA platform.
Learning the design philosophy of a soft core
multiprocessor architecture.
Using multiprocessor architecture to
implement adaptive background mixture
model for motion segmentation.
i.e Background modeling and change detection
algorithm. (Cris stauffer)
Motivation
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Signal processing, especially Image processing
involves repetitive computation which can easily be
divided into parallel computations
There are many algorithm that follows “locally
sequential globally parallel” computation.
Surveillance camera related processing need
economic real time solutions.
FPGA provides an easy way to alter design depending
on algorithm requirements – making soft multicore
processing feasible.
Architecture of the Processing Elements (PE) could
be optimized for image processing.
Adaptive background mixture model
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The algorithm helps to generate an adaptive
model for the background and helps in motion
detection.
This can be applied for surveillance.
The algorithm is spatially parallel, thus
computations for different part of the image
can be done simultaneously.
This will help in real time operation of this
algorithm on embedded platform.
Nature of parallelism
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Data Partitioning: The task is partitioned so
that each processor performs exactly the same
function, but on different sub-blocks of data.
For different image regions, our chosen
algorithm is sequential in nature, which can be
efficiently implemented through a processor.
Basic Idea
RGB Conversion
Power PC
M1
M
M1
M1
E
Video
ADC`
M
O
MPMC
M1
M1
M1
M1
M1
M1
Video
DAC
R
Y
Array Topology
Camera
Virtex II Pro
Monitor
Basic Idea
RGB Conversion
Power PC
M1
M
M1
M1
E
Video
ADC`
M
O
MPMC
M1
M1
M1
M1
M1
M1
Video
DAC
R
Y
Array Topology
Monitor
Camera
Virtex II Pro
Inter-processor Communication [12]
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For transferring large chunks of image data, we will
be using shared external DDR Ram as
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It provides large memory space for storing multiple frames.
Multiple processors can access the RAM simultaneously
using MPMC.
For sharing intermediate computation results we will
use FSL Links between neighboring processors.
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Unidirectional point-to-point communication.
Unshared non-arbitrated communication mechanism.
FIFO based communication.
Network Topology [1]
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Completely meshed: Each node is connected
to all other nodes. Adv: Reduce inter processor
communication time. Disadvantage: Max 9
processors possible.
Ring Network:
Star Network
Array Network: (our choice)
Overall Plan
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Analysis of the algorithm.
Configuring Video input and output for XUPV2P
FPGA kit.
Finalizing the architecture
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For one processor
For two processors
For multiprocessors
Implementing
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Basic Test algorithm
The algorithm
Work Done
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Studied Background mixture Model for
foreground subtraction algorithm [2], [3], as a
case study.
Analysis of the algorithm for:
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Parallelism exploitation
Length of code for implementation
Memory requirements to store data.
Feasibility
Work Done
RGB Conversion
Power PC
Virtex II Pro
Video
ADC`
Camera
Top Down Approach
Video
DAC
Monitor
Work Done
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Studied Microblaze architecture. [4]
Studied
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FSL Link [5]
PLB, LMB, OPB Buses [6]
XPS Design Flow [7]
Literary survey on related works [8],[9], [10], [11]
Configuration Video input and output for
XUPV2P FPGA kit.
Bottom Up Approach
Work Ahead – Step 1
RGB Conversion
Power PC
M
Video
ADC`
Memory Read
And Write
Video
DAC
E
M
O
MPMC
R
Y
Camera
Virtex II Pro
23rd Feb – 7th March
Monitor
Work Ahead – Step 2
RGB Conversion
Power PC
M
Video
ADC`
Some
Simple
Processing
E
M
MPMC
M1
O
Video
DAC
R
Y
Camera
Virtex II Pro
8th March – 15th March
Monitor
Work Ahead – Step 3
RGB Conversion
Power PC
M1
M
M1
M1
E
Video
ADC`
M
O
MPMC
M1
M1
M1
M1
M1
M1
Video
DAC
R
Y
Simple processing
Camera
Virtex II Pro
24th March – 5th April
Monitor
Work Ahead – Step 4
RGB Conversion
Power PC
M1
M
M1
M1
E
Video
ADC`
M
O
MPMC
M1
M1
M1
M1
M1
M1
Video
DAC
R
Y
Complex Processing
Camera
Virtex II Pro
6th April – 19th April
Monitor
Time Line
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Step 1 – 23rd Feb – 7th March
Step 2 – 8th March – 15th March
Step 3 – 24th March – 5th April
Step 4 – 6th April – 19th April
Related Works
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Design Development and performance evaluation of
multiprocessor system on FPGA. Somen Barma, CSE
IITD. [8].
A Microblaze based Multiprocessor SoC[1]
An FPGA based soft multiprocessor system for IPv4
packet forwarding. [9]
An automated framework for FPGA based soft
Multiprocessor System. [10]
Multiprocessor interconnection based on DMA for
FPGA.[11]
REFERENCES
[1] A Microblaze based Multiprocessor SOC – 2003
[2] Adaptive background mixture model for real-time tracking – 1999
[3] Understanding background mixture model for foreground segmentation –
2002
[4] Microblaze processor reference guide
[5] Xilinx FSL datasheet
[6] Xilinx Microblaze bus interface (ppt)
[7] Virtex II Pro design flow – getting started
[8] Design Development and performance evaluation of multiprocessor system
on FPGA. Somen Barma, CSE IITD. Under Prof Kolin Paul
[9] An FPGA based soft multiprocessor system for IPv4 packet forwarding.
[10] An automated framework for FPGA based soft Multiprocessor System.
[11] Multiprocessor interconnection based on DMA for FPGA.
[12] XPS White paper – Designing multiprocessor System on Platform Stdio.
Visit www.cse.iiitd.ernet.in/~ee5060412