Analog Devices
FMCOMMS1-EBZ
WINLAB – Rutgers University
Date : April 22, 2013
Authors :
Prasanthi Maddala, prasanthi.m@gmail.com

 Software tunable across wide frequency range (400MHz to 4GHz)
 125MHz channel bandwidth (250MSPS ADC, 1GSPS (1230MSPS) DAC)
 RF section bypass for baseband sampling
 Phase and frequency synchronization on both transmit and receive paths


Supports MIMO radio, with less than 1 sample sync on both ADC and DAC
Common I 2 C access for all device registers


Key Components
- AD9122 Dual, 16-Bit, 1200 MSPS, TxDAC
+® Digital-to-Analog Converter with offset, phase and gain compensation.
- ADL5375 400 MHz to 6 GHz Broadband Quadrature Modulator.
- ADF4351 Wideband Synthesizer with Integrated VCO (35MHz to 4400MHz).

- ADL5602 50 MHz to 4.0 GHz RF/IF Gain (20dB) Block.
FPGA Interface
- dac_data_out[15:0] : interleaved I/Q data from the FPGA to the DAC
- dac_clk_out : DCI input to the DAC, reference bit used to generated DDR clock for data sampling in the DAC. I DAC data should correspond to DCI high and Q DAC data to DCI low.
- dac_frame_out : used for DAC FIFO reset
- dac_clk_in : clk input to the FPGA (comes from AD9523). This clock is used to send data out to the DAC and to generate dac_clk_out (same rate).

 Transmit bandwidth can be as high as 250 MHz, depending on the flatness of
ADL5602 and ADL5375 that works for your application
 With a sampling rate of 1230MSPS, AD9122 can support a bandwidth of 600MHz
(300MHz ?)


Key Components
- AD9548 Quad/Octal Input Network Clock Generator/Synchronizer (1Hz to 750MHz)
- AD9523-1 Low Jitter Clock Generator (1MHz to 1GHz) with 14 Outputs.
 FPGA Interface/Inputs

- ref_clk_out : reference clock from the FPGA to AD9548.
- crystal oscillators : 19.2MHz oscillator connected to AD9548
50
– 122.88MHz VC oscillator connected to AD9523
Clocking in the default reference design
- ref_clk_out = 30MHz. This is cleaned up (from a jitter standpoint) and sent to
AD9523
- AD9523 takes this, and creates
491.52 MHz for the DAC sample rate
245.76 MHz for the ADC sample rate
122.88 MHz for the reference clocks for the LO PLLs.

 Key Components
- ADL5380 400 to 6000 MHz Quadrature Demodulator, 500MHz bandwidth.
- AD8366 DC to 600 MHz, Dual-Digital Variable Gain ( 4.5dB to 20.5dB) Amplifiers.
- AD9643 14-Bit, 250 MSPS, Dual Analog-to-Digital Converter (ADC).
- ADF4351 Wideband Synthesizer with Integrated VCO (35MHz to 4400MHz).
 FPGA Interface
- adc_data_in[13:0] : 14 bit interleaved I/Q samples from ADC to the FPGA
- adc_clk_in : clock from ADC to FPGA in sync with the data
- adc_or_in : overrange at the ADC input is indicated by this bit (with some latency)

 ADL5380 baseband response shows the 3dB point at 300MHz.