A Mixed-Signal/MEMS CMOS Co-Design
Flow with MEMS-IP Publishing / Integration
Che-Sheng Chen1 (jason@nctutwt.net),
Louis Thiam2, Ahmed Hussein Osman2,
Kuei-Ann Wen1, Long-Sheng Fan3
1 Inst.
Of Electronics, National Chiao Tung University, Taiwan
2 VCAD, Cadence Design System, Ltd, USA
3 Inst. Of NanoEngineering and MicroSystems,
National Tsing Hua Unversity, Taiwan
Motivation
Analog+Mixed-Signal
+ Digital Components
MEMS IP
C-to-V
MEMS
Inter-digitized
Sensor
Glue
Signal
Proc
Single monolithic
CMOS-MEMS
C-to-V
Logic
Clock Tree
& Divider
FEM Simulation
ADC
Design Team Fragmentation
Cross-domain Verification
Cross-discipline Verification
MEMS +
Mixed-Signal +
Digital concurrent design
Methods for efficient use of EDA + FEM
Inter-digitized
Sensor IP
Integration
Outlines
 MS/MEMS Co-Design Flow Overview
 MEMS Design Sub-flow
 MEMS
HDL Behavioral Modeling
 DRC-aware Layout Generation
 MEMS-IP Publishing/Integration Interface (SIMPLI)
 Overview
 Layout
Black-boxing
 HDL Code Encryption
 Electrical Parasitic Extraction
 Mixed-Signal Design Sub-flow
 Correlated
 Summary
Double Sampling Capacitive Readout
MS/MEMS Co-design Flow
IP Integration Approach
Electrical
Simulation
Physical
Design
Analog (MixedSignal)
MEMS/Mixed-Signal Design Subflow
Top-down
Integration /
Publishing
Physical
Integration
IC System Specifications
Functional
Validation
MEMS
Specifications
SIPP-SIMPLI (SIPP MEMS
PLatform Integrator)
Top-down
Physical
Design
Digital
Bottomup
Electromechanical
Simulation
Electro-mechanical
CMOS MEMS Foundry Design Kit
MEMS Design Sub-flow
 MEMS design flow
is traditionally topdown starting from
mechanical
characteristics
with FEM iterations
 SIPP-SIMPLI
interface is
providing the
bridge between
MEMS and IC
designers
 IC design flow
integrate MEMS
components as IP
Outlines
 MS/MEMS Co-Design Flow Overview
 MEMS Design Sub-flow
 MEMS
HDL Behavioral Modeling
 Specification-Driven Verification
 DRC-aware Layout Generation
 MEMS-IP Publishing/Integration Interface (SIMPLI)
 Overview
 Database
Structure
 Code/Layout Encryption
 Electrical Parasitic Extraction
 Mixed-Signal Design Sub-flow
 Correlated
 Summary
Double Sampling Capacitive Readout
MEMS Design Sub-flow
Physical Design
P-Cell Layout Generator
Creation
FEM Simulations
N-DOF
Reduced-Order Model
(ROM)
GUI
GUI
Geometrical
Behavioral Macro Model
(MM)
Layout Generation
Optimization
Post-layout Sign-off
SIPP-SIMPLI (SIPP MEMS PLatform Integrator)
IC System Specifications
Electro-mechanical
Simulation
Top-down
MEMS Design Sub-flow
Electro-mechanical
CMOS MEMS Foundry Design
Kit
Top-down approach
MEMS Design Sub-flow Details
Interleaved Interaction
MEMS
Design
Data
Input
1A
MEMS
Design
Specifica
tions
MEMS Top-down Functional Design
2A
MEMS
Executable
Specifications
Creation
3A
MEMS
Topology
Selection
4A
Geometrical/
Mechanical
Nominal Design
5A
Nominal FiniteElement
Verification
2B
MEMS Design
Validation
Strategy
6
Geometrical/
Mechanical
Models
Enhancement
7A
Nominal/
Statistical
Verification with
Enhanced
Models
7B
Geometrical/
Mechanical
Design
Optimization
8A
Finite-Element
Sign-off
8B
N-DOF
Reduced-order
Model
Generation
MEMS Top-down Physical Design
1B
Foundry
Design Kit
(180nm)
5B
MEMS Block
Early
Design Rule
Checking
2C
Auxiliary DRC
Rules Creation
3B
P-Cells Creation
4B
MEMS Layout
Nominal Design
Generation
7C
MEMS Layout/
Abstract Final
Design
Generation
8C
MEMS Block
Final
Design Rule
Checking
8D
MEMS Block
Electrical
Parasitic
Extraction
9
MEMS IP
Packaging
MEMS HDL Macro-Modeling (1)
Interfacing multi-physics, electrical and MEMS geometries
 Advantages of HDL
behavioral modelling for
MEMS:

Parameters governing
accelerometer geometrical
dependancies



MEMS electrical ports
corresponding to silicon ports
Substrate connection port name
Mechanical ports expressed in
VHDLAMS displacement type

Multi-disciplinary language
combining physics and
electrical quantities
Open standard to enable
re-use and flexible mixedsignal simulation
environment
Ability to create highly
parameterizable
component libraries
MEMS geometrical
structure description can
be part of the macro-model
Natural convergence
toward mixed-signal and
digital verification
MEMS HDL Macro-Modeling (2)
Describing multi-physics equivalence with electrical
Expression of external force
induced on the proof mass
due to acceleration and
electrostatic interaction of
proof mass in motion
 Each physical
equations can be stated
independently and HDL
concurrent process
statement enables
system solution
convergence
 No limit to describe 2nd,
3rd order effects but at
expense of
development time
Electrical behaviour
implemented as induced
capacitance on electrical
ports
 Models can be further
enhanced based on
results extracted from
FEM simulation
MEMS Functional Verification cockpit
Specification-driven verification
Testbench bank and
simulation analysis
definition
Global variables
Specifications captured
as expressions,
waveforms or postprocessing scripts
Specification
boundaries
MEMS Functional Validation
Re-usable and scalable verification environment
Specification failure
Sensitivity defines
as F/g
Optimum
geometrical
parameter value
Specification
passed
 Single specificationdriven environment
for:
 Re-use and
automation of
verification tasks
 Synthetic view of
design status
versus
specification target
 Testing
environment can
be hierarchical
 Use model similar
to digital functional
verification
MEMS Physical Design
DRC aware parameterizable layout generator
Spring Beams Width
Finger Width
Finger Length
Eatch Hole Separation
Length
Initial Displacement
Eatch Hole Width
Length
Electrode-to-Mass Separation
Length
 SKILL based PCell enables
parameterization over
geometrical parameters with
DRC awareness
 Parameterization linked directly
to HDL macro-modelling in order
to enabled schematic-driven
layout
Outlines
 MS/MEMS Co-Design Flow Overview
 MEMS Design Sub-flow
 MEMS
HDL Behavioral Modeling
 Specification-Driven Verification
 DRC-aware Layout Generation
 MEMS-IP Publishing/Integration Interface (SIMPLI)
 Overview
 Database
Structure
 Code/Layout Encryption
 Electrical Parasitic Extraction
 Mixed-Signal Design Sub-flow
 Correlated
 Summary
Double Sampling Capacitive Readout
SIPP-SIMPLI Subflow concept
Physical Integration
Encrypted ElectricalMechanical Model
MEMS Black-box Abstract
Silicon Calibrated Model
Black-box Physical
Verification
Electrical Parasitic Network
GUI
GUI
Functional Validation
Layout Sign-Off
MEMS/Mixed-Signal Design Sub-flow
IC System Specifications
SIPP-SIMPLI (SIPP MEMS PLatform Integrator)
Integration / Publishing
MEMS Design Sub-flow
MEMS Specifications
CMOS MEMS Foundry Design
Kit
IP publishing and integration
SIPP-SIMPLI MEMS IP Publishing Subflow
Automated approach
Required MEMS IP input files
Functional
Description
Files
GDSII
Files
Specification
Files
SIMPLI Library
Processor
Target
PDK
Symbol
View
Layout
View
Symbol
Generation
Layout
Generation
Measurement
Files
Assura
customization
CDL
Netlist
Layout
GDSII File
DRC
Abstract
View
Spice
Black-box
Spectre
Black-box
CDL Blackbox
Functional
View
Auxiliary Virtuoso not shipped
Coupled C
extraction
Abstract
Generation
Spice,
Spectre
coupled C
Netlists
Abstract
LEF File
Blackboxing
Functional
View
LEF
Files
Encrypted
Functional
File
 SIPP-SIMPLI operated
on standard inputs and
generates views
required for MixedSignal design within
Cadence environment
 SIPP-SIMPLI requires
following Cadence tools:
 AMS Incisive for
processing HDL
models
 Abstract Generator
for black-box layout
generation
 Assura for MEMS
DRC compliance
 QRC for MEMS
parasitics extraction
SIPP-SIMPLI MEMS IP Integration Subflow
Automated approach
 Only Virtuoso views
have to be re-created in
target PDK which might
be packaged differently
between MEMS IP
provider and end-user
Required MEMS IP
package
SIMPLI MEMS
Package
Target PDK
Symbol
View
SIMPLI Library
Processor
Symbol
Generation
Abstract
Generation
Spice
Black-box
Spectre
Black-box
CDL Blackbox
Assura
customization
Abstract
View
Blackboxing
Functional
Functional
View
 If PDK package identical
between MEMS IP
provider and IC designer
then MEMS IP published
by SIPP-SIMPLI can be
re-used as-is
SIPP-SIMPLI Virtuoso Custom Interface
Single interface for publishing and integration
 Single interface and
options for both
publishing and
integration
 Interface integrated
directly with Virtuoso
platform and
compatible with both
IC 5.1.41 and IC 6.1.3
 Support batch
processing through
SKILL APIs for entire
library management
and maintenance
SIPP-SIMPLI Layout Processing
Layout black-boxing while enabling accurate integration
Before
SIPP-SIMPLI
After
Abstract with
antenna information
SIPP-SIMPLI Functional Processing
HDL description encrypted while enabling accurate simulation
Before
SIPP-SIMPLI
After
RSA encrypted code
readable in AMS
Designer
SIPP-SIMPLI Extraction Processing
Layout extraction while enabling accurate parasitics
Before
SIPP-SIMPLI
After
“Air”
Sensor harness capacitance
Vibrating
connecting to
sensor floating
CMOS
normal CMOS
in air dielectric
capacitance
substrate
Outlines
 MS/MEMS Co-Design Flow Overview
 MEMS Design Sub-flow
 Overview
 MEMS HDL Behavioral Modeling
 Specification-Driven Verification
 DRC-aware Layout Generation
 MEMS-IP Publishing/Integration Interface (SIMPLI)
 Overview
 Database Structure
 Code/Layout Encryption
 Electrical Parasitic Extraction
 Mixed-Signal Design Sub-flow
 Overview
 Correlated Double Sampling Capacitive Readout
 Design Summary
 Conclusion
CMOS Mixed-Signal MEMS Subflow
concept
Behavioral HDL + MEMS
Selection
Floorplan/Route + MEMS
Abstract
Calibrated HDL + ROM
Preliminary Estimate +
MEMS Abstract
FastSPICE + ROM
Post-layout Abstract +
MEMS Rule Set
Digital
Transistor + ROM
Pre-layout Abstract
Bottom-up
Physical Design
Mixed-level
Mixed-level
Electrical Simulation
IC System Specifications
MEMS/Mixed-Signal Design Sub-flow
Top-down
SIPP-SIMPLI (SIPP MEMS PLatform Integrator)
Analog (Mixed-Signal)
CMOS MEMS Foundry Design
Kit
Meet-in-the-middle approach
CMOS Mixed-Signal MEMS Subflow details
Meet-in-the-middle approach
IC Design
Data Input
1A
Design
Specificati
ons
1B
Modified
Foundry
Design Kit
(180nm)
IC Top-down Functional
Design
2
IC Design
Validation
Strategy
3
AMS Design
Partitioning
Bottom-up Functional and Physical
Design
5D
Digital
Hierarchical
RTL Design
9
IC Design
Functional
Performance
Validation
13
IC Post-layout
Validation
8A
Analog Block
Circuit
Optimization
10A
Analog Block
Physical
Estimation
12A
Analog Block
Physical Design
8B
Digital Block
Synthesis
10B
Digital Block
Physical
Estimation
12B
Digital Block
Physical Design
16
IC Design
Functional Signoff
14
Block Physical
Integration
Preparation
5E
MEMS IP
Import
1E
MEMS
packaged IP
1H
Legacy IP
7
IC Design
Re-specification
5C
Legacy and 3rd
Party
IP Import
1D
System-level
Testbenches
1G
3rd Party IP
5A
Analog Block
Circuit Design
5B
Analog Block
Behavioral
Design
1C
System-level
Models
1F
MEMS DFII
Testbenches
6A
IC Design
Functional
Concept
Validation
4
Block
Specifications
IC Top-down Physical
Design
6B
IC Design Early
Floorplanning
11
IC Refinement
Floorplanning
15
IC Design
Assembly
Correlated Double Sampling Readout
Φ1d
Inertial Sensor
Vrefp
Vrefn
Φ1d
Φ1d
Cf
Φ2
Φ1d
Φ2d
Φ2d
Cs
Vout
Φ1
 CDS circuit is suitable for capacitive sensor readout
 Offset
cancellation & Low frequency noise reduction
 Suitable for following Analog to Digital conversion
 Following another S/H amplifier for proper sensitivity
 Process: UMC CMOS-RF 180nm
Schematic Capture of Monolithic Integration
Parameterizable accelerometer
suitable for both simulation
optimization and schematicdriven layout
System output
Accelerometer
mechanical inputs
stimuli through
inherited connections
Switched-cap
sampling clock
Schematic-Driven Layout Assembly
Hierarchical layout while reducing LVS errors
Readout as plain
footprint
 Schematic-driven
layout enables to
track connectivity
between schematic
and layout view
 SIPP-SIMPLI creates
a connectivity aware
view for safe layout
integration
List of nets that
are completed
routed.
Opened MEMS
connections
MEMS accelorometer
as abstract
 Custom router could
be leveraged since
MEMS black-box as
connectivity and
antenna information
 SIPP-SIMPLI has
also LEF file for
digital P&R
integration
Design Summary
Specifications
Conditions
Value Unit
Sensor Input Range
Sampling Freq.
Sensitivity
SFDR
Resonate Freq.
Output RMS Noise
Vsupply = 3.3v
Vsupply = 3.3v
< 4kHz Vsupply = 3.3v
±2
<100
218
58.5
6.3
141
g
kHz
mv/g
dB
kHz
uV
Current Consumed
Vsupply = 3.3v
360
uA
Clock Freq. = 100KHz
The first result of accelerometer
(ACC) fabricated with .18mm 8”
CMOS foundry under the
constrain of standard CMOS
process.
[1] SEM of the ACC
[2] Movement of the fingers triggered by
external voltage source
[3] Capacitance variation under the excitation of shaker with
20~8kHz shaking. ( The green one is the "PZT reference
accelerometer“ provided as the reference and the blue one
is the performance of DUT.)
Outlines
 MS/MEMS Co-Design Flow Overview
 MEMS Design Sub-flow
 Overview
 MEMS HDL Behavioral Modeling
 Specification-Driven Verification
 DRC-aware Layout Generation
 MEMS-IP Publishing/Integration Interface (SIMPLI)
 Overview
 Data Structure
 Code/Layout Encryption
 Electrical Parasitic Extraction
 Mixed-Signal Design Sub-flow
 Overview
 Correlated Double Sampling Capacitive Readout
 Design Summary
 Conclusion
Conclusion
 A Mixed Signal-MEMS co-design flow is proposed for
CMOS/MEMS monolithic integration.
 A MEMS IP Publishing/Integration interface is
developed to enable handshaking between MEMS &
Mixed signal circuits.
 With parametric layout & HDL, MEMS/CMOS cooptimization can be achieved.
 A fully integrated CMOS monolithic accelerometer
has been implemented to demonstrate the proposed
design flow.
Q&A