TWEPP2012, 19 September 2012
The Belle II Silicon Vertex Detector
Readout Chain
Markus Friedl (HEPHY Vienna)
Introduction
Front-End
Junction Box
FADC
DAQ
Summary
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Introduction
Front-End
Junction Box
FADC
DAQ
Summary
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
3
KEKB and Belle @ KEK (1999-2010)
KEKB
~1 km in diameter
Belle
 Asymmetric machine:
8 GeV e- on 3.5 GeV e+
Belle
Linac
KEKB
About 60km northeast of Tokyo
 Center of mass energy: Y(4S) (10.58 GeV)
 High intensity beams (1.6 A & 1.3 A)
 Integrated luminosity of 1 ab-1 recorded in total
Linac
 Belle mentioned explicitly in 2008 Physics
Nobel Prize announcement to Kobayashi and
Masukawa
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Belle Detector (1999–2010)
SC solenoid
1.5 T
Aerogel Cherenkov counter
n=1.015~1.030
3.5 GeV e+
CsI(Tl)
16 X0
TOF
counter
8 GeV e-
Si vertex detector
4 layers DSSD
M.Friedl (HEPHY Vienna): Belle II SVD Readout
Central Drift
Chamber
small cell +He/C2H5
µ / KL detection
14/15 lyr. RPC+Fe
19 September 2012
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SuperKEKB/Belle II Upgrade: 2010–2015
 Aim: super-high luminosity ~81035 cm-2s-1  11010 BB / year
 LoI published in 2004; TDR published in 2010
 Refurbishment of accelerator and detector required

nano-beams with cross-sections of ~10 µm x 60 nm
 10 mm radius beam pipe at interaction region
http://belle2.kek.jp
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Previous SVD Layout (until 2010)
20
[cm]
10
0
-30
layers 4
-20
3
2
1
-10
0
10
20
30
40
[cm]
 4 straight layers of 4" double-sided silicon detectors (DSSDs)
 Outer radius of r~8.8 cm
 Up to three 4” sensors are
daisy-chained and read out
by one hybrid located outside
of acceptance region (VA1 chip)
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Belle Silicon Vertex Detector (SVD)
 Previous SVD limitations were
 occupancy (~10% in innermost layer)
 need faster shaping
 dead time (~3%)
 need faster readout and pipeline
10%
 Belle II needs detector with
 high background tolerance
 pipelined readout
 robust tracking
 low material budget in active volume
M.Friedl (HEPHY Vienna): Belle II SVD Readout
L1
10%
L2
L3
L4
Current SVD is not suitable
for Belle II
19 September 2012
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New Layout for Belle II SVD (2015-)
20
[cm]
10
layers
6
5
4
4 layers of doublesided strip sensors
3
0
-30
Two layers of DEPFET pixels
1+2
-20
-10
0
10
20
30
40
[cm]
 New double-layer pixel detector
using DEPFET technology
 Four layers with 6” double-sided strip
detectors and forward part

Optimized for precision vertex
reconstruction of the decays of short-lived
B-mesons
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Sensor underneath flex circuit
End ring (support)
APV25 chips
Origami ladder
Pitch adapter bent
around sensor edge
Cooling pipe
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Readout Chain Overview
 Analog APV25 readout is through copper cable to FADCs
 Junction box provides LV to front-end
Finesse Transmitter
Board (FTB)
FADC
~2m Junction ~10m
copper
box
copper
cable
cable
Unified optical
data link (>20m)
COPPER
1748
APV25
chips
Front-end
hybrids
Rad-hard
DC/DC
converters
Analog level translation,
data sparsification and
hit time reconstruction
M.Friedl (HEPHY Vienna): Belle II SVD Readout
Unified Belle II
DAQ system
19 September 2012
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Not Entirely New…
 2007: plans for an intermediate upgrade of Belle I SVD
 Prototype system built and tested thoroughly in several
beam tests since then
 Now enlarging and improving details, but concept is same
 See reports at previous TWEPPs for details & performance
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Introduction
Front-End
Junction Box
FADC
DAQ
Summary
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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APV25 Readout Chip
Schematics of one channel








Developed for CMS (LHC) by IC London and RAL (70k chips installed)
0.25 µm CMOS process (>100 MRad tolerant)
40 MHz clock (adjustable), 128 channels
192 cell analog pipeline  no dead time
50 ns shaping time  low occupancy
Noise: 250 e + 36 e/pF  must minimize capacitive load!!!
Multi-peak mode (read out several samples along shaping curve)
Thinning to 100µm successful
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Front-End Hybrids
 2 variants
 Standard PCBs outside acceptance for the edge sensors
 “Origami” chip-on-sensor concept for inner sensors
See presentation by C. Irmler today at 14:50
Martin Wood Lecture Theater
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Introduction
Front-End
Junction Box
FADC
DAQ
Summary
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Junction Box: Mother Board
 Junction box board with CERN
DC/DC converters to be placed
in SVD DOCK boxes
 Converter boards now have a
commercial chip, to be replaced
by the rad-hard AMIS5 chip
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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DC/DC Converter: Noise Comparison
600
APV25 Noise (old hybrid only)
DC/DC
500
DC/DC
400
Noise [e]
400
Noise [e]
APV25 Noise (new hybrid only)
Conventional
Conventional
(known
problem)
500
600
300
300
200
200
100
100
0
0
0
1
APV#
2
3
Test hybrid
(larger)
0
1
APV#
2
3
Belle II design
(smaller)
 Same noise within measurement precision (few %) between
conventional and DC/DC powering!
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Junction Box: Draft Design
 (Top lid not
shown)
 As in Belle 1 SVD:
Located ~2m from
front-end (outside
acceptance) =
radiation zone
 Mostly aluminum,
only bottom plate
copper (to be
cooled)
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Introduction
Front-End
Junction Box
FADC
DAQ
Summary
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Readout Electronics: Scheme
 No direct connection between
power supplies and FADC
 Bias currents are measured
remotely by FADC
Power Supplies
(floating)
HV
LV
APV25
FADC
Detector
Junction
Box
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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FADC Block Diagram
Jitter
Cleaner
Delay
CLK
Controls
V/I
Monitoring
Junction Box
FIR
ADCs
Signals
Level Translation
Controls
Central
FPGA
VME
FPGA
Slow
Controls
Data
Data
FADC Controller
VME bus
GbE
FTB
HV LV
 Analog & digital level translation between  bias and GND
 Digitization, signal conditioning (FIR filter), data processing
 Central FPGA is an Altera Stratix IV GX
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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FADC: Overall Concept
 Similar to
Indicator
LEDs
VME
Altera
P1
Delay
Analog
level
translation
Bus
ADCs
CLK
distribution
Stratix 4 GX
daughter board
Jitter
Cleaner
Hybrid
Connectors
P2
FE control
& monitoring
Digital
(controls)
level
translation
GbE
Delay
CLK
distribution
M.Friedl (HEPHY Vienna): Belle II SVD Readout
P3
Belle 1 SVD
FADC, but
with twice
higher
density (48
APV25
inputs) and
more
powerful
FPGA
19 September 2012
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FADC: Level Translation Daughter Boards
 Analog board: existing design, but simplified
 Digital board: completely new design based on digital
isolator ICs (Analog Devices)
 No floating LV power needed for either board!
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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FADC: Level Translation Tests
APV25 Hybrid
Ana+Digi daughter boards
on adapter board
APVDAQ Repeater
 Both boards tested thoroughly, working perfectly fine 
 Short (2m) and long (12m) cable to FADC
 100V between floating and GND sides
 No damage with repeated instantaneous shorting of HV
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Introduction
Front-End
Junction Box
FADC
DAQ
Summary
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Finesse Transmitter Board (FTB)
 Sends FADC data
through optical
link to
 COPPER
 Pixel system (for
online data
reduction)
 Firmware in
development
Markus Friedl (HEPHY Vienna): Status of SVD
12 November 2011
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COPPER = Common Readout Platform
 Standardized 9U VME crate with CPU and network interface
 4 slots for FINESSE daughter boards (ADC, TDC, …)
according to subsystem needs
 In case of SVD: Belle2Link (Optical receiver)
Detector Signals
Local Bus
PCI Bus
Mezzanine Cards
FINESSE
FIFO
FINESSE
FIFO
Bridge
Bridge
PCI Mezzanine Cards
FINESSE
FIFO
Memory
FINESSE
FIFO
CPU
Control
Bridge
Trigger interrupt
Trigger input
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Introduction
Front-End
Junction Box
FADC
DAQ
Summary
M.Friedl (HEPHY Vienna): Belle II SVD Readout
19 September 2012
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Overall Readout System Scheme
 DAQ: PC Farm
DAQ
Copper
Finesse
Copper
Finesse
Copper
VME Crate
 COPPER: common
readout platform
3 more FADC crates
FTB
FADC_
Controller
 FADC system with
FTB
FADC
VME Crate
Buffer
FADC
FADC
Backplane Bus
HV + LV
Power
Junction
Board
Hybrid
Junction
Board
Hybrid
M.Friedl (HEPHY Vienna): Belle II SVD Readout
DOCK Box
optical link to
COPPER
 DOCK box with
DC/DC
 Front-End
19 September 2012
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Summary & Outlook
 Belle I  Belle II
 Needs completely new vertex detector (pixel + strips)
 Readout Chain
 Based on a 2007 design (for an earlier update option) 
 “Origami” chip-on-sensor concept for front-end with APV25
 Junction box near front-end with rad-hard DC/DC converters

 FADC with powerful FPGA for online signal processing
 Level translation daughter boards – working fine 
 DAQ link to common readout platform
 Will report on performance at next TWEPP 
 No noise penalty from switching power
M.Friedl (HEPHY Vienna): Belle II SVD Readout
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