VLSI Design
Circuits & Layout
Outline
 CMOS Gate Design
 Pass Transistors
 CMOS Latches & Flip-Flops
 Standard Cell Layouts
 Stick Diagrams
CMOS Gate Design
 A 4-input CMOS NOR gate
A
B
C
D
Y
Complementary CMOS
 Complementary CMOS logic gates
 nMOS pull-down network
 pMOS pull-up network
 a.k.a. static CMOS
inputs
pM O S
pull- up
netw or k
output
nM O S
pull- dow n
netw or k
Pull-up OFF
Pull-up ON
Pull-down OFF
Z (float)
1
Pull-down ON
0
X (crowbar)
Series and Parallel
a
a
0
g1
g2
(a)
 pMOS: 0 = ON
 Series: both must be ON
 Parallel: either can be ON
g2
b
OF F
OF F
OF F
ON
a
a
a
a
0
1
0
1
a
(d)
b
b
b
b
ON
OF F
OF F
OF F
a
a
a
a
0
( c)
b
1
b
1
b
g2
0
b
1
a
g1
1
1
0
(b)
g2
1
0
b
g1
a
b
a
g1
a
0
0
b
 nMOS: 1 = ON
a
0
0
1
1
0
1
1
b
b
b
b
OF F
ON
ON
ON
a
a
a
a
0
0
0
1
1
0
1
1
b
b
b
b
ON
ON
ON
OF F
Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate



Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS
Y
A
B
 Rule of Conduction Complements


Pull-up network is complement of pull-down
Parallel -> series, series -> parallel
Compound Gates
 Compound gates can do any inverting function
 Ex: AND-AND-OR-INV
Y  ( A  B )  (C  D )
(AOI22)
A
C
A
C
B
D
B
D
( a)
A
( b)
B C
( c)
D
A
B
( d)
C
D
A
B
A
C
B
D
A
B
C
D
Y
( e)
C
D
( f)
Y
Example: O3AI

Y  (A  B  C) D
Example: O3AI

Y  (A  B  C) D
A
B
C
D
Y
D
A
B
C
Pass Transistors
 Transistors can be used as switches
g
s
d
g
s
d
Pass Transistors
 Transistors can be used as switches
g =0
g
s
s
Input
d
d
0
g =1
s
d
s
s
Output
strong 0
g =1
g =0
g
g =1
1
Input
d
degraded 1
g =0
0
Output
degraded 0
d
g =1
s
g =0
d
strong 1
Signal Strength
 Strength of signal

How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0

But degraded or weak 1
 pMOS pass strong 1

But degraded or weak 0
 Thus NMOS are best for pull-down network
 Thus PMOS are best for pull-up network
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
Input
g = 0, gb = 1
g
a
a
b
a
b
gb
b
a
g
b
gb
g = 1, gb = 0
strong 1
1
b
g
g
a
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
gb
Output
a
b
gb
Tristates
 Tristate buffer produces Z when not enabled
EN
EN
A
Y
0
0
Z
0
1
Z
1
0
0
1
1
1
Y
A
EN
Y
A
EN
Nonrestoring Tristate
 Transmission gate acts as tristate buffer
 Only two transistors
 But nonrestoring
 Noise on A is passed on to Y (after several stages, the
noise may degrade the signal beyond recognition)
EN
A
Y
EN
Tristate Inverter
 Tristate inverter produces restored output
 Note however that the Tristate buffer

ignores the conduction complement rule because we want a
Z output
A
EN
Y
EN
Tristate Inverter
 Tristate inverter produces restored output
 Note however that the Tristate buffer

ignores the conduction complement rule because we want a
Z output
A
A
A
EN
Y
Y
Y
EN = 0
Y = 'Z '
EN = 1
Y =A
EN
Multiplexers
 2:1 multiplexer chooses between two inputs
S
D1
D0
0
X
0
0
X
1
1
0
X
1
1
X
S
Y
D0
0
Y
D1
1
Multiplexers
 2:1 multiplexer chooses between two inputs
S
D1
D0
Y
0
X
0
0
0
X
1
1
1
0
X
0
1
1
X
1
S
D0
0
Y
D1
1
Gate-Level Mux Design

D

S
D
(
t
o
o
m
a
n
y
t
r
a
n
s
i
s
t
o
r
s
)
1
0
 YS
 How many transistors are needed?
Gate-Level Mux Design

D

S
D
(
t
o
o
m
a
n
y
t
r
a
n
s
i
s
t
o
r
s
)
1
0
 YS
 How many transistors are needed? 20
D1
S
D0
Y
D1
S
D0
4
2
4
2
4
2
2
Y
Transmission Gate Mux
 Nonrestoring mux uses two transmission
gates
Transmission Gate Mux
 Nonrestoring mux uses two transmission
gates

Only 4 transistors
S
D0
S
Y
D1
S
Inverting Mux
 Inverting multiplexer



Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
 Noninverting multiplexer adds an inverter
D0
S
S
D1
D0
D1
S
S
Y
S
S
S
Y
S
D0
0
Y
S
D1
1
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two
selects
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two
selects


Two levels of 2:1 muxes
Or four tristates
S1S0 S1S0 S1S0 S1S0
D0
S0
D0
0
D1
1
S1
D1
0
Y
Y
D2
0
D3
1
1
D2
D3
D Latch
 When CLK = 1, latch is transparent
 Q follows D (a buffer with a Delay)
 When CLK = 0, the latch is opaque
 Q holds its last value independent of D
 a.k.a. transparent latch or level-sensitive latch
D
Latch
C LK
C LK
D
Q
Q
D Latch Design
 Multiplexer chooses D or old Q
C LK
D
1
C LK
Q
Q
Q
D
Q
0
C LK
Old Q
C LK
C LK
D Latch Operation
Q
D
C LK = 1
C LK
D
Q
Q
Q
D
C LK = 0
Q
D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-
slave flip-flop
C LK
C LK
D
F lop
D
Q
Q
D Flip-flop Design
 Built from master and slave D latches
C LK
C LK
C LK
QM
Q
D
C LK
QM
Latch
Latch
D
C LK
C LK
C LK
C LK
Q
C LK
A “negative level-sensitive” latch
C LK
A “positive level-sensitive” latch
D Flip-flop Operation
Inverted version of D
D
QM
Q
C LK = 0
Holds the last value of NOT(D)
D
QM
Q
Q -> NOT(NOT(QM))
C LK = 1
C LK
D
Q
Race Condition
 Back-to-back flops can
malfunction from clock skew



Second flip-flop fires Early
Sees first flip-flop change
and captures its result
Called hold-time failure or
race condition
Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races

As long as nonoverlap exceeds clock skew
 Good for safe design

Industry manages skew more carefully instead
2
1
QM
Q
D
2
2
2
1
2
1
1
1
Gate Layout
 Layout can be very time consuming



Design gates to fit together nicely
Build a library of standard cells
Must follow a technology rule
 Standard cell design methodology




VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
Example: Inverter
Layout using Electric
Inverter, contd..
Example: NAND3
 Horizontal N-diffusion and p-diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom
 32  by 40 
NAND3 (using Electric), contd.
Stick Diagrams
 Stick diagrams help plan layout quickly


Need not be to scale
Draw with color pencils or dry-erase markers
Stick Diagrams
 Stick diagrams help plan layout quickly


Need not be to scale
Draw with color pencils or dry-erase markers
VDD
Vin
Vout
GND
Wiring Tracks
 A wiring track is the space required for a wire

4  width, 4  spacing from neighbor = 8 
pitch
 Transistors also consume one wiring track
Well spacing
 Wells must surround transistors by 6 


Implies 12  between opposite transistor flavors
Leaves room for one wire track
Area Estimation
 Estimate area by counting wiring tracks

Multiply by 8 to express in 
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area

Y  (A  B  C) D
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area

Y  (A  B  C) D
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area

Y  (A  B  C) D