Design of Two-Level Multiple-Output Networks
Design a network with four inputs and three
outputs which realizes the functions
F1(A,B,C,D) = S m(11,12,13,14,15)
F2(A,B,C,D) = S m(3,7,11,12,13,15)
F3(A,B,C,D) = S m(3,7,12,13,14,15)
AB
AB
1
Direct Realization
(each function as a min.
sum of prime implicants)
Note: AB is common to F1, F3
= AB+ACD
Multiple-Output
Realization
= ABC’+A’CD+ACD
= A’CD+AB
2
Example: Using Common Terms in Multiple Output Network
Design
f1 = a’bd + abd+ab’c’ + b’c
f2 = c + a’bd
f3 = bc + ab’c’ + abd
8 gates, 22 gate inputs
3
Another Example
Best Soln.
Soln. Requires
extra gate
4
Another Example
Soln. with max.
number of common
terms (8 gates, 26
inputs)
Best Soln.has no
common terms
(7 gates, 18 inputs)
5
Code Converters
 Code converters – take an input code, translate to its
equivalent output code.
Input
code
Code
converter
Output
code
 Example: BCD to Excess-3 Code Converter.
Input: BCD digit
Output: Excess-3 digit
6
BCD-to-Excess-3 Code Converter
 Truth table:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BCD
B C
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Excess-3
W X Y Z
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
W = S m(5,6,7,8,9)
x = S m(1,2,3,4,9)
y = S m(0,3,4,7,8)
z = S m(0,2,4,6,8)
7
W = Sm(5,6,7,8,9)+
Sd(10,11,12,13,14,15)
= a+bc+bd = a+b(c+d)
AB
CD 00 01 11
00
0
4 x12
01
1 1 5 x13
11
3 1 7 x15
10
2 1 6 x14
10
18
19
x 11
x10
y = Sm(0,3,4,7,8)+
Sd(10,11,12,13,14,15)
= c’d’+cd
AB
CD 00 01 11
00 1 0 1 4 x12
01
1
5 x13
11 1 3 1 7 x15
10
2
6 x14
10
18
9
x 11
x10
x =Sm(1,2,3,4,9)+
Sd(10,11,12,13,14,15)
bc’d’+b’d+b’c=bc’d’+b’(c+d)
AB
CD 00 01 11
00
0 1 4 x12
01 1 1 5 x13
11 1 3 7 x15
10 1 2 6 x14
10
08
19
x 11
x10
Underlined
terms are
common
z = Sm(0,2,4,6,8)+
Sd(10,11,12,13,14,15)
AB = d’
CD 00 01
00 1 0 1 4
01
1
5
11
3
7
10 1 2
11
x12
x13
x15
1 6 x14
10
18
9
x 11
x10
8
Multi-Output NAND and NOR Networks
(a) Network of AND and OR gates
(b) NOR network
Conversion to a
network of all
NAND or all
NOR gates can
also be done for
the case of
multiple-output
networks, using
method of Section
8.6, p. 194
9
Multiplexers
2/1 Multiplexer (MUX)
Data
Inputs
I0
I1
Z
if S = 0, then Z = I0
if S = 1, then Z = I1
S
Control Input
S is the Control Input
used to select one of the
data inputs I0 , I1 and
connect it to the output
terminal, Z.
I0
S’
Logic Diagram
Z
I1
S
Z = I0S’ + I1S
10
Higher Order Muxes
4/1 Mux
8/1 Mux
I0
I1
I2
I3
I4
I5
I6
I7 S[2:0]
I0
I1
Z
I2
I3 S1 S0
if S = “00”, then Z = I0
if S = “01”, then Z = I1
if S = “10”, then Z = I2
if S = “11”, then Z = I3
Z
3
Z = I0 S1’ S0’ + I1 S1’ S0 + I2 S1 S0’ + I3 S1 S0
Note: S[2:0] means the three control inputs S2 S1 S0 <--lsb
11
Logic Diagram for 8-to-1 Multiplexer
12
Muxes are often used
to select groups of bits
arranged in busses.
S
A[3:0]
I0
Z
B[3:0]
I1
A0
B0
I0
I1
A1
B1
I0
I1
A2
B2
I0
I1
A3
B3
I0
I1
Z
Z0
Z
Z1
Z
Z2
Z
Z3
S
S
D[3:0]
S
To build a 2/1 mux for 4bit wide busses, need four
1-bit 2/1 muxes.
S
S
13
Function Realization using MUX
A 4-to-1 MUX can realize any 3-variable function with no added
Logic gates.
Example:
Realize F(A,B,C)= A’B’ + AC
Soln.: Expanding F so that all terms include both control inputs,
A and B, yields
F = A’B’ + AC(B’+B) = A’B’1 + AB’C + ABC
The general eqn. For 4-to-1 MUX is
F = A’B’I0 + A’BI1+ AB’I2+ ABI3
Comparing eqns.
We see they will be identical if
I0 =1, I1 =0, I2 =C, I3 =C
14
Function Realization using MUX
Example: Consider the function
Z(A,B,C,D) = Sm(0,1,3,6,7,8,11,12,14) and implement it
using an 8-to-1MUX
Soln.: Assume that A,B,C are applied to control inputs s2,s1,s0 resp.
Then all 16 possible minterms that can be generated by the MUX can be
represented in a table.
I0
I1
I2
I3
I4
I5
I6
I7
000 001 010 011 100 101 110 111
D’ 0
2
4
6
8 10
12 14
D
1
1
3
D
5
0
7
1
9
D’
11
D
13
D’
15
D’
Working out the bottom row tells us what to apply to I0, I1, 12, etc.
How to work it out? e.g. I0 col  D’+D=1, I1 col only minterm with D appears,
(apply D), I2 col no minterms used (apply 0), I3 col D’+D=1,
I4 col. only minterm with D’ appears(apply D’).
15
Example: Continued
The function is then realized with an 8-to-1 MUX
with ABC applied to the control inputs and the values
found in the table to I0, I1, I2, etc.
S2 S1 S0
16
Example: Continued Alternate Solution
One-variable k-maps
Represent all of the minterms of Z on a k-map. Then obtain
groupings corresponding to [I0 = 000 with both D’ and D]
[I1=001 with both D’ and D] etc. Each of the two-minterm groupings
can be thought of as a 1-variable k-map in D only and simplified.
17
Example: Continued Yet anotherAlternate Solution
This time assume that A,B,D are applied to control inputs S2,S1,S0 resp.
I0
I1
I2
I3
I4
I5
I6
I7
000 001 010 011 100 101 110 111
C’ 0
1
4
5
8
9 12 13
C
2
C’
3
1
6
C
7
C
10
C’
11
C
14
1
15
0
C’
1
C
C
C’
C
1
0
Mux Realization with Control Inputs A, B, and D
S2 S1 S0
D
18
Example: Continued Yet anotherAlternate Solution using
external gates
I0
I1
I2
I3
00
00 0
01 1
11 3
10 2
01
4
5
7
6
10
8
9
11
10
11
12
13
15
14
CD
Table method in this case is
equivalent to four 2-variable
K-maps
19
Decoders
This decoder
generates all
minterms of of the
three input variables
Exactly one of the output
lines will be 1 for each
combination of the input
variables.
20
Decoders
7442 4-to-10 decoder
Note: Active low outputs
21
Realization of Multiple-Output Network using Decoder
f1 = (m1’m2’ m4’)’
= m1 + m2 + m4
f2 = (m4’m7’ m9’)’
=m4 + m7 + m9
Can realize a function by ORing together selected minterm outputs.
In this case outputs are active low, so NAND gates are used
(effectively ORing together these outputs).
22