Sequential Logic
Materials taken from: Digital Design and
Computer Architecture by David and Sarah
Harris &
The Essentials of Computer Organization and
Architecture by L. Null & J. Lobur
3.6 Sequential Circuits
• Combinational logic circuits are perfect for
situations when we require the immediate
application of a Boolean function to a set of inputs.
• There are other times, however, when we need a
circuit to change its value with consideration to its
current state as well as its inputs.
– These circuits have to “remember” their current state.
• Sequential logic circuits provide this functionality
for us.
2
3.6 Sequential Circuits
• As the name implies, sequential logic circuits require
a means by which events can be sequenced.
• State changes are controlled by clocks.
– A “clock” is a special circuit that sends electrical pulses
through a circuit.
• Clocks produce electrical waveforms such as the
one shown below.
3
3.6 Sequential Circuits
• State changes occur in sequential circuits only
when the clock ticks.
• Circuits can change state on the rising edge,
falling edge, or when the clock pulse reaches its
highest voltage.
4
3.6 Sequential Circuits
• Circuits that change state on the rising edge, or
falling edge of the clock pulse are called edgetriggered.
• Level-triggered circuits change state when the
clock voltage reaches its highest or lowest level.
5
3.6 Sequential Circuits
• To retain their state values, sequential circuits rely
on feedback.
• Feedback in digital circuits occurs when an output
is looped back to the input.
• A simple example of this concept is shown below.
– If Q is 0 it will always be 0, if it is 1, it will always be 1.
Why?
6
A Bistable Feedback Circuit
• Consider the two possible cases:
– Q = 0: then Q = 1 and Q = 0 (consistent)
1
0
I1
I2
– Q = 1: then Q = 0 and Q = 1 (consistent)
0
1
I1
I2
0
1
1
0
Q
Q
Q
Q
• Bistable circuit stores 1 bit of state in the state variable, Q (or
Q)
• But there are no inputs to control the state
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SR (Set/Reset) Latch
• SR Latch
R
S
N1
Q
N2
Q
• Consider the four possible cases:
–
–
–
–
S = 1, R = 0
S = 0, R = 1
S = 0, R = 0
S = 1, R = 1
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SR Latch Analysis
– S = 1, R = 0: then Q = 1 and Q = 0
R
S
0
1
N1
Q
N2
Q
– S = 0, R = 1: then Q = 0 and Q = 1
R
S
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3-<9>
1
0
N1
Q
N2
Q
SR Latch Analysis
– S = 1, R = 0: then Q = 1 and Q = 0
R
0
N1
1
Q
0
S
0
1
N2
0
Q
– S = 0, R = 1: then Q = 0 and Q = 1
R
1
N1
0
Q
1
S
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3-<10>
0
0
N2
1
Q
SR Latch Analysis
– S = 0, R = 0: then Q = Qprev
Qprev = 0
R
S
0
0
N1
0
Qprev = 1
N2
R
Q
Q
S
– S = 1, R = 1: then Q = 0 and Q = 0
R
S
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1
1
N1
Q
N2
Q
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0
0
N1
Q
N2
Q
SR Latch Analysis
– S = 0, R = 0: then Q = Qprev and Q = Qprev (memory!)
Qprev = 0
R
0
Qprev = 1
0
N1
R
Q
1
S
0
0
0
N1
1
Q
0
1
N2
Q
S
1
0
N2
0
Q
– S = 1, R = 1: then Q = 0 and Q = 0 (invalid state: Q ≠ NOT Q)
R
1
N1
0
Q
0
S
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0
1
N2
0
Q
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3.6 Sequential Circuits
• The SR latch actually
has three inputs: S, R,
and its current output, Q.
• Thus, we can construct
a truth table for this
circuit, as shown at the
right.
• Notice the two undefined
values. When both S
and R are 1, the SR
latch is unstable.
13
D Latch
• Two inputs: CLK, D
– CLK: controls when the output changes
– D (the data input): controls what the output changes to
• Function
– When CLK = 1, D passes through to Q (the latch is transparent)
– When CLK = 0, Q holds its previous value (the latch is opaque)
• Avoids invalid case when Q ≠ NOT Q
D Latch
Symbol
CLK
D
Q
Q
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D Latch Internal Circuit
CLK
D
R
S
D
CLK D
0
X
1
0
1
1
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D
R
CLK
Q Q
D
S
Q Q
S
R
Q
Q
Q
Q
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D Latch Internal Circuit
CLK
D
R
S
D
CLK D
0
X
1
0
1
1
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D
X
1
0
R
Q Q
CLK
D
S
Q Q
S
0
0
1
R
0
1
0
Q
Q
Q
Q
Qprev Qprev
0
1
1
0
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D Flip-Flop
• Two inputs: CLK, D
• Function
– The flip-flop “samples” D on the rising edge of CLK
• When CLK rises from 0 to 1, D passes through to Q
• Otherwise, Q holds its previous value
– Q changes only on the rising edge of CLK
• A flip-flop is called an edge-triggered device because it is
activated on the clock edge
D Flip-Flop
Symbols
D
Q
Q
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D Flip-Flop Internal Circuit
• Two back-to-back latches (L1 and L2) controlled by
complementary clocks
• When CLK = 0
– L1 is transparent
– L2 is opaque
– D passes through to N1
• When CLK = 1
– L2 is transparent
– L1 is opaque
– N1 passes through to Q
CLK
CLK
D D
L1
Q
Q
CLK
N1
D
Q Q
L2
Q Q
• Thus, on the edge of the clock (when CLK rises from 0 1)
– D passes through to Q
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3.6 Sequential Circuits
• If we can be sure that the inputs to an SR flip-flop
will never both be 1, we will never have an
unstable circuit. This may not always be the case.
• The SR flip-flop can be modified to provide a
stable state when both inputs are 1.
• This modified flip-flop is
called a JK flip-flop,
shown at the right.
-
The “JK” is in honor of
Jack Kilby.
19
3.6 Sequential Circuits
• At the right, we see
how an SR flip-flop
can be modified to
create a JK flip-flop.
• The characteristic
table indicates that
the flip-flop is stable
for all inputs.
20
Enabled Flip-Flops
• Inputs: CLK, D, EN
– The enable input (EN) controls when new data (D) is stored
• Function
– EN = 1
• D passes through to Q on the clock edge
– EN = 0
Internal
Circuit
• the flip-flop retains its previous state
EN
Symbol
CLK
0
D
D
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1
Q
Q
D
Q
EN
Resettable Flip-Flops
• Inputs: CLK, D, Reset
• Function:
– Reset = 1
• Q is forced to 0
– Reset = 0
• the flip-flop behaves like an ordinary D flip-flop
Symbols
D
Q
r
Reset
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3.6 Sequential Circuits
• This illustration shows a
4-bit register consisting of
D flip-flops. You will
usually see its block
diagram (below) instead.
A larger memory configuration is
shown on the next slide.
23
3.6 Sequential Circuits
24
3.6 Sequential Circuits
• A binary counter is
another example of a
sequential circuit.
• The low-order bit is
complemented at each
clock pulse.
• Whenever it changes
from 0 to 1, the next bit
is complemented, and
so on through the
other flip-flops.
25
Synchronous Sequential Logic Design
• Breaks cyclic paths by inserting registers
• These registers contain the state of the system
• The state changes at the clock edge, so we say the system is
synchronized to the clock
• Rules of synchronous sequential circuit composition:
–
–
–
–
Every circuit element is either a register or a combinational circuit
At least one circuit element is a register
All registers receive the same clock signal
Every cyclic path contains at least one register
• Common synchronous sequential circuits
– Finite State Machines (FSMs)
– Pipelines
– memory
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Finite State Machine (FSM)
• Consists of:
– State register that
• Store the current state and
• Load the next state at the clock edge
– Combinational logic that
• Computes the next state
• Computes the outputs
CLK
S’
Next
State
S
Current
State
Next State
Logic
CL
Next
State
Output
Logic
CL
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Outputs
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3.6 Sequential Circuits
• The behavior of sequential circuits can be
expressed using characteristic tables or finite state
machines (FSMs).
– FSMs consist of a set of nodes that hold the states of the
machine and a set of arcs that connect the states.
• Moore and Mealy machines are two types of FSMs
that are equivalent.
– They differ only in how they express the outputs of the
machine.
• Moore machines place outputs on each node, while
Mealy machines present their outputs on the
transitions.
28
Finite State Machines (FSMs)
• Next state is determined by the current state and the inputs
• Two types of finite state machines differ in the output logic:
– Moore FSM: outputs depend only on the current state
– Mealy FSM: outputs depend on the current state and the inputs
Moore FSM
inputs
M
next
state
logic
CLK
next
k state
k
state
output
logic
N
outputs
Mealy FSM
inputs
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M
next
state
logic
CLK
next
k state
k state
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output
logic
N
outputs
3.6 Sequential Circuits
• The behavior of a JK flop-flop is depicted below by
a Moore machine (left) and a Mealy machine
(right).
30
3.6 Sequential Circuits
• Although the behavior of Moore and Mealy
machines is identical, their implementations differ.
This is our Moore
machine.
31
3.6 Sequential Circuits
• Although the behavior of Moore and Mealy
machines is identical, their implementations differ.
This is our Mealy
machine.
32
Finite State Machine Example
• Traffic light controller
– Traffic sensors: TA, TB (TRUE when there’s traffic)
– Lights: LA, LB
Bravado
LA
Academic
Labs
TB
TA
LB
LA
TA
TB
Blvd.
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Dining
Hall
3-<33>
LB
Fields
Ave.
Dorms
FSM Black Box
• Inputs: CLK, Reset, TA, TB
• Outputs: LA, LB
CLK
TA
TB
Traffic
Light
Controller
Reset
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LA
LB
FSM State Transition Diagram
• Moore FSM: outputs labeled in each state
• States: Circles
Reset
• Transitions: Arcs
S0
LA: green
LB: red
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FSM State Transition Diagram
• Moore FSM: outputs labeled in each state
• States: Circles
TA
Reset
• Transitions: Arcs
TA
S0
LA: green
LB: red
S1
LA: yellow
LB: red
S3
LA: red
LB: yellow
S2
LA: red
LB: green
TB
TB
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FSM State Transition Table
Current
State
S
S0
TA
0
TB
X
S0
S1
S2
S2
1
X
X
X
X
X
0
1
S3
X
X
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Inputs
Next
State
S'
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FSM State Transition Table
Current
State
S
S0
TA
0
TB
X
Next
State
S'
S1
S0
S1
S2
S2
1
X
X
X
X
X
0
1
S0
S2
S3
S2
S3
X
X
S0
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Inputs
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FSM Encoded State Transition Table
Current State
S1
S0
Inputs
TA
TB
Next State
S'1
S'0
State
Encoding
0
0
0
0
0
1
X
X
S0
00
0
1
X
X
S1
01
1
1
0
0
X
X
0
1
S2
10
S3
11
1
1
X
X
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FSM Encoded State Transition Table
Current State
S1
S0
Inputs
TA
TB
Next State
S'1
S'0
State
Encoding
0
0
0
0
0
1
X
X
0
0
1
0
S0
00
0
1
X
X
1
0
S1
01
1
1
0
0
X
X
0
1
1
1
1
0
S2
10
S3
11
1
1
X
X
0
0
S'1 = S1  S0
S'0 = S1S0TA + S1S0TB
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FSM Output Table
Current State
S1
S0
0
0
0
1
1
0
1
1
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LA1
Outputs
LA0 LB1
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LB0
Output Encoding
green
00
yellow
01
red
10
FSM Output Table
Current State
S1
S0
0
0
0
1
1
0
1
1
LA1
0
0
1
1
Outputs
LA0 LB1
0
1
1
1
0
0
0
0
LA1 = S1
LA0 = S1S0
LB1 = S1
LB0 = S1S0
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3-<42>
LB0
0
0
0
1
Output Encoding
green
00
yellow
01
red
10
FSM Schematic: State Register
CLK
S'1
S1
S'0
S0
r
Reset
state register
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FSM Schematic: Next State Logic
CLK
TA
S'1
S1
S'0
S0
r
TB
Reset
S1
S0
inputs
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next state logic
state register
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FSM Schematic: Output Logic
CLK
S'1
LA1
S1
LA0
TA
S'0
S0
LB1
r
TB
Reset
S1
S0
inputs
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LB0
next state logic
state register
3-<45>
output logic
outputs
FSM Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Cycle 10
CLK
Reset
TA
TB
S'1:0
??
S1:0
??
S0 (00)
S1
LA1:0
??
Green (00)
Yellow (01)
LB1:0
??
Red (10)
0
S0 (00)
S1 (01)
S2
S3
(10)
(01)
(11)
S2 (10)
S3 (11)
Red (10)
10
15
25
TA
Reset
S0
LA: green
LB: red
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20
S3
LA: red
LB: yellow
TA
S1
LA: yellow
LB: red
S2
LA: red
LB: green
TB
TB
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30
S1
(01)
S0 (00)
Green (00)
Green (00)
5
S0 (00)
Yellow (01) Red (10)
35
40
45
t (sec)
FSM State Encoding
• Binary encoding: i.e., for four states, 00, 01, 10, 11
• One-hot encoding
–
–
–
–
–
One state bit per state
Only one state bit is HIGH at once
I.e., for four states, 0001, 0010, 0100, 1000
Requires more flip-flops
Often next state and output logic is simpler
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Moore vs. Mealy FSM
• Alyssa P. Hacker has a snail that crawls down a paper tape
with 1’s and 0’s on it. The snail smiles whenever the last four
digits it has crawled over are 1101. Design Moore and Mealy
FSMs of the snail’s brain.
Copyright © 2007 Elsevier
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State Transition Diagrams
Moore FSM
reset
1
S0
0
1
1
0
S1
0
0
1
S2
0
S3
0
1
0
S4
1
0
0
Mealy FSM: arcs indicate input/output
Mealy FSM
reset
1/1
1/0
S0
1/0
S1
0/0
S2
1/0
0/0
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0/0
3-<49>
S3
0/0
Moore FSM State Transition Table
Current State Inputs Next State
S2
S1
S0
A
0
0
0
0
State
Encoding
0
0
0
1
0
0
1
0
S0
000
0
0
1
1
S1
001
0
1
0
0
S2
010
0
1
0
1
S3
011
0
1
1
0
0
1
1
1
S4
100
1
0
0
0
1
0
0
1
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S'2
S'1
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S'0
Moore FSM State Transition Table
Current State Inputs Next State
S2
S1
S0
A
S'2
S'1
S'0
0
0
0
0
0
0
0
State
Encoding
0
0
0
1
0
0
1
0
0
1
0
0
0
0
S0
000
0
0
1
1
0
1
0
S1
001
0
1
0
0
0
1
1
S2
010
0
1
0
1
0
1
0
S3
011
0
1
1
0
0
0
0
0
1
1
1
1
0
0
S4
100
1
0
0
0
0
0
0
1
0
0
1
0
1
0
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3-<51>
Moore FSM Output Table
Current State
S2
S1
S0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
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Output
Y
3-<52>
Moore FSM Output Table
Current State
S2
S1
S0
Output
Y
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
1
0
0
1
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3-<53>
Y = S2
Mealy FSM State Transition and Output Table
Current State
Input
Next State
S1
S0
A
0
0
0
State
Encoding
0
0
1
S0
00
0
1
0
0
1
1
S1
01
1
0
0
S2
10
1
0
1
S3
11
1
1
0
1
1
1
Copyright © 2007 Elsevier
S'1
S'0
Output
3-<54>
Y
Mealy FSM State Transition and Output Table
Current State
Input
Next State
Output
S1
S0
A
S'1
S'0
Y
0
0
0
0
0
0
State
Encoding
0
0
1
0
1
0
S0
00
0
1
0
0
0
0
0
1
1
1
0
0
S1
01
1
0
0
1
1
0
S2
10
1
0
1
1
0
0
S3
11
1
1
0
0
0
0
1
1
1
0
1
1
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3-<55>
Moore FSM Schematic
A
CLK
S'2
S2
S'1
S1
S'0
S0
Reset
S2
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S1
S0
3-<56>
Y
Mealy FSM Schematic
A
CLK
S'1
S1
S'0
S0
Reset
S1
S0
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3-<57>
Y
Moore and Mealy Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
1
1
1
0
1
1
0
Cycle 9 Cycle 10
CLK
Reset
A
0
1
Moore Machine
S
??
S0
S1
S2
S3
S2
S4
S2
S3
S4
S0
S1
S2
S3
S1
S0
Y
Mealy Machine
S
??
S0
S1
S2
S3
S2
Y
Copyright © 2007 Elsevier
3-<58>
FSM Design Procedure
•
•
•
•
•
Identify the inputs and outputs
Sketch a state transition diagram
Write a state transition table
Select state encodings
For a Moore machine:
–
–
•
For a Mealy machine:
–
•
•
Rewrite the state transition table with the selected state encodings
Write the output table
Rewrite the combined state transition and output table with the selected
state encodings
Write Boolean equations for the next state and output logic
Sketch the circuit schematic
Copyright © 2007 Elsevier
3-<59>