55:035
Computer Architecture and Organization
Lecture 4
Outline


HDL Overview
Why not use “C”?

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Concurrency
Hardware datatypes / Signal resolution
Connectivity / Hierarchy
Hardware simulation
SystemVerilog Introduction
Datapaths and Control Paths
Moore and Mealy State Machines
Examples
State Encoding
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HDL Overview

Hardware Description Languages

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Can model “real” hardware (synthesizable)
Can model behavior (e.g. for test)
Most widely used are VHDL and VerilogHDL


Used to model digital systems
Can model anything from a simple gate to a complete system
Support design hierarchy
Support Hardware Design Methodology
Both are non-proprietary, IEEE standards
Behavioral and structural coding styles
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Basic Design Methodology
Requirements
RTL Model
Device Libraries
Synthesize
Gate-level
Model
ASIC or FPGA
Simulate
Simulate
Test Bench
Place & Route
Timing
Model
Simulate
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Why Not Use C or C++?

HDLs need to support characteristics of “real”
hardware

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HDLs must support hardware simulation


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Concurrency
Hardware datatypes / Signal resolution
Connectivity / Hierarchy
Circuit timing
Time
Cycle-accurate or Event-driven (for simulation speed)
Note: C++ has been extended for hardware

SystemC
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Basic Comparison
Verilog
 Similar to C
 Popular in commercial,
on coasts of US
 Designs contained in
“module”s
VHDL
 Similar to Ada
 Popular in Military,
midwest US
 Designs contained in
“entity” “architecture”
pairs
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Concurrency

HDLs must support concurrency


Real hardware has many circuits running at the same
time!
Two basics problems


Describing concurrent systems
Executing (simulating) concurrent systems
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Describing Concurrency

Many ways to create concurrent circuits

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
initial/always (Verilog) and process (VHDL) blocks
Continuous/concurrent assignment statements
Component instantiation of other modules or
entity/architectures
These blocks/statements execute in parallel in
every VHDL/Verilog design
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Executing Concurrency
Simulations are done on a host computer
executing instructions sequentially
 Solution is to use time-sharing



Each process or always or initial block gets the
simulation engine, in turn, one at a time
Similar to time-sharing on a multi-tasking OS,
with one major difference


There is no limit on the amount of time a given
process gets the simulation engine
Runs until process requests to give it up (e.g. “wait”)
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Process Rules

If the process has a sensitivity list, the process is
assumed to have an implicit “wait” statement as
the last statement


Execution will continue (later) at the first statement
A process with a sensitivity list must not contain
an explicit wait statement
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Sensitivity List
With Explicit List
Without Explicit List
XYZ_Lbl: process (S1, S2)
begin
S1 <= ‘1’;
S2 <= ‘0’ after 10 ns;
end process XYZ_Lbl;
XYZ_Lbl: process
begin
S1 <= ‘1’;
S2 <= ‘0’ after 10 ns;
wait on S1, S2;
end process XYZ_Lbl;
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Incomplete Sensitivity Lists

Logic simulators use
sensitivity lists to know
when to execute a
process



Perfectly happy not to
execute proc2 when “c”
changes
Not simulating a 3-input
AND gate though!
What does the
synthesizer create?
-- complete
proc1: process (a, b, c)
begin
x <= a and b and c;
end process;
-- incomplete
proc2: process (a, b)
begin
x <= a and b and c;
end process;
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Datatypes

Verilog has two groups of data types

Net Type – physical connection between structural
elements



Value is determined from the value of its drivers, such as a
continuous assignment or a gate output
wire/tri, wor/trior, wand/triand, trireg/tri1/tri0, supply0, supply1
Variable (Register) Type – represents an abstract
data storage element


Assigned a value in an always or initial statement, value is
saved from one assignment to the next
reg, integer, time, real, realtime
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Datatypes

VHDL categorizes objects in to four classes

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Constant – an object whose value cannot be changed
Signal – an object with a past history
Variable – an object with a single current value
File – an object used to represent a file in the host
environment
Each object belongs to a type




Scalar (discrete and real)
Composite (arrays and records)
Access
File
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Hierarchy

Non-trivial designs are developed in a
hierarchical form

Complex blocks are composed of simpler blocks
VHDL
Verilog
Entity and architecture
Module
Function
Function
Procedure
Task
Package and package body
Module
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Hardware Simulation

A concurrent language allows for:


Multiple concurrent “elements”
An event in one element to cause activity in another



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An event is an output or state change at a given time
Based on interconnection of the element’s ports
Logical concurrency — software
True physical concurrency — e.g., “<=” in Verilog
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Discrete Time Simulation

Models evaluated and state updated only at time
intervals — n

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
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Even if there is no change on an input
Even if there is no state to be changed
Need to execute at finest time granularity
Might think of this as cycle accurate — things only happen
@(posedge clock)
You could do logic circuits this way, but either:


Lots of gate detail lost — as with cycle accurate above (no
gates!)
Lots of simulation where nothing happens — every gate is
executed whether an input changes or not.
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Discrete Event (DE) Simulation

Discrete Event Simulation…also known as Eventdriven Simulation



Only execute models when inputs change
Picks up simulation efficiency due to its selective evaluation
Discrete Event Simulation




Events — changes in state at discrete times. These cause
other events to occur
Only execute something when an event has occurred at its
input
Events are maintained in time order
Time advances in discrete steps when all events for a given
time have been processed
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Discrete Event (DE) Simulation

Quick example



Gate A changes its output.
Only then will B and C execute
B
A
C
Observations


The elements in the diagram don’t need to be logic
gates
DE simulation works because there is a sparseness
to gate execution — maybe only 12% of gates
change at any one time.

The overhead of the event list then pays off
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Test Benches
Testing a design by simulation
 Use a test bench model




an architecture body that includes an instance of the
design under test
applies sequences of test values to inputs
monitors values on output signals


either using simulator
or with a process that verifies correct operation
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Simulation


Execution of the processes in the elaborated model
Discrete event simulation



time advances in discrete steps
when signal values change—events
A processes is sensitive to events on input signals


specified in wait statements
resumes and schedules new values on output signals
 schedules transactions
 event on a signal if new value different from old value
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Simulation Algorithm

Initialization phase



each signal is given its initial value
simulation time set to 0
for each process


activate
execute until a wait statement, then suspend
 execution usually involves scheduling transactions on signals
for later times
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Simulation Algorithm

Simulation cycle


Advance simulation time to time of next transaction
For each transaction at this time

update signal value
 event if new value is different from old value

For each process sensitive to any of these events, or
whose “wait for …” time-out has expired



resume
execute until a wait statement, then suspend
Simulation finishes when there are no further
scheduled transactions
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Synthesis
Translates register-transfer-level (RTL) design
into gate-level netlist
 Restrictions on coding style for RTL model
 Tool dependent

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Basic VerilogHDL Concepts
Interfaces
 Behavior
 Structure

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A Gate Level Model

A Verilog description of an SR latch
A module
is defined
name of the
module
module nandLatch
(output
q, qBar,
input
set, reset);
nand #2
g1 (q, qBar, set),
g2 (qBar, q, reset);
endmodule
The module has ports
that are typed
type and delay of
primitive gates
primitive gates with
names and
interconnections
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A Behavioral Model - FSM
Q2
D1
Q1
Z
reset
X
Q1
D2
Q2
Q2’
clock
reset
reset
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Verilog Organization for FSM

Two always blocks


One for the combinational logic — next state and output
logic
One for the state register
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Verilog Behavioral Specification
module FSM (x, z, clk, reset);
input
clk, reset, x;
output
z;
reg [1:2] q, d;
reg
z;
always
@(posedge clk or negedge reset)
if (~reset)
q <= 0;
else q <= d;
always @(x or q)
begin
d[1] = q[1] & x | q[2] & x;
d[2] = q[1] & x | ~q[2] & x;
z = q[1] & q[2];
end
The sequential part (the
D flip flop)
The combinational logic
part
next state
output
endmodule
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SystemVerilog
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Verilog-95
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VHDL Much Richer Than Verilog
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C Can’t Do Hardware
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Verilog-2001
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Verification and Modeling
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SystemVerilog: Unified Language
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Typical Digital System Structure
Data Inputs
Execution
Unit
(Datapath)
Data Outputs
Control Inputs
Control
Signals
Control
Unit
(Control)
Control Outputs
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Execution Unit (Datapath)
Provides All Necessary Resources and
Interconnects Among Them to Perform Specified
Task
 Examples of Resources


Adders, Multipliers, Registers, Memories, etc.
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Control Unit (Control)
Controls Data Movements in an Operational
Circuit by Switching Multiplexers and Enabling or
Disabling Resources
 Follows Some ‘Program’ or Schedule
 Often Implemented as Finite State Machine
or collection of Finite State Machines

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Finite State Machines (FSMs)

Any Circuit with Memory Is a Finite State
Machine


Even computers can be viewed as huge FSMs
Design of FSMs Involves



Defining states
Defining transitions between states
Optimization / minimization
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Moore FSM

Output Is a Function of a Present State Only
Inputs
Next State
function
Next State
clock
reset
Present State
Present State
Register
Output
function
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Outputs
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Mealy FSM

Output Is a Function of a Present State and
Inputs
Inputs
Next State
function
Next State
clock
reset
Present State
Present State
Register
Output
function
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Outputs
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Moore Machine
transition
condition 1
state 1 /
output 1
state 2 /
output 2
transition
condition 2
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Mealy Machine
transition condition 1 /
output 1
state 2
state 1
transition condition 2 /
output 2
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Moore vs. Mealy FSM (1)

Moore and Mealy FSMs Can Be Functionally
Equivalent


Equivalent Mealy FSM can be derived from Moore
FSM and vice versa
Mealy FSM Has Richer Description and Usually
Requires Smaller Number of States

Smaller circuit area
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Moore vs. Mealy FSM (2)

Mealy FSM Computes Outputs as soon as
Inputs Change


Mealy FSM responds one clock cycle sooner than
equivalent Moore FSM
Moore FSM Has No Combinational Path
Between Inputs and Outputs

Moore FSM is more likely to have a shorter critical
path
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Moore FSM - Example 1

Moore FSM that Recognizes Sequence “10”
0
1
0
1
S0 / 0
S1 / 0
reset
Meaning
of states:
1
S2 / 1
0
S0: No
elements
of the
sequence
observed
S1: “1”
observed
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S2: “10”
observed
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Mealy FSM - Example 1

Mealy FSM that Recognizes Sequence “10”
0/0
1/0
S0
reset
Meaning
of states:
1/0
S1
0/1
S0: No
elements
of the
sequence
observed
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S1: “1”
observed
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Moore & Mealy FSMs - Example 1
clock
0
1
0
0
0
S0
S1
S2
S0
S0
S0
S1
S0
S0
S0
input
Moore
Mealy
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FSMs in VHDL
Finite State Machines Can Be Easily Described
With Processes
 Synthesis Tools Understand FSM Description If
Certain Rules Are Followed



State transitions should be described in a process
sensitive to clock and asynchronous reset signals
only
Outputs described as concurrent statements outside
the clock process
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Moore FSM
Inputs
process
(clock, reset)
Next State
function
Next State
clock
reset
concurrent
statements
Present State
Register
Output
function
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Present
State
Outputs
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Mealy FSM
Inputs
process
(clock, reset)
Next State
clock
reset
concurrent
statements
Next State
function
Present
State
Present State
Register
Output
function
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Outputs
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Moore FSM - Example 1

Moore FSM that Recognizes Sequence “10”
0
1
0
1
S0 / 0
S1 / 0
reset
Meaning
of states:
1
S2 / 1
0
S0: No
elements
of the
sequence
observed
S1: “1”
observed
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S2: “10”
observed
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Moore FSM in VHDL (1)
TYPE state IS (S0, S1, S2);
SIGNAL Moore_state: state;
U_Moore: PROCESS (clock, reset)
BEGIN
IF(reset = ‘1’) THEN
Moore_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Moore_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Moore_state <= S1;
ELSE
Moore_state <= S0;
END IF;
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Moore FSM in VHDL (2)
WHEN S1 =>
IF input = ‘0’ THEN
Moore_state <= S2;
ELSE
Moore_state <= S1;
END IF;
WHEN S2 =>
IF input = ‘0’ THEN
Moore_state <= S0;
ELSE
Moore_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
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Mealy FSM - Example 1

Mealy FSM that Recognizes Sequence “10”
0/0
1/0
S0
reset
1/0
S1
0/1
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Mealy FSM in VHDL (1)
TYPE state IS (S0, S1);
SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset)
BEGIN
IF(reset = ‘1’) THEN
Mealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Mealy_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Mealy_state <= S1;
ELSE
Mealy_state <= S0;
END IF;
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Mealy FSM in VHDL (2)
WHEN S1 =>
IF input = ‘0’ THEN
Mealy_state <= S0;
ELSE
Mealy_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
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Moore FSM - Example 2 State Diagram
resetn
w = 1
w = 0
A z = 0
B z = 0
w = 0
w = 1
w = 0
C z = 1
w = 1
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Moore FSM - Example 2 State Table
Next state
Present
state
w = 0
w = 1
z
A
B
C
A
A
A
B
C
C
0
0
1
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Output
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Moore FSM
Input: w
process
(clock, reset)
clock
resetn
concurrent
statements
Next State
function
Next State
Present State
Register
Output
function
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Present State: y
Output: z
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Moore FSM - Example 2 VHDL (1)
USE ieee.std_logic_1164.all ;
ENTITY simple IS
PORT ( clock
resetn
w
z
END simple ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
BEGIN
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Moore FSM - Example 2 VHDL (2)
IF resetn = '0' THEN
y <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
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Moore FSM - Example 2 VHDL (3)
WHEN C =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
END CASE ;
END IF ;
END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
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Moore FSM
Input: w
process
(w, y_present)
Next State
function
Next State: y_next
process
(clock,
resetn)
concurrent
statements
clock
resetn
Present State
Register
Present State:
y_present
Output: z
Output
function
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Alternative Example 2 VHDL (1)
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
SIGNAL y_present, y_next : State_type ;
BEGIN
PROCESS ( w, y_present )
BEGIN
CASE y_present IS
WHEN A =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= B ;
END IF ;
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Alternative Example 2 VHDL (2)
WHEN B =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= C ;
END IF ;
WHEN C =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= C ;
END IF ;
END CASE ;
END PROCESS ;
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Alternative Example 2 VHDL (3)
PROCESS (clock, resetn)
BEGIN
IF resetn = '0' THEN
y_present <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
y_present <= y_next ;
END IF ;
END PROCESS ;
z <= '1' WHEN y_present = C ELSE '0' ;
END Behavior ;
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Mealy FSM - Example 2 State Diagram
resetn
w = 1 z = 0
w = 0 z = 0
A
B
w = 1 z = 1
w = 0 z = 0
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Mealy FSM - Example 2 State Table
Next state
Present
state w = 0 w = 1
A
B
A
A
B
B
Output z
w= 0
w= 1
0
0
0
1
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Mealy FSM
Input: w
process
(clock, reset)
Next State
clock
resetn
concurrent
statements
Next State
function
Present State: y
Present State
Register
Output
function
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Output: z
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Mealy FSM Example 2 VHDL (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Mealy IS
PORT ( clock : IN
resetn : IN
w
: IN
z
: OUT
END Mealy ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Behavior OF Mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
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Mealy FSM Example 2 VHDL (2)
PROCESS ( resetn, clock )
BEGIN
IF resetn = '0' THEN
y <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
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Mealy FSM Example 2 VHDL (3)
WHEN B =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
END CASE ;
END IF ;
END PROCESS ;
WITH y SELECT
z <= w WHEN B,
z <= ‘0’ WHEN others;
END Behavior ;
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State Encoding

State Encoding Can Have a Big Influence on
Optimality of the FSM Implementation



No methods other than checking all possible
encodings are known to produce optimal circuit
Feasible for small circuits only
Using Enumerated Types for States in VHDL
Leaves Encoding Problem for Synthesis Tool
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Types of State Encodings (1)

Binary (Sequential) – States Encoded as
Consecutive Binary Numbers



Small number of used flip-flops
Potentially complex transition functions leading to
slow implementations
One-Hot – Only One Bit Is Active



Number of used flip-flops as big as number of states
Simple and fast transition functions
Preferable coding technique in FPGAs
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Types of State Encodings (2)
State
Binary Code
One-Hot Code
S0
S1
S2
000
001
010
10000000
01000000
00100000
S3
S4
S5
S6
S7
011
100
101
110
111
00010000
00001000
00000100
00000010
00000001
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