A VHDL nyelv alapjai
VHDL nyelvi elvonatkoztatások
 Tervezési hierarchiák – szerkezeti leírás

A VHDL nyelv alapjai
VHDL nyelvi elemek
VHDL is composed of language building blocks that consist
of more than 75 reserved words and about 200 descriptive
words or word combinations
A VHDL nyelv alapjai
Foglalt VHDL kulcsszavak
ABS
ACCESS
AFTER
ALIAS
ALL
AND
ARCHITECTURE
ARRAY
ASSERT
ATTRIBUTE
BEGIN
BLOCK
BODY
BUFFER
BUS
CASE
COMPONENT
CONFIGURATION
CONSTANT
A VHDL nyelv alapjai
DISCONNECT
DOWNTO
ELSE
ELSIF
END
ENTITY
EXIT
FILE
FOR
FUNCTION
GENERATE
GENERIC
GROUP
GUARDED
IF
IMPURE
IN
INERTIAL
INOUT
IS
LABEL
LIBRARY
LINKAGE
LITERAL
LOOP
MAP
MOD
NAND
NEW
NEXT
NOR
NOT
NULL
OF
ON
OPEN
OR
OTHERS
OUT
PACKAGE
PORT
POSTPONED
PROCEDURE
PROCESS
PURE
RANGE
RECORD
REGISTER
REM
REPORT
ROL
ROR
RETURN
VARIABLE
SELECT
SEVERITY
SIGNAL
SHARED
SLA
SLL
SRA
SRL
SUBTYPE
WAIT
WHEN
WHILE
WITH
THEN
TO
TRANSPORT
TYPE
UNAFFECTED
UNITS
UNTIL
USE
XNOR
XOR
Tervleírási módszerek
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Szerkezeti leírási módszer
Viselkedési leírási módszer
Adatáramlási leírási módszer
Kapcsolási rajz
These two are similar in that both use a process to describe
the functionality of a circuit
A VHDL nyelv alapjai
VHDL nyelvi elvonatkoztatások


VHDL is rich in language abstractions, in addition to which the
language can be used to describe different abstraction levels,
from functions right down to a gate description
Abstraction levels are a means of concealing details
A VHDL nyelv alapjai
Elvonatkoztatási szintek
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Functional (system) level + architecture =>
Behavioral level + resource handler =>
RTL (dataflow) level + construction data =>
Structural level + technology data =>
Logic (gate) level + electrical specification =>
Electrical level + layout requirements =>
Layout level
A VHDL nyelv alapjai
A fő témánk
A leírási módszerek meghatározásai

Szerkezeti leírási módszer: expresses the design as an arrangement
of interconnected components
– It is basically schematic

Viselkedési leírási módszer: describes the functional behavior of a
hardware design in terms of circuits and signal responses to
various stimuli
– The hardware behavior is described algorithmically

Adatáramlási leírási módszer: is similar to a register-transfer
language
– This method describes the function of a design by defining the flow
of information from one input or register to another register or output
A VHDL nyelv alapjai
Feladatköri (rendszer-) szint
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Algorithms can be describe at this level
E.g. a controller algorithm can be described and simulated on
the computer
An algorithm does not need to contain any time information
Specifications written in VHDL will be able to be simulated
A VHDL nyelv alapjai
Viselkedési szint
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Behavior and time are described at this level
No architecture is required here
The advantage of models at this level is that models for
simulation can be built quickly
A behavioral model can be described as functional modules and
an interface interface between them
The modules contain one or more functions and time relations
In certain cases the architecture can be defined
A VHDL nyelv alapjai
Leírási módszerek összehasonlítása
A Behavioral Description uses a small number of processes
where each process performs a number of sequential signal
assignments to multiple signals
In contrast, a Data-Flow Description uses a large number of
concurrent signal assignment statements
A concurrent statement executes asynchronously with respect to
other concurrent statements
Concurrent statements used in Data-Flow Description include:
- block statement (used to group one or more concurrent
statements)
- concurrent procedure call
- concurrent assertion statement
- concurrent signal assignment statement
A VHDL nyelv alapjai
RTL = Regiszter átviteli szint

It consists of a language which describes behavior in
–
–
–
–
asynchronous and synchronous state machines
data paths
operators (+,*,<,>,...)
registers
A VHDL nyelv alapjai
Elektromos szint


Other name is: transistor level
There are models of
– transistors
– capacitances
– resistances

This is not supported in VHDL
A VHDL nyelv alapjai
Layout szint


At layout level models are made of the physical process
This is not supported in VHDL
A VHDL nyelv alapjai
Szintézis = Növekvő összetettség


Synthesis is done between each level
The volume of information increases between the various
abstraction levels
– E.g. technology information is required to synthesize from RT to
gate level
– Each transition (synthesis) generates more information

In order to implement a function in an ASIC, are required the
followings:
–
–
–
–
technology information
wiring information
gate information
set-up times
A VHDL nyelv alapjai
Miért használnak különböző
elvonatkoztatási szinteket?


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It is usually the requirements that determine the abstraction
level at which the information is to be described
If a short development time is required, a high abstraction level
should be chosen as the description language
In practice RT level (and parts of behavioral) can be synthesized
automatically to gate level
A VHDL nyelv alapjai
Különböző alkalmazások

ASIC = Application Specific Integrated Circuit
– Usually includes FPGA, gate array, standard cell and full custom
designs.

PCB = Printed Circuit Board design
– On a circuit board there are usually several ASICs together with a
microprocessor and its infrastructure

System = a number of PCBs
A VHDL nyelv alapjai
Modell kiértékelés
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The code for VHDL component can be verified
functionally in a simulator
The simulator simulates (“executes”) the VHDL code
with input signals and produces a signal diagram and
error messages on the basis of the components
The input signals are defined either in VHDL or in the
simulator’s language
When the VHDL code is simulated, functional
verification takes place
At a later stage, time verification of the design is also
possible
A VHDL nyelv alapjai
Szimuláció
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Simulating models is an effective way of verifying
the design
The model in the computer is only a time-discrete
model, however, while reality is continuous
The computer model is more or less like reality
It is least like reality at a high abstraction level
(behavioral) and most like it at the lowest level
(layout)
A VHDL nyelv alapjai
Egyéb elektronikai leíró nyelvek
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There are several languages which are used to describe
electronic designs
One popular language is called VERILOG
It is used from RT level down
In some other languages there are no hierarchies, which causes
major problems when working on complex assignments
There languages are developed by universities and research
centers
A VHDL nyelv alapjai
Other HDL languages

There are several other language extensions built to either aid in RTL construction
or assist in modeling:
– ParaCore - http://www.dilloneng.com/paracore.shtml
– RubyHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml
– MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtml
– JHDL - http://www.jhdl.org/
– Lava - http://www.xilinx.com/labs/lava/
– HDLmaker - http://www.polybus.com/hdlmaker/users_guide/
– SystemC
– AHDL – http://www.altera.com
» It is good for Altera-made chips only, which limits its usefulness
» But it is easy to pick up and use successfully

The main purpose of a language -- programming, hdl, or otherwise -- is to ease the
expression of design
A VHDL nyelv alapjai
A SystemC


C++ könyvtár rendszerszintű modellezésre
Különböző elvonatkoztatási szinteket támogat
– Feladatköri leírástól RTL szintűig


Használható gyors, hatékony tervekhez
Igazoláshoz (verification)
A VHDL nyelv alapjai
Miért nem csak C++?

C++: sorrendi programozás, nem alkalmas párhuzamos események
modellezésére
A hardver modellben kell késleltetés, idő
A hardver modellek közlési csatornái (port, signal) különböznek a szoftver
modellekben használtaktól
C++ adattípusai túl távol állnak a hardver megvalósításoktól

C++ önmagában nem elég leírni egy bonyolult rendszert
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A VHDL nyelv alapjai
SystemC adattípusok

Adattípusokat határoz meg a hardver modellezéshez
–
–
–
–

bit (‘0’, ‘1’)
bitvector (‘0101’)
logic (‘0’, ‘1’, ‘Z’, ‘X’)
logicvector (’01XZ’)
Használhatók az alap C++ adattípusok is
– fixed
– float
– signed, unsigned, stb.
A VHDL nyelv alapjai
Verilog
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Verifying Logic
Phil Moorby from Gateway Design Automation in 1984 to 1987
– Absorbed by Cadence
» Cadence's ownership of Verilog => others support VHDL
Verilog-XL simulator from GDA in 1986
Synopsis Synthesis Tool in 1988
In 1990 became open language
– OVI: Open Verilog International
IEEE Standard in 1995
– IEEE Std-1364-1995
Last revision in 2001
– IEEE Std-1364-2001
Ongoing work for adding
– Mixed-signal constructs: Verilog-AMS
– System-level constructs: SystemVerilog
A VHDL nyelv alapjai
VHDL vs. Verilog
VHDL
Verilog
All abstraction levels
All abstraction levels
Complex grammar
Easy language
Describe a system (everything)
Describe a digital system
Lots of data types
Few data types
User-defined package & library
No user-defined packages
Full design parameterization
Simple parameterization
Easier to handle large designs
Very consistent language. Code written and
simulated in one simulator will behave
exactly the same in another simulator. E.g.
strong typing rules.
Less consistent language. If you don't
follow some adhoc methodology for coding
styles, you will not get it right.
It executes differently on different platforms
unless you follow some adhoc coding rules.
A VHDL nyelv alapjai
VHDL vs. Verilog (Cont.)
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
It does seem that Verilog is easier for designing at the
gate-level, but that people who do higher level simulations express a
preference for VHDL
VHDL places constraints on evaluation order that limit the
optimizations that can be performed
– Verilog allows the simulator greater freedom
– For example, multiple levels of zero-delay gates can be collapsed into a
single super-gate evaluation in Verilog
– VHDL requires preserving the original number of delta cycles of delay
in propagating through those levels
VHDL
Verilog
In Europe the VHDL is the most popular
language
Based on Pascal language
Based on C language
Most FPGA design in VHDL
Most ASIC design in Verilog
A VHDL nyelv alapjai
VHDL vs. Verilog: Process block

VHDL:
process (siga, sigb)
begin
…...
end;

Verilog:
always @ (siga or sigb)
begin
….
end
A VHDL nyelv alapjai
VHDL vs. Verilog:
Concurrent Signal Assignment

VHDL:
c <= a and b;

Verilog:
assign c = a & b ;
A VHDL nyelv alapjai
VHDL vs. Verilog: Signal Delays

VHDL:
a <= transport b after 1 ns;

Verilog:
#1 assign a = b;
»
»
»
»
‘a’ output is delayed by 1 time unit
The ‘# ‘ operator is the delay operator
# N will delay for N simulation units
Delays can assigned to both inputs and outputs
#1 assign a = #1 b;
» ‘b’ is delayed by 1 unit, then assigned to ‘a’, which is then delayed
by 1 time unit
A VHDL nyelv alapjai
VHDL vs. Verilog: Clock Generator

VHDL:
signal clk : std_logic := ‘0’;
process
begin
clk <= not (clk) after clkperiod/2;
wait on clk;
end;

Verilog:
initial clk = 0;
always #(clkperiod/2) clk = ~ clk;
A VHDL nyelv alapjai
Verilog Weakness

Not well suited for complex, high level modeling
– No user defined type definition
– No concept of libraries, packages, configurations
– No ‘generate’ statement - can’t build parameterized structural
models
– No complex types above a two-dimensional array
A VHDL nyelv alapjai
VHDL vs. Verilog:
Managing Large designs

VHDL:
– Configuration, generate, generic and package statements all help
manage large design structures

Verilog:
– There are no statements in Verilog that help manage large designs
A VHDL nyelv alapjai
VHDL vs. Verilog:
Procedures and Tasks

VHDL:
– allows concurrent procedure calls

Verilog:
– does not allow concurrent task calls
A VHDL nyelv alapjai
VHDL vs. Verilog:
Structural Replication

VHDL:
– The generate statement replicates a number of
instances of the same design-unit or some sub part
of a design, and connects it appropriately

Verilog:
– There is no equivalent to the generate statement in
Verilog.
A VHDL nyelv alapjai
Languages “under development”

SystemVerilog
– Extending Verilog to higher levels of abstraction for architectural
and algorithm design and advanced verification

VHDL 200x
– Goal of VHDL Analysis and Standards Group (VASG):
» Enhance/update VHDL for to improve performance, modeling
capability, ease of use, simulation control, and the type system

e.g.: Data types and abstractions:
– variant records
– interfaces
A VHDL nyelv alapjai
Az összetettség csökkentésének
módszerei

Language abstractions use the language to describe
complex matters without having to describe small
details
– Functions and procedures are important parts of the
language in order to handle complexity

Design hierarchy uses components in order to conceal
details - the black box principle
– The term black box means that only inputs/outputs of a
component are visible at a certain level
– It is the designer who decides how many different
hierarchies there are to be in the design
A VHDL nyelv alapjai
Fő sajátságok

VHDL uses the concept of delta delay to keep track of
processes that should occur at a given time step, but
are actually evaluated in different machine cycles
 A delta delay is a unit of time as far as the simulator
hardware is concerned, but in the simulation itself time
has no advance
A VHDL nyelv alapjai
VHDL összetevők
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Components are a central concept in VHDL
Components are used, among other things, to build up
component libraries, e.g.:
– microprocessors
– special user circuits
– other standard circuits

If a “good” component has been designed, it can be saved in a
component library, enabling it to be copied as many times as
required, i.e. components are reusable
– this is called creating instances, i.e. creating the component in a
schematic or in the text file
A VHDL nyelv alapjai
Objektum alapú nyelv
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Staying with computer science a while longer, VHDL
is an object-based language, i.e. what separates VHDL
from object-oriented languages is that the language
does not have inheritance
Generic components and instantiation are typical for
object-based languages
Generic components are components which can be
modified before instantiation, e.g. a generic
component which copes with different width for the
input and output signals
A VHDL nyelv alapjai
Feketedoboz használata
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The internal structure can be concealed from the designer the black box principle
In some cases there is no need to know how to component
is structured
The designer is usually only interested in
– inputs and outputs
– a specification function and
– access times

The majority of hardware designers are used to working
with black boxes such as the 74LSXX circuit family, for
example
A VHDL nyelv alapjai
Fő nyelvi szerkezetek
Tervezési
egyed
-It is the basic unit of hardware description
- = egyed bejelentés + építmény
Egyed
bejelentés: fekete doboz modell
Építmény: It describes the relationship between the design
entity inputs and outputs
Each architecture consists of concurrent statements denoted
by CS
A VHDL nyelv alapjai
Egyidejű és sorrendi utasítások
Concurrent statements define interconnected processes and
blocks that together describe a design’s overall behavior or
structure
They can be grouped using block statement. Groups of
blocks can also be partitioned into other blocks
At this same level, a VHDL component (CP) can be
connected to define signals within the blocks
It is a reference to an entity
A process can be a single signal assignment statement or a
series of sequential statements (SS)
Within a process, procedures and functions can partition
the sequential statements
A VHDL nyelv alapjai
Elsődleges nyelvi elvonatkoztatás
Tervezési egyed
Egyed bejelentés
Építmény
The primary abstraction level
of a VHDL hardware model is
the Design Entity. The Design
Entity can represent a cell,
chip, board, or subsystem
A Design Entity is composed of two main parts:
1) An Entity Declaration
2) An Architecture
A VHDL nyelv alapjai
Elsődleges nyelvi elvonatkoztatás
(folyt.)
An Entity Declaration defines the
interface between the Design Entity and the
environment outside of the Design Entity
An Architecture describes the
relationships between the Design Entity inputs
and outputs
A VHDL nyelv alapjai
Példa az egyedbejelentésre és az
építményre
ENTITY and2 IS
PORT (a, b: IN bit;
q: OUT bit);
END and2;
The entity name in the
Architecture has to be the
same as the identifier of
the corresponding Entity
Declaration
ARCHITECTURE example OF and2 IS
-- declaration here
BEGIN
-- statement here
END example;
A VHDL nyelv alapjai
Egyedbejelentés és építmény

A component is made up of two main parts:
– Entity: Port declaration for inputs and outputs
– Architecture: structural of behavioural description
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Behaviour is defined as a collective name for
functions, operations, behaviour and relations
Behaviour can also be a structural description, i.e. the
component consists of other components
The entity can be regarded as a black box with inputs
and outputs
A VHDL nyelv alapjai
Példák egyedbejelentésre
entity vhdl_component1 is
port ( a : in std_logic;
b : out std_logic);
end vhdl_component1;
entity vhdl_component2 is
port ( signal a_in: in std_logic; -- input
signal b_out: out std_logic); -- output
end vhdl_component2;
A VHDL nyelv alapjai
Egy építmény példakódja
architecture vhdl_code of vhdl_component1 is
begin
B <= not A;
....
end vhdl_code;

Two names are specified in the declaration of the
architecture: the component name which describes
which entity the architecture belongs to, and
vhdl_code, which is the name of the architecture
A VHDL nyelv alapjai
Az egyedbejelentés jelölésmódja
entity <identifier_name> is
port( [signal] <identifier>:[<mode>] <type_indication>;
...
[signal] <identifier>:[<mode>] <type_indication>);
end [entity] [<identifier_name>];

The word “entity” in the last line is not supported before the
VHDL-93 standard
A VHDL nyelv alapjai
A kapcsok üzemmódjai
<mode> = in, out, inout, buffer, linkage
in: Component only read the signal
out: Component only write to the signal
inout: Component read or write to the signal (bidirectional
signals)
buffer: Component write and read back the signal (no
bidirectional signals, the signal is going out from the
component)
linkage: Used only in the documentation
A VHDL nyelv alapjai
Inout vagy Buffer

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Mode inout should only be used in the case of bidirectional
signals
If the signal has to be reread, either mode buffer or an internal
dummy signal should be used
The word signal is normally left out of the port declaration, as it
does not add any information
Mode in and the name of the entity after end can also be left
out
A VHDL nyelv alapjai
Példa az egyszerűsítésre
entity gate1 is
port( signal a,b: in std_logic;
signal c: out std_logic);
end entity gate1;
entity gate1 is -- Identical with the above example
port( a,b:
std_logic;
c: out std_logic);
end;
A VHDL nyelv alapjai
Építmény

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
An architecture defines a body for a component entity
An architecture specifies a behavior between inputs and outputs
The architecture name is not the same as the component name:
instead an architecture is tied to an entity
A VHDL nyelv alapjai
Az építmény jelölésmódja
architecture <architecture_name> of <entity_identifier> is
[<architecture_declarative_part>]
begin
<architecture_statement_part> -- The body of the arch.
end [architecture] [<architecture_name>];
A VHDL nyelv alapjai
Megjegyzések

The architecture declaration part must be defined before first
begin and can consist of, for example:
–
–
–
–
types
subprograms
components
signal declarations
A VHDL nyelv alapjai
Egy inverter építménye
architecture dtf of cir is
begin
b_out <= not a_in;
end dtf;
A VHDL nyelv alapjai
Fontos megjegyzések



An entity can be linked to several architectures such as
behavioral and RTL descriptions, for example
Note that VHDL does not differentiate between upper-case and
lower-case letters
The double dash “--” indicates that the rest of the line is
commentary
A VHDL nyelv alapjai
A VHDL-ben meghatározott logikai
operátorok
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A VHDL nyelv alapjai
NOT
AND
NAND
OR
NOR
XOR
EXOR
Példa a logikai operátorokra
architecture rtl of cir is
signal int: std_logic; -- Internal signal declaration
begin
int <= not (((a nand b) nor (c or d)) xor e);
aOut <= int and f;
end;
A VHDL nyelv alapjai
Megjegyzések

Comments follow two hyphens '--' and instruct the analyzer to
ignore the rest of the line

There are no multiline comments in VHDL

Tabs improve readability, but it is best not to rely on a tab as a
space in case the tabs are lost or deleted in conversion

You should thus write code that is still legal if all tabs are
deleted (use spaces as tabs!)
A VHDL nyelv alapjai
Szövegelemek, pl. rögzített értékű tételek


Sokféle alakú szövegelem létezik a VHDL-ben
A következő kódok néhány példát mutatnak be:
entity literals1 is end;
architecture bhv of literals1 is
begin process
variable I1 : integer;
variable R1 : real;
variable C1 : character;
variable S16 : string(1 to 16);
variable BV4 : bit_vector(0 to 3);
variable BV12 : bit_vector(0 to 11);
variable BV16 : bit_vector(0 to 15);
A VHDL nyelv alapjai
Szövegelemek (folyt.)
begin
-- Abstract literals are decimal or based literals
-- Decimal literals are integer or real literals
-- Integer literal examples (each of these is the same):
I1 := 120000; I1 := 12e4; I1 := 120_000;
-- Based literal examples (each of these is the same):
I1 := 2#1111_1111#; I1 := 16#FF#;
-- Base must be an integer from 2 to 16:
I1 := 16:FFFF:; -- you may use a : instead of #
-- Real literal examples (each of these is the same):
R1 := 120000.0; R1 := 1.2e5; R1 := 12.0E4;
-- Character literal must be one of the 191 graphic characters
-- 65 of the 256 ISO Latin-1 set are non-printing control
-- characters
C1 := 'A'; C1 := 'a'; -- these are different!
A VHDL nyelv alapjai
Szövegelemek (folyt.)
-- String literal examples:
S16 := " string" & " literal"; -- concatenate long strings
S16 := """Hello,"" I said!";
-- doubled quotes
S16 := %string literal%;
-- can use % instead of "
S16 := %Sale: 50%% off!!!%;
-- doubled %
-- Bit-string literal examples:
BV4 := B"1100";
-- binary bit-string literal
BV12 := O"7777";
-- octal bit-string literal
BV16 := X"FFFF";
-- hex
bit-string literal
wait;
end process; -- the wait prevents an endless loop
end;
A VHDL nyelv alapjai
Pl.: két bemenet és egy kimenet
entity halfAdder is
port (x, y : in bit := '0'; sum, cOut : out bit); -- formals
end;
– Matching the parts of this code with the constructs you can see that the
identifier is halfAdder and that
x, y: in bit := '0'; sum, cOut: out bit
corresponds to
port_interface_list
– The ports x, y, sum, and cOut are formal ports, or formals
– This particular entity halfAdder does not use any of the other optional
constructs that are legal in an entity declaration
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Példa egy félösszeadóra

The following architecture body (we shall just call it an architecture from now on)
describes the contents of the entity halfAdder:
architecture dtf of halfAdder is
begin
sum <= x xor y;
cOut <= x and y;
end dtf;
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Építmény

We use the same signal names, the formals: sum , x , y , and cOut, in the
architecture as we use in the entity
– we say the signals of the "parent" entity are visible inside the architecture
"child"

An architecture can refer to other entity-architecture pairs (i.e., we can nest
black boxes)

We shall often refer to an entity-architecture pair as
entity(architecture)

For example, the architecture bhv of the entity halfAdder is
halfAdder(bhv)
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Kérdés-válasz az építményről
Q:
Why would we want to describe the outside
of a black box (an entity) separately from the
description of its contents (its architecture)?
A:
Separating the two makes it easier to move
between different architectures for an entity
(there must be at least one).
For example, one architecture may model an
entity at a behavioral level, while another
architecture may be a structural model.
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