UNIT 7: Mixed-Language Description
9.1 Highlights of Mixed-Language Description
 Simulator that we use with the HDL package should be able to handle mixedlanguage environment.
 Both VHDL and Verilog module files are made visible to the simulator.
 In mixed-language environment both VHDL and Verilog Libraries are made
visible to the simulator.
 At present time, mixed language environment has many limitations. VHDL
module can only invoke the entire Verilog module; and a Verilog module can only
invoke a VHDL entity. We can not invoke a VHDL procedure from a Verilog
module.
 Mixed-Language description can combine advantages of both languages in one
module.
HDL Programming Fundamentals
9.2.1 How to Invoke a VHDL entity from Verilog Module
Listing 9.1 Invoking VHDL entity from Verilog Module
//This is the Verilog module
module mixed (a, b, c, d);
input a,b;
output c,d;
...........
VHD_enty V1 ( a,b,c,d);
/*The above module VHD_enty is the VHDL entity to be
invoked in this module*/
...........
endmodule
--This is the VHDL entity
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity VHD_enty is
port (x, y : in std_logic; O1, O2: out std_logic);
end VHD_enty ;
architecture VHD_enty of VHD_enty is
begin
...........
end VHD_enty ;
HDL Programming Fundamentals
Only VHDL entities can
Be invoked from Verilog
module
9.2.2 How to Invoke a Verilog Module from VHDL Module
Listing 9.2 Invoking a Verilog Module from VHDL Module
-- This is the VHDL Project
library IEEE;
Declare a VHDL component
use IEEE.STD_LOGIC_1164.ALL;
entity Ver_VHD is
with the Same name as the
port ( a, b : in std_logic; c: out std_logic);
Verilog Module.
end Ver_VHD;
architecture Ver_VHD of Ver_VHD is
component V_modl
port (x,y: in std_logic; z : out std_logic);
-- The name of the Component V_modl should be identical to the name of the
--Verilog module; also the ports should identical in name and mode
--with the inputs and outputs of the Verilog module
end component;
.......
end Ver_VHD;
//This is the Verilog module
module V_modl (x, y, z);
input x,y;
output z;
..........
endmodule
HDL Programming Fundamentals
9.3.1 Invoking VHDL entity from Verilog Module-Examples
Example 9.1 Mixed-Language Description of a Full Adder
Listing 9.3
x
sum
y
cin
Half adder
Half adder
carry
A VHDL half-adder is written.
A Verilog module uses the
VHDL half adder to describe
A full adder
HDL Programming Fundamentals
Example 9.2 Mixed-Language Description of a 9-bit Adder
Listing 9.4
b6-8
a6-8
b3-5
a3-5
b0-2
a0-2
3
3
3
3
3
3
A3
3-bit
carryLook
ahead
3
Carry_out
Sum_total6-8
cr1
A2
3-bit
carryLook
ahead
3
Sum_total3-5
cr0
A1
3-bit
carryLook
ahead
c0
3
Sum_total0-2
A VHDL description of a 3-bit
Carry-lookahead adder is used
To write a Verilog description of
9-bit adder
HDL Programming Fundamentals
Example 9.3 Mixed-Language Description of 3-bit Adder with zero Flag
Listing 9.5
sum
X
Y
cin
cout
1-bit full adder description
is written in VHDL. A
Verilog module uses the
VHDL description to
describe a 3-bit full adder
with zero flag.
HDL Programming Fundamentals
Example 9.4 Mixed-Language Description of a Master-Slave D Flip-Flop
Listing 9.6
D_in
Q0
d
d
Q
D-Latch
C
clkb
Q
Q_out
D-Latch
C
Qb
Qb_out
Qb
clk2
clk
A VHDL description of a Dlatch is written. A Verilog
module implements the VHDL
description to describe a
Master-Slave D Flip-Flop.
HDL Programming Fundamentals
Example 9.5 Mixed-Language Description of a 4x4 Comparator
Y2
X2
Y1
X1
Y0
X0
Listing 9.7
Full
adder
Full
adder
Full
adder
carry2
carry1
carry0
sum2
xgty
xlty
sum1
0
sum0
A 1-bit full adder is
written in VHDL. A
Verilog module
implements the VHDL
Only three bits code to describe a 4x4
are shown
comparator.
xeqy
HDL Programming Fundamentals
9.3.2 Invoking Verilog module from VHDL Module
Example 9.6 Instantiating an AND gate From VHDL Module
Listing 9.8
VHDL component and2 is
declared in the VHDL
module. A Verilog module
with the same name and2
describes and2. The Verilog
description is implemented
in the VHDL module..
HDL Programming Fundamentals
Example 9.7 Mixed-Language Description of a JK Flip Flop with a Clear
Listing 9.9
A VHDL component jk_verilog
is declared in a VHDL module.
A Verilog module jk_verilog
describes the flip-flop. The
VHDL implements the Verilog
description.
HDL Programming Fundamentals
Example 9.8 Mixed-Language Description of 3-bit Synchronous Counter
with Clear
Listing 9.10
clr
Q
J
Q
JK2
Q
J
Q
JK1
K
Q
J
clrb1
JK0
K
Q
K
1
clrbar
Several VHDL
components JK_FF, inv,
and2, or2 have been
declared in the VHDL
module. Verilog is
implemented to describe
these components.
VHDL uses the escription
to describe the counter.
HDL Programming Fundamentals
Example 9.9 Mixed-Language Description of N-bit Asynchronous Counter
Listing 9.11
rco
Q(n-1)
Q
Q
Q1
J
Q
1
K
Q0
…………...
Q
J
1
K
Q
J
Q
K
1
Two Verilog modules
(jkff and andgate) are
implemented in a VHDL
module to describe N-bit
Asynchronous counter
clk
HDL Programming Fundamentals
Example 9.10 Mixed-Language Description of a Switch-Level Multiplexer
Listing 9.12
A VHDL description appears to
have primitives nmos and
pmos by linking it to a Verilog
module where these primitives
are built-in.
HDL Programming Fundamentals
Example Instantiating CASEX in VHDL.
Listing9.11
Table 9.2 Truth Table for 4-bit Encoder
Input
Output
a
b
xxx1
1
xx10
2
x100
4
1000
8
Others
0
CaseX is a Verilog built-in
function. By writing mixed
language, the VHDL appears as if
it has this built-in function.
HDL Programming Fundamentals
Example 9.12 Mixed-Language Description of a Low Pass RC Filter
Listing 9.14
R
Vi
C
Vo
Verilog can easily handle real
(floating) arithmetic
operations; VHDL can easily
handle File operations. By
writing mixed language, we
utilize the advantages of both
languages.
HDL Programming Fundamentals
9.4 Limitations of Mixed-Language Description
Mixed language description is limited at present time. The limitations can be
summarized as follows
• Not all VHDL data types are supported in mixed language description.
Only bit, bit_vector, std_logic, std_ulogic, std_logic_vector, and
std_ulogic_vector are supported.
•VHDL Port type Buffer is not supported in many of the current simulators.
•Only VHDL component construct can invoke a Verilog module. We can not
invoke Verilog module from any other construct in the VHDL module.
•Verilog module can only invoke a VHDL entity. It can not invoke any other
construct in the VHDL module such as procedures or functions.
HDL Programming Fundamentals
Summary
To invoke a VHDL entity from a Verilog module, we write a module statement in
Verilog. The name of the module should be identical to the name of the entity;
the type of the parameters of the module should match the type of the ports of
the entity. For example the module statement:
HA H1 (y, cin, s0,c0);
written in a Verilog module invokes a VHDL entity by the name of HA. In the
Verilog module, no other module should have the same name HA.
Invoking a Verilog module from VHDL module is done by declaring a component
in the VHDL module with the same name as the Verilog module. The ports of the
component should be the same name and match in type with the ports of the
Verilog module. For example, the VHDL component:
component V_modl
port (x,y: in std_logic; z : out std_logic);
end component;
invokes a Verilog module V_modl.
HDL Programming Fundamentals