DIGITAL DESIGN WITH VHDL
Exercise 1
Muhammad Amir Yousaf
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What is VHDL?
What it is used for?
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VHDL vs Programming
languages?
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VHDL
VERY HIGH SPEED INTEGRATED CIRCUIT
HARDWARE DESCRIPTION LANGUAGE:
Origininally designed to describe and specify
hardware.
Specifications were made executable with
simulators.
Synthesizer were developed to synthesize.
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VHDL - MODULARITY
Component in VHDL is refferd as ’entity’ and has a clear
interface.
Inputs
Outputs
Type and size.
How the external
world would see
it.
Internal of component is called architecture declaration.
Complexity is hidden inside.
Made of components and wires.
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DESCRIPTION OF A DIGITAL
COMPONENT.
A component is to be designed with following
description:
A full adder that adds two 1 bit inputs and a carryin bit. The result is shown at a 1 bit SUM and a
carry-out bit.
Describe this component
in (a standard descriptive
language)
VHDL
SUM
A
B
CIN
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Full Adder
COUT
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DESCRIPTION OF A FULLADDER WITH
VHDL
SUM
A
B
CIN
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Full Adder
COUT
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DESCRIPTION OF A DIGITAL
COMPONENT.
A component is to be designed with following
description:
A full adder that adds two 1 bit inputs and a carryin bit. The result is shown at a 1 bit SUM and a
carry-out bit.
RST
Let add a ‘RESET’ pin in the
component.
A
Describe this component
in (a standard descriptive
language)
VHDL
B
CIN
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SUM
Full Adder
COUT
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DESCRIPTION OF A DIGITAL
COMPONENT.
VHDL code:
If RST = ’1’ then
SUM <= ‘0’;
COUT <= ‘0’;
else
-----------End if;
 If is sequential, so must be
contained in process.
 Sequential or procedural
statements execute in the
order as they appear in code.
label: process (<senstivity_list>)
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DESCRIPTION OF A FULLADDER
RST
SUM
A
B
CIN
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Full Adder
COUT
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EXERCISES
EX 1: Describe a system in VHDL with an input x and output y of
type integer. The system gives x+10 at output whenever a change
is detected on input.
EX 2: ´Describe a 4-bit comparator in VHDL using relational
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operators i.e > < =.
x
EX 3: A MUX is described in VHDL as .
y
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Make a 4-to-1 MUX using
the structure of 2-to-1
MUXs.
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gt
comp
MUX
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eq
lt
A MODEL OF A DIGITAL
SYSTEM IS DESCRIBED
IS IT TIME TO TRANSLATE IT IN
HARDWARE?
CAN WE SIMULATE THE
RESULTS?
IS IT POOSIBLE TO SEE
AND ANALYZE THE
SYSTEM PERFORMANCE?
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SIMULATING DESCRIPTION
OF DIGITAL DESIGN
 A digital component is modeled in VHDL but not proven yet.
 Model a ’TESTBENCH’ in VHDL to prove the performance of
designed part.
 ’TESTBENCH’ applies stimulus to the design and simulates
the response of system.
In stimulus we assign inputs to the
system.
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TESTBENCH
RST
SUM
A
B
CIN
Full Adder
COUT
TESTBENCH
RST
Stimulus
A
B
SUM
Full Adder
CIN
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COUT
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TESTBENCH BY XILINX
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TESTBENCH BY XILINX
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PRACTICAL
LET WE MODEL THIS IN VHDL WITH XILINX
START XILINX
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SYNTHESIZE
LET TRANSLATE OUR MODEL INTO
HARDWARE
RST
A
B
CIN
SUM
Full
Adder
COUT
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User IOs
 8 slide switches.
 8 LEDs
DIGILENT
 4 push
buttonsNEXYS2
 4 seven segment displays
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SYNTHESIZE
User IOs
 8 slide switches.
 8 LEDs
 4 push buttons
 4 seven segment
displays
Use Adept from
Digilent to load the
bit file in FPGA.
FPGA
.ucf file gives
connection
map
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Top VHDL file
Gives top interface
of the system.
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Home Exercise:
VGA:
Read about VGA controller to know that how it works.
VGA reference document and VHDL code is given at:
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400
,789&Prod=NEXYS2
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