LECTURE 1
oVon-Neumann Architecture
oRegisters
oVon Neumann Architecture
oVon Neumann SAP
oInstruction Set
oInstruction execution
oVon Neumann Architecture’s limitation
oHarvard Architecture
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The Basic Register
oA register is a storage device that is capable of
holding the collection of one or more bits.
D0
Clk
R,/W
En
Dn-1
0
1
.
.
D0
N bit Register
n-1
Dn-1
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Data Transfer between registers
1 01 1
Control Signal
R1,
/W1
Clk
0
En1
1
.
n1
.
D0
Dn-1
D0
Clk
R2,/W2
0
Dn-1
1
.
n1
.
En2
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VON NEUMANN ARCHITECTURE
Execution unit
MAR
Memory
ALU
Register A
Register B
Both data and instructions
at the same system bus
C
P
U
PC
IR
Output Register
Controller
Control unit
Binary Display
System bus
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VON NEUMANN SAP
Lm
Clk
Ea
Register A
MAR
S
E
ALU
RAM
16 x 8
La
Register B
CE
CPU
Lb
Clk
clr
Ep
Cp
PC
PC
Lo
Output Register
clr
Li
Ei
IR
Clk
Controller
Binary Display
clr
Simple As Possible Computer
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Components in a microprocessor system
INSTRUCTION SET
The instruction set specifies the basic operations
supported by the machine.
It provides an interface to the underlying hardware.
It expresses the machine’s ability to transfer data, store
data, operate on data and make decisions.
o Arithmetic and Logic Instruction.
o Looping and decision making.
o Transfer of data.
o Transfer of control.
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Components in a microprocessor system
INSTRUCTION SET
The entities that instructions operate on are denoted
operands.
The number of operands that an instruction operate on
is called arity of operation.
ADD 9H
ADD R1,R2
z = x+y;
x = x+y;
x++;
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More on
INSTRUCTIONS
Operand 0
(Source and/or Destination)
Operation
15
x
x
0
Operand 2
Src / Dest
Operation
15
Operand 0
Source
Operand 1
Src / Destination
Operation
15
0
Operand 1
Src
x
Operand 0
Src
0
oThe size of operation field is determined by the number of
instructions a machine supports.
oEach instruction is given a unique code called op-code
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Components in a microprocessor system
INSTRUCTION SET FOR SAP
Instruction Operation
000
001
010
011
111
Load RAM data into Register A
Add RAM data to RegisterA
Subtract RAM data from RegisterA
Load RegisterA into Output register
Stop Processing
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Components in a microprocessor system
INSTRUCTION SET
These numbers, called op-codes can be stored in program
memory and can be fetched by the computer during execution.
Mnemonic names are given to op-code’s binary pattern to make
them easier to work with.
Mnemonics Op-codes
LDA
ADD
SUB
OUT
HLT
0000
0001
0010
0011
1111
Operation
Load RAM data into Register A
Add RAM data to RegisterA
Subtract RAM data from RegisterA
Load RegisterA into Output register
Stop Processing
Assembler translate these mnemonics to op-codes
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Components in a microprocessor system
INSTRUCTION SET
LDA instruction includes the hex address of the data to be
loaded.
LDA 8H
ADD instruction includes the address of the word to be added
into RegisterA.
ADD 9H means ‘add the contents of memory location 9H to the
RegisterA’; the sum replaces the original contents of RegisterA
SUB instruction includes the address of the word to be
subtracted.
RegisterB holds the word to be operated, adder/sub compute
instantly and the result is written on RegisterA.
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Components in a microprocessor system
PROGRAMMING SAP
Address
0H0H
1H
Address
Data
6H
FFH
7H
FFH
8H
FFH
9H
01H
AH
04H
BH
02H
CH
03H
DH
FFH
EH
FFH
FH
FFH
Mnemonics
:
LDA
9H
0000
1001
ADD AH
2H
ADD BH
3H
SUB CH
4H
OUT
5H
HLT
How instructions are stored in
the memory?
Assembly language: language of mnemonics
Machine language : language of 1,0 strings
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ADDRESSES
Lm
Clk
Ea
Register A
MAR
La
o Each location in memory has an
S
associated address.
ALU
E
RAM
16 x 8
o Information is accessed in memoryLbby
Register B
giving that.
CE
CPU
Clk
o If a memory has 16 locations, it will
have 16 addresses. PC
PC
Lo
Output Register
o Address word size to access all the
IR
locations?
MSB
N-1
0
Controller
Binary Display
clr
Ep
Cp
clr
Li
Ei
Clk
Big Endian
clr
0
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MSB
Little Endian
EpCpEiLiEaLa S E N-1
LbLmCE Lo
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INSTRUCTION EXECUTION CYCLE
Ea
Register A
Lm
Clk
La
MAR
ALU
RAM
16x8
S
E
Register B
CE
CPU
PC
Lo
Lb
Clk
clr
PC
Cp
Output Register
clr
Li
Ei
IR
Clk
Controller
Binary Display
clr
PC  MAR
EpCpEiLiEaLa S E LbLmCE Lo
Fetch instr.
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Instruction Execution Cycle
Ea
Register A
Lm
Clk
La
MAR
ALU
RAM
16x8
S
E
Register B
CE
CPU
PC
Lo
Lb
Clk
clr
PC
Cp
Output Register
clr
Li
Ei
IR
Clk
Controller
Binary Display
clr
PC Inc
EpCpEiLiEaLa S E LbLmCE Lo
Fetch instr.
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Instruction Execution Cycle
Ea
Register A
Lm
La
Clk
MAR
0H:0000 1001
ALU
Register B
RAM
16x8
CE
S
E
CPU
PC
Lo
Lb
Clk
clr
PC
Cp
Output Register
clr
Li
Ei
0000 1001
IR
Clk
Controller
Binary Display
clr
Mem  IR
EpCpEiLiEaLa S E LbLmCE Lo
Fetch instr.
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Instruction Execution Cycle
Lm
Ea
Register A
1001
La
Clk
MAR
0H:010 1001
ALU
1001
Register B
RAM
16x8
CE
S
E
CPU
PC
Lo
Lb
Clk
clr
PC
Cp
Output Register
1001
clr
Li
Ei
0000 1001
1001
IR
Clk
1001
Controller
Binary Display
Fetch instr.
clr
Decode instr.
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Instruction Execution Cycle
Register A
Ea
Lm
00000001
1
La
MAR
ALU
S
E
0
0H:010 1001
0
Clk
00000001
CPU
0
CE
PC
Clk
clr
PC
Cp
0
Lo
Register B
0
RAM
16x8
Lb
00000001
00000001
0
0
Output Register
clr
Li
Ei
0000 1001
IR
Clk
Controller
Binary Display
Fetch instr.
clr
Decode instr.
Fetch operand
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Instruction Execution Cycle
Register A
Ea
Lm
00000001
1
La
MAR
ALU
S
E
Lb
0
0H:010 1001
0
Clk
00000001
CPU
0
CE
PC
Clk
clr
PC
Cp
0
Lo
Register B
0
RAM
16x8
00000001
00000001
0
0
Output Register
clr
Li
Ei
0000 1001
IR
Clk
Controller
Binary Display
Fetch instr.
clr
Decode instr.
Fetch operand
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Execute
Write result
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DATA TRANSFER INSTRUCTIONS
Responsible for moving data around inside the processor .
Bringing data in from outside and sending data out.
Each data transfer instruction has three pieces of information:
o The data
oThe source
oThe destination.
 The source and destination can be:
o A register
o Memory
o IO port
The path to actual selection of operands is controlled by ‘addressing
mode’ specified by operand.
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DATA TRANSFER INSTRUCTIONS
A portion of each operand field is designated as specification to the
hardware as how to interprete the information in the remaining bits of
operand fields.
A microprocessor design implements four to eight addressing
modes.
 Common addressing modes are:
o Immediate
oDirect and Indirect
oRegister Direct and Register Indirect
oIndexed
oProgram counter Relative.
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DATA TRANSFER INSTRUCTIONS
 Common addressing modes are:
oDirect and Indirect
o Immediate
oRegister Direct and
Register Indirect
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DATA TRANSFER INSTRUCTIONS
 Common addressing modes are:
oIndexed
oProgram
Relative
counter
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VON NEUMANN LIMITATION
The shared bus between the program memory and data memory
leads to the Von Neumann bottleneck.
 Because program memory and data memory cannot be accessed
at the same time, throughput is much smaller than the rate at which
the CPU can work.
The CPU is continuously forced to wait for needed data to be
transferred to or from memory.
For example if we try to read an operand at the same time as we
try to read an instruction. This is not possible in the von Neumann
architecture since we only have one system bus and cannot
address two memory positions simultaneously.
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Other Architectures
HARVARD ARCHITECTURE
In the Harvard architecture this is
solved by having two separate system
buses:
oOne for instructions
oOne for data
oData and instructions can be
loaded simultaneously, which
improves the efficiency.
Program
Memory
Program system Bus
CPU
Computer
Memory
Data system Bus
Means more I/O signals.
oMore expensive processor.
oUses more power.
Is used internally in modern 32-bit
microprocessors and RISC processors.
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IOs
MICROPROCESSOR SYSTEM DESIGN
General Purpose Computer e.g
PC
A general-purpose computer, such
as a personal computer (PC), is
designed to be flexible and to meet
a wide range of end-user needs.
Embedded Systems
An embedded system is designed
and optimized to perform a specific
task very efficiently.
They are different in:
o Resources
o Real time.
o Robustness
o Outer world interaction (IOs)
o Program structure
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MICROPROCESSOR SYSTEM DESIGN
Embedded Systems
Microprocessor based systems:
An embedded system is designed
and optimized to perform a specific
task very efficiently.
A microprocessor is an integrated
implementation of central processing
unit portion (CPU).
Use separate integrated circuits for
memory and peripherals.
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MICROPROCESSOR SYSTEM DESIGN
Embedded Systems
Microcontroller based systems:
An embedded system is designed
and optimized to perform a specific
task very efficiently.
A microcontroller brings together a
microprocessor core and a rich
collection of peripherals and IO
capability into single integrated
circuit.
Reduces cost and size.
Timers, ADC, DAC, DIO, serial and
parallel communication channels,
DMA
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INSTRUCTION ADDRESSING
MODES
Instruction Architecture
Opcode
0
Operand1
Operand2
3 4
Instruction: Add with register
Opcode : 0011 or 3
Operand : address of memory location,
register or constant
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RISC vs CISC
Addressing modes
29
Components in a microprocessor system
PROCESSOR TYPES:
CISC (Complex Instruction Set Computer)
oThe primary goal of CISC architecture is to
complete a task in as few lines of assembly as
possible.
oThis is achieved by building processor
hardware that is capable of understanding and
executing a series of operations.
o"MULT“. When executed, this instruction loads
the two values into separate registers, multiplies
the operands in the execution unit, and then
stores the product in the appropriate register.
Thus, the entire task of multiplying two numbers
can be completed with one instruction:
oMULT 2:3, 5:2
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Components in a microprocessor system
REDUCED INSTRUCTION
SET COMPUTING
RISC (Reduced Instruction Set Computer)
oRISC processors only use simple instructions that can be executed
within one clock cycle.
o Thus, the "MULT" command described above could be divided into
three separate commands:
oLOAD, which moves data from the memory bank to a register,
oPROD, which finds the product of two operands located within the
registers.
oSTORE, which moves data from a register to the memory banks.
oA programmer would need to code four lines of assembly:
LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
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Components in a microprocessor system
MEMORY:
 To store data or instructions
the computer system uses a socalled primary memory
The executable program code
and data is stored in main
memory.
The primary memory is divided
in two main parts
The memory can be seen as a
number of post boxes
o RAM
o ROM
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Von Neumann Architecture
MICROCONTROLLERS
What does a computer system
comprise:
oProcessor (CPU, Central Processing
Unit)
oMemory
oPeripheral units, I/O
oSystem bus, to communicate with
peripheral units
If we have a chip that comprise all this it
is often called a ‘Micro Controller’
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Primary Memory
RAM
CPU
ROM
I/O unit
The outer world/ The user
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Components in a microprocessor system
PROCESSOR SYSTEM BUS
 Data bus
oCommunication channel to move data to and from CPU and
peripheral units.
 Address bus
oUsed to point out which memory position or IO port that is to
be read or written.
 Control signals
o Used to signal when a data
transaction starts and stops.
o For example signals if a
transaction is a read or write
operation.
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REFERENCES
Lecture slides: Benny Thörnberg, Mattias O’ Nils
Video Lecture: Prof. Anshul Kumar
http://www.computersciencelab.com/ComputerHistory/History.htm
Webopedia
http://www.world-war-2-planes.com/american-world-war-2-planes.html (slide 12)
http://www.anvari.org/cols/Typewritter_ASCII_Art/Steam_Engine_Number_3.html
(slide 10)
http://www.old-computers.com/history/detail.asp?n=61 (slide 15)
http://www.freewebs.com/computingstudies/S1_UT_Systems/S1UTSystems_07.ht
m
http://www.computer-museum.org/index.html
http://www.ucdsb.on.ca/school/sla/aboutus/Pages/ExamSchedule.aspx
http://www.youtube.com/watch?v=AqbyMRs3ocs
Camera Pills Use MEMS Micro Reed Sensors to Activate the Battery
http://en.wikipedia.org/wiki
http://www-cs-faculty.stanford.edu/~eroberts/courses/soco/projects/risc/risccisc/
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