3D ON-CHIP NETWORK
ARCHITECTURES
Anjie Cao
OUTLINES & PAPERS
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Author: Rohit Sunkam Ramanujam
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Paper #1 : "Randomized Partially-Minimal Routing: Near-Optimal Oblivious
Routing for 3D Mesh Networks," IEEE Transactions on VLSI (TVLSI), vol. 9, no.
11, November 2012, pp. 2080-2093.
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Paper #2: "A Novel 3D Layer-Multiplexed On-Chip Network,"ACM/IEEE
Symposium on Architectures for Networking and Communications Systems
(ANCS), Princeton, NJ, October 19-20, 2009.
Author: Amir-Mohammad Rahmani
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Paper #3 : ”Congestion aware, fault tolerant, and thermally efficient inter-layer
communication scheme for hybrid NoC-bus 3D architectures” Networks on Chip
(NoCS), Publication Year: 2011 , Page(s): 65 – 72
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Paper #4: "Generic Monitoring and Management Infrastructure for 3D NoC-Bus
Hybrid Architectures” Networks on Chip (NoCS), Publication Year: 2012 ,
Page(s): 177 - 184
BACKGROUND
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Importance of 3-D NOC Architecture:
Global interconnect is the major concern in SOC
design.
 Compare to 2-D, 3-D reduce the interconnect length
which allow for performance enhancement.
 In addition : Reduce wire delay/ reduce chip footprint
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Goal of 3-D NOC Architecture:
Maximize throughput
 Minimize hop- count  Minimize Delay
 Minimize power consumption
 Reduce Thermal issues
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#1 3-D MESH ARCHITECTURE
• 2 horizontal dimension ( X & Y), 1 vertical dimension (Z).
• Vertical interconnects implemented using ThroughSilicon-Vias (TSVs)
• 7 * 7 Crossbar
Layer
#2 3-D LAYER-MULTIPLEXED (LM)
ARCHITECTURE (COMPARE TO #1)
Replace the vertical connection with an injection
stage & an ejection stage.
 reduce 7 * 7 crossbar  5 * 5 crossbar
 Change one-layer-per-hop routing  Single hop
vertical routing.
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3-D MESH(#1) VS 3-D LM(#2)
Throughput & latency evaluation
#3 STACKED (HYBRID NOC-BUS) MESH
ARCHITECTURE
Add an extra physical channel for vertical
communication.
 Each packet is traversed through only one buffer
instead of two buffers
 7 * 7 Crossbar  6 * 6 Crossbar
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block
Input buffer
Output buffer
BUS
Figure 1: overview in the same layer
Figure 2: 3-D overview
#4 ARB-NET UTILIZED BUS ARBITER
ARCHITECTURE
Add a monitoring platform called ARB-NET
 Make bus arbiter exchange information directly
with each other without using data network
 ARB-NET node: measuring unit, control unit &
arbitration unit.
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Figure 1: ARB-NET Unit
Figure 2: 3-D overview
STACKED BUS(#3) VS ARB-NET BUS(#4)
Avg. Power Consumption (W)
2.85
2.8
2.75
2.7
2.65
2.6
2.55
2.5
2.45
Stacked bus
ARB-NET
Throughput & latency evaluation
DRAWBACKS & NEW IDEA
#2 LM: less crossbar & less power, but hard to
control the thermal issue.
 #4 ARB-NET: easy to control thermal issue, but
high power consumption.
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New Idea: Add a Net on the ejection stage to
decide the percentage rate to accept from each
layer base on the measure thermal unit.
Thermal unit
P