K&H MFG. Co., LTD.
Manufacturer, Exporter & Importer for Educational Equipment & Measuring Instrument
CIC-310
CPLD/FPGA Development System
CIC-310 CPLD/FPGA Development System
§ CPLD / FPGA Background
§ Hardware Overview
--- System Overview
--- Development Board
--- Experiment Board
§ Design Flowchart
--- Experiment Flowchart
--- Programming Flowchart
--- Program manager
§ Experiments
--- List of experiments
--- Implementations
CIC-310 CPLD/FPGA Development System
§ CPLD / FPGA Background
§ Hardware Overview
--- System Overview
--- Development Board
--- Experiment Board
§ Design Flowchart
--- Experiment Flowchart
--- Programming Flowchart
--- Program manager
§ Experiments
--- List of experiments
--- Implementations
§ CPLD/FPGA BACKGROUND – (1)
Traditional design flow of the logic circuit
Design
specification
In = A, B, C, D ...
Out = X, Y …
Manual
Truth table
Manual (K-map)
Boolean
expression
Manual
Implement on
several ICs
X = (Ā+B+C) (B+D) ( Ā+D )
PAL – Programmable Array Logic
Programmable AND array followed by fixed fan-in OR gates
A
B
C
Programmable switch or fuse
f1  A  B  C  A  B  C
AND plane
PLD - Programmable Logic Device
A
B
C
D
Q
Q
PLD
HDL : Hardware Description Language
A
B
C
D
S0
S1
AND plane
Q
CPLD (Complex PLD) Structure
Integration of several PLD blocks with a
programmable interconnect on a single chip
PLD
Block
•
•
•
•
•
•
I/O Block
PLD
Block
I/O Block
I/O Block
•
•
•
Interconnection Matrix
I/O Block
•
•
•
PLD
Block
PLD
Block
FPGA Look-Up Tables (LUT)
• Look-up table with N-inputs can be used to implement
any combinatorial function of N inputs
• LUT is programmed with the truth-table
A
B
C
D
Z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
Truth-table
A
B
C
D
LUT
Z
LUT implementation
A
B
Z
C
D
Gate implementation
• FPGAs vs. CPLDs
• Are FPGAs and CPLDs the same thing? No. Both are
programmable digital logic chips. Both are made by the same
companies. But they have different characteristics.
• FPGAs are "fine-grain" devices. That means that they contain a lot
(up to 100000) of tiny blocks of logic with flip-flops. CPLDs are
"coarse-grain" devices. They contain relatively few (a few 100's max)
large blocks of logic with flip-flops.
• FPGAs are RAM based. They need to be "downloaded" (configured)
at each power-up. CPLDs are EEPROM based. They are active at
power-up (i.e. as long as they've been programmed at least once...).
• CPLDs have a faster input-to-output timings than FPGAs (because
of their coarse-grain architecture, one block of logic can hold a big
equation), so are better suited for microprocessor decoding logic for
example than FPGAs.
• FPGAs have special routing resources to implement efficiently
binary counters and arithmetic functions (adders, comparators...).
CPLDs do not.
• FPGAs can contain very large digital designs, while CPLDs can
contain small designs only.
FPGA & CPLD
•
FPGAs are RAM based. They need to be "downloaded" (configured) at each
power-up. CPLDs are EEPROM based. They are active at power-up (i.e. as long as
they've been programmed at least once...).
•
FPGAs can contain very large digital designs, while CPLDs can contain small
designs only.
•
CPLDs have a faster input-to-output timings
§ CPLD/FPGA BACKGROUND – (2)
Modern design flow of the logic circuit
Design
specification
In = A, B, C, D ...
Out = X, Y …
Manual
(programming)
Design
description
Automatic
Implement on ONE
CPLD/FPGA chip
Save lots of time!!!
HDL Syntax
SOPC (System On Programmable Chip)
MCU
MPU
Decoder
PWM
FPGA/CPLD
Converter
Memory
ALU
Counter
GPIO
Control
Timer
CIC-310 CPLD/FPGA Development System
§ CPLD / FPGA Background
§ Hardware Overview
--- System Overview
--- Development Board
--- Experiment Board
§ Design Flowchart
--- Experiment Flowchart
--- Programming Flowchart
--- Program manager
§ Experiments
--- List of experiments
--- Implementations
§ System Overview
CIC-310
=
CPLD/FPGA
Development Board
+
Experiment Board
CIC-310 provides digital system designers with an
economical solution for hardware verification or students
with an efficient learning of digital system design.
§ Hardware Overview – Development Board
89C2051 for load the configuration data to
FPGA or SEEPROM devices with data
compression techniques
Reset button:
Reset connection
to PC
Program
selector jumper
Altera 8k/10k
RAM-based FPGA
Max. 32kB SEEPROM
HIN230 for RS-232
transmitters/receivers
interface circuits
11.0592MHz Xosc
RS232 connector
7.5C DC Power
§ Hardware Overview – Experiment Board
16-Segment Display Section
6-Digit Parallel-Serial 7-segment Display
Output Logic LED Display
20MHz X’TRAL OSC
5 x 7 DOT LED display
RC Oscillator
Logic Switch Input Section
SW and Keypad Section
Pulse generator
Input Status Logic LED Display
CIC-310 CPLD/FPGA Development System
§ CPLD / FPGA Background
§ Hardware Overview
--- System Overview
--- Development Board
--- Experiment Board
§ Design Flowchart
--- Experiment Flowchart
--- Programming Flowchart
--- Program manager
§ Experiments
--- List of experiments
--- Implementations
§ EXPERIMENT FLOWCHART
Windows
98/2000/XP
Programming
Rs-232
Download the
program
Personal
Computer
Development
Board
Program manager
Show the
result
Experiment
Board
§ Programming Flowchart
§ Program manager functions
Add the program to
SEEPROM
Execute the program
from SEEPROM
Download the program to
FPGA and execute the program
CIC-310 CPLD/FPGA Development System
§ CPLD / FPGA Background
§ Hardware Overview
--- System Overview
--- Development Board
--- Experiment Board
§ Design Flowchart
--- Experiment Flowchart
--- Programming Flowchart
--- Program manager
§ Experiments
--- List of experiments
--- Implementations
§ LIST OF EXPERIMENTS
• Combinational logic circuits
–
–
–
–
Applications of ALUs
Encoder / Decoder
Alpha-Nemaric LED display
Multiplexer / Demultiplexer
• Sequential logic circuits
– Flip-flop circuits
– Applications of counters
– Frequency synthesizers / Shift Registers
• Dynamic 5x7 LED matrix display
• 4x4 keypad of matrixes
More than 50 examples in the experimental manual!!!
Implementations
Exp1 : Step by step design of basic logic circuit by Graphic and Text Editor
Exp2 : Binary-to-16-segment decoder
Exp3: Counters
Exp4: 5X7 DOT matrix display
Exp5: Keypad
Exp1: Basic logic circuit design (Primal.gdf)
Specification:
Output : P55, P56, P57, P58
Input: DIP switches
Output: LED display
Relation:
P55 = !P01
P56 = P02 & P03
P57 = P04 # P06
P58 = P07 $ P08
! => NOT
& => AND
# => OR
$ => XOR
Input: P01, P02, P03, P04, P06, P07, P08
Step 1: Programming by graphic editor
P01
P55
P02
P03
P56
P04
P06
P57
P07
P08
P58
Step 2: Assign Devices (Assign / Devices)
Step 3: Save&Compile (Max+Plus II / Compiler)
Step 4: Simulation ( 1. Max+Plus II / Waveform Editor )
( 2. Max+Plus II / Simulator)
Step 4: Pin Assignment ( Max+Plus II / Floorplan Editor)
Step 5: Download the program
Execute the program from
SEEPROM
Add the program to
SEEPROM
Download the program to FPGA
and execute the program
Program by Text Editor --- Primal.tdf
The rest design steps are the same
Exp2: Binary-to-16-segment decoder
Specification:
Output : 16-segment display
Input: DIP switches
Output: 16-segment display
Relation:
6 bit inputs are decoded to
16-segment display as:
Numerical number : 0~9
Alphabet letters : A~Z
Math Operators: ＊, +,-,/
Why you need 6-bit input?
0~9  10
A~Z  26
＊,+,-,/  4
10+26+4=40
2^6 = 64 > 40
Input: P01, P02, P03, P04, P06, P07
Program by Text Editor --- 16segb.tdf
.
.
.
Symbol
a1
a2
b1
b2
c1
c2
d1
d2
e1
e2
g1
g2
h1
h2
i1
i2
/p
Position
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Pin Assignment (1)
2
1
16segment
FPGA
8K
10k
16segment
FPGA
8K 10k
A1
P13
P16
E2
P23
P27
A2
P14
P17
G1
P24
P28
B1
P15
P18
G2
P25
P29
B2
P16
P19
H1
P27
P30
C1
P18
P21
H2
P28
P35
C2
P19
P22
I1
P29
P36
D1
P20
P23
I2
P30
P37
D2
P21
P24
DP
P63
P64
E1
P22
P25
C-SEL
P23
P27
Table 1-6 16 segment display pin-out (8k-84pin)
Pin Assignment (2)
P13
P14
P27 P24 P29
P15
P21
P22
P20
P30 P25 P28
P19
Symbol
Segment
Pin
P23
P16
P63
P18
a1
a2
b1
b2
c1
c2
d1
d2
e1
e2
g1
g2
h1
h2
i1
i2
/p
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
13
14
15
16
18
19
20
21
22
23
24
25
27
28
29
30
63
Show Result
FPGA
JP8
JP8
FPGA Pin
Symbol
JP9
JP9
JP10
JP10
16
17
18
19
21
22
23
24
25
27
28
28
30
35
36
37
64
a1
a2
b1
b2
c1
c2
d1
d2
e1
e2
g1
g2
h1
h2
i1
i2
/p
Exp3: Counters
Specification:
Output : P55, P56, P57, P58
Construct a 4-bit asynchronous
counter by T flip-flops
Input: Enable: Sw1_1
Reset: Sw1_2
Clock: SWP3
Output: LED display
Relation:
The 4-bit ripple counter repeats
itself for every 2^4 (16) clock
pulses. :
Input: Sw1_1, p01 (Enable)
Sw1_2, P02 (Reset)
SWP3, P83 (Clock)
Asynchronous Counter: Program by Graphic Editor --- 4slcnt.gdf
Asynchronous Counter: Program by Text Editor --- 4slcnt.gdf
TFF primitive
Asynchronous Counter: Program by Text Editor --- 4slcnt.gdf
FF[]=FF[]-1;
Synchronous Counter: Program by Graphic Editor --- ptcnt8.gdf
Synchronous Counter: Program by Text Editor --- ptcnt8t.tdf
Delay Matrix
Asynchronous Counter
Synchronous Counter
4 Digit Counter: Frequency Counter --- pdec9999.tdf
Input: Clock
Output: LED Display
(Counting 0~9999 in binary format)
7 segment displayer --- 7segd.tdf
Input: DIP switch
Output: 7 segment displayer
SA SB SC SD SE SF SG
4 Digit Counter: Parallel mode --- 4dec7sp.tdf
Require Pins: 6 x 4 = 24
01 2 34 5 6 7 89 01 2 34 5 6 7 89 01 2 34 5 6 7 89
4 Digit Counter: Serial Scan mode --- 4dec7sn.tdf
Require Pins: 6 x 1 + 4 = 10
0
1
0
2
0
3
0
4
0
5
Exp4: 5x7 dot matrix display
5x7 Matrix DOT display (dot_test.tdf)
P13
PA1
P14
PA2
P15
PA3
P16
PA4
P18
PA5
P19
PA6
P20
PA7
P22P23P24P25P27
1
0
1
0
1
0
1
5x7 DOT Matrix display (dot_test.tdf)
Counter
P13
PA1
P14
PA2
P15
PA3
P16
PA4
P18
PA5
P19
PA6
P20
PA7
P22 P23 P24 P25 P27
TRY 57dots.hex !!!
Exp5: Keypad
P48
P43
P39
P34
Individual Mode --- require 16 ports
P49
P44
P40
P35
P50
P45
P41
P36
P51
P46
P42
P37
Parallel Mode => PKI1, PKI2, PKI3
Serial Mode => SCN1, SCN2, SCN3
Scan Mode --- require 8 ports
Output : P53, P54, P58, P59
A: Mechanical Shock Wave Test
( key_test.tdf )
Input: SW0
B: Debounce Circuit Design
(debounce_test.tdf )
Detect 16 times
C: Keypad Circuit Design with debounce function --- Parallel Mode
(16_KEY_Parallel.tdf)
Parallel Mode => PKI1, PKI2, PKI3
Serial Mode => SCN1, SCN2, SCN3
D: Keypad Circuit Design with debounce function --- Scan Mode
(16_key_scan.tdf)
Parallel Mode => PKI1, PKI2, PKI3
Serial Mode => SCN1, SCN2, SCN3
DECODE
00
01
S[1..0]
10
11
0  SR[ ]=SR[ ]+1
1  SR[ ]=SR[ ]
DEB
DEB
DEB
DEB
DEB [3..0]
O
E: Keypad Circuit Design with debounce function & 7-segment display
(.tdf)
MPU
DSP
CPLD
FPGA