Chapter 4 9S12 Architecture
From the text by Valvano:
Introduction to Embedded Systems:
Interfacing to the Freescale 9S12
Chapter 4 Objectives
• Present the basic microcomputer
architecture
• Study software execution at the bus cycle
level
• List three 9S12 microcomputers and their
memory and I/O port configurations
• Describe the timer and use it to create
fixed time delays
4.1 Introduction
• 4.1.1 Big and Little Endian
– Freescale microcomputers implement the big
endian approach for data storage—the most
significant byte first.
– Intel microcomputers implement the little
endian approach—the least significant byte is
stored first.
– Consider storage of 1000 ($03E8) –Figure
4.1, page 112 of the text.
4.1 Introduction
• 4.1.2 Memory-Mapped I/O
– The architecture defines how the processor,
RAM, ROM, and I/O devices are connected.
– The 9S12 implements Memory-Mapped I/O.
– The I/O devices are connected to the
processor in a manner similar to memory
(see Figure 4.4, page 113 of text).
4.1 Introduction
• 4.1.3 I/O Mapped I/O—the control bus for
the I/O is separate from that for memory.
• See Figure 4.5, page 113.
• 4.1.4 Segmented or Partitioned
Memory— memory is divided into different
groups, according to function—the Intel
8051 has 3 segments.
4.1.5 Memory Bus Cycles
• The bus contains address, data , and
control information.
– Address– specifies which module will
communicate with the processor.
– Data—the information being transferred.
– Control—indicates the direction of transfer.
• A bus cycle is a complete data transfer.
Checkpoints
• Checkpoint 4.1: The 9S12C32 has a 16-bit
address bus. How many locations can it
address?
• Checkpoint 4.2: Both the 9S12DP512 and the
9S12E128 can access 1 mebibyte, including
internal and external memory. How many
address lines are in their busses? (recall Table
3.3, page 59).
• Checkpoint 4.3: The 9S12C32 in single-chip
mode has a 16-bit address bus and a 16-bit data
bus, but can still only address 65, 536 bytes of
memory. Why?
4.1.6 Processor Architecture
• BUI—the bus interface unit handles the
read/write access to memory (see Figure 4.9)
– Bus signals are divided into 3 groups: control,
address, and data
• Control—E (the clock that controls the timing of each bus
cycle) and R/W.
• Address-- 16 signals ( the memory address for the current
bus cycle.)
• EAR (Effective address register)—contains current
instruction location (set during third phase of execution.)
4.1.6 Processor Architecture (cont.)
• Registers—temporary storage elements with a
usage defined by instructions.
– Condition Code Register (Figure 4.10)
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S—Stop disable
X—XIRQ Interrupt mask
H—Half carry from bit 3 (used for BCD addition)
I—Interrupt mask
N—Negative
Z—Zero
V—signed oVerflow
C--Carry/borrow or unsigned overflow
– A,B,D,X,Y,SP,PC Registers (Figure 4.9)
4.1.6 Processor Architecture (cont.)
• Arithmetic Logic Unit (ALU) —performs
arithmetic and logic operations.
• Control Unit (CU) —orchestrates the
sequence of operations in the processor
(recall page 34) with the opcode of the
current instruction located in the
instruction register (IR).
Checkpoint
• Checkpoint 4.4: For what do the
acronyms CU BIU and ALU stand?
Phases (page 117)
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Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Phase 6
Opcode and operand fetch
Decode instruction
Evaluate address
Data read
Free cycle
Data write
Phase 1: Op code and Operand
Fetch
• The op code is fetched and placed in the
instruction register (IR).
– Inherent mode –no additional bytes
– Immediate addressing mode—1 or 2 bytes
– Direct addressing mode—1 byte (used to calculate
the effective address).
– Extended Addressing mode—2 bytes (used to
calculate the effective address)
– Indexed Addressing Mode—1,2,or 3 bytes (used to
calculate the effective address)
– PC relative addressing—1 or 2 bytes
Phase 2: Decode Instruction
• Requires no extra bus cycles—processor
determines instruction to be executed.
Phase 3 Evaluate Address
• Usually does not require any bus cycles—
processor calculates the effective address
for the EAR (note: some indirect modes
require addition cycles).
Phase 4: Data Read
• If data is needed from memory, the
contents of the EAR will be used to fetch 1
or 2 bytes from memory.
• These cycles will either be fetches or
stack pulls.
Phase 5: Free Cycles
• Null cycles or free cycles will be generated
if additional time is needed for the result of
the ALU and the setting of the CCR as
needed (simulation will not show these
cycles, but will count them as needed.)
Phase 6: Data Write
• If needed, data is stored in memory (1 or 2
bytes.)
• These cycles will either be data writes or
stack pushes.
Assembly Example (TExaS)
• movw $3800,$240
– Assume the location of the instruction is
$F000.
– 180438000240 contains the opcode and
operands
– [6] indicates the number of cycles
– {ORPWPO} explains the details of the cycle .
– See page 118.
4.1.7 I/O Port Architecture
• Some ports are input only (PE1 and PEO
on the 9S12.)
• See figure 4.11 , page 118.
• There are no latched input ports on the
9S12 (see Figure 4.12 for an example).
• Most of the 9S12 port pins can be inputs
or outputs—Freescale uses a direction
register —see Figure 4.14 for an
illustration of a bidirectional port.
Example 4.1
• Design an I/O driver for a single output
pin.
• Solution: (page 120-121)—initialize, set
and clear (using the instructions bset and
bclr.
4.2 Understanding Software
Execution at the Bus Cycle Level
• More details on bus cycles.
4.3 9S12 Architecture Details
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All 9S12 microcontrollers have a 16-bit central processing unit (HCS12CPU).
System Integration Manual (SIM)
Random Access Memory (RAM)
Electronic Erasable Programmable Memory (EEPROM)
PLL (Phase-locked Loop)
Asynchronous serial communication interface (SCI)
Serial Peripheral Interface (SPI)
Inter-integrated circuit (I2C)
Key wakeup
16-bit timer
Pulse Width Modulation (PWM)
8-bit digital-to-analog converter (DAC)
Liquid Crystal Display (LCD)
Controller area network (CAN 2.0)
Universal serial bus (USB2.0) interface
Ethernet (MAC FEC 10/100) interface
Memory Expansion Logic
4.3.1 9S12C32
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See Figure 4.16
Smaller and lower cost of the 9S12’s.
RAM—2 Kbytes
EEPROM—32 Kbytes
Pin packages—(Table 4.5, page128)
– Also, see Fig. 4.17 (NC12C32 Nanocore 12).
• TExaS does not simulate the external data
bus, SPI, PWM, or CAN.
4.3.2 OS12DP512
• 112 pin module with 91 I/O pins.
• EEPROM—512 Kbytes
– Only 48 K bytes is directly addressable.
– Paged Memory is use the access the rest.
4.3.3 9S12E128
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8 K Bytes of RAM
128 K bytes of EEPROM.
12 input capture/output compare timer pins
12 pulse-width modulated output pins
16 ADC inputs
Two DAC outputs
One SPI module
Three SCI modules
One I2C module
Two sizes: 80 pins and 112 pins.
4.3.4 Operating Modes
• 8 different modes
• BKGD,MODA, and MODB are used to
select the mode (0,0,0—1,1,1).
• Table 4.10, page 134 shows the three
most common.
– Normal single chip
– Normal expanded narrow
– Normal expanded wide
Single—Chip Mode
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Mode used in the Valvano text.
All ports are available for input/output.
RAM—2Kbytes to 32Kbytes
If more RAM is needed, then expanded
narrow and expanded wide modes are
used to interface larger external memory.
4.3.5 Phase-Locked Loop
• Execution speeds are normally determined
by an external clock.
• A slower clock requires less power.
• Some MC9S12C32 boards have an 8 MHz
crystal creating a 4-MHz clock.
• The Phase-Locked Loop allows the
software to adjust the execution speed.
4.4 The Stack
• Two basic operations: Push and Pull or Push and Pop.
• Push—saves data on the top of the stack (decrement SP
then store at SP.)
• Pull—removes data (read at SP then increment the SP).
• Instructions psha and pula use Register A.
• These instructions use inherent addressing and do not
change the CCR.
• Last in first out (LIFO).
• See page 135.
• See Figure 4.21.
Checkpoints
• Checkpoint 4.7: After a psha instruction, how
many copies exist of the data being pushed?
• Checkpoint 4.8: After a pula instruction, how
many copies exist of the daata being pulled?
• Checkpoint 4.9: Assume you have two 8-bit
global variables M and N. Write assembly code
that switches the values in M and N using just
the ldaa staa psha and pula instructions.
4.5 16-Bit Timer
• The 16 bit timer on the 9S12 is called TCNT.
• It is a counter that increments at a fixed rate and can be
used to create pulses, squarewaves, and pulse-width
modulated waves.
• It can also be used to measure the period, pulse-width,
or frequency of an input signal.
• Table 4.12 shows how PR2,PR1 and PR0 (in the TSCR2
register) are used to set the rate of the counter.
• Bit 7 of the TSCR1 register must be set in order to use
TCNT.
• Program 4.5 (page 138 of text) illustrates how to set a
time delay.
4.6 Memory Allocation
• The memory of a PC-compatible computer
is configured as a linear array—segments
are used by the programmer.
• Embedded systems use segmentation.
• Segments could have the following
groups: global variables, heap, local
variables fixed constants, and machine
instructions.
4.7 Performance Debugging
• 4.7.1 Instrumentation
– A prescaler placed between the E clock and
the TCNT counter can be used to measure
timing (with a little intrusiveness.)
– Program 4.7 (page 142 shows how Port T, bit
6, can also be used to measure timing, when
it is attached to an oscilloscope—jsr
statements at “strategic” places can then be
used to mearue the timing.
4.7.2 Measurement of Dynamic
Efficiency
1. Count bus cycles using assembly listing
(only useful for short programs).
2. The internal timer TNT could be used
(program 4.9, page 144 of text).
3. Oscilloscope can be attached to an used
pin. (program 4.10, page 144)—looks
similar to 4.7.1.