Chapter 8 Register Transfer Level
8-1 Register Transfer Level (RTL) Notation
8-2 Register Transfer Level in HDL
8-3 Algorithmic State Machines (ASM)
8-4 Design Example
Chapter 8 Register Transfer Level
8-5 HDL Description of Design Example
8-6 Binary Multiplier
8-7 Control Logic
8-8 HDL Description of Binary Multiplier
8-9 Design with Multiplexers
8-1 Register Transfer Level
(RTL) Notation
A digital system is a sequential logic system
constructed with flip-flops and gates.
Because the number of states would be
prohibitively large, digital systems are designed
using a modular approach instead of state table.
Digital modules are best defined by a set of
registers and the operations that are performed on
the binary information stored in them.
8-1 Register Transfer Level
(RTL) Notation
A digital system is represented at the register
transfer level (RTL) when it is specified by the
following three components:
1. The set of register in the system
2. The operations that are performed on the data
stored in the register.
3. The control that supervises the sequence of
operations in the system.
8-1 Register Transfer Level
(RTL) Notation
The type of operations most often encountered in
digital systems can be classified into four
categories:
1. Transfer operations
2. Arithmetic operations
3. Logic operations
4. Shift operations
8-2 Register Transfer Level in
HDL
In Verilog HDL, RTL descriptions use a
combination of behavioral and dataflow constructs.
Register transfers are specified by means of
procedural assignment statement.
Combinational circuit functions are specified by
means of continuous assignment or procedural
assignment statement.
8-2 Register Transfer Level in
HDL
Examples:
assign S = A + B;
Continuous assignment
always @ (A OR B)
S = A + B;
Procedural assignment
( without a clock )
always @ ( posedge clock) Blocking procedural
begin
assignment
RA = RA + RB;
RD = RA;
end
8-2 Register Transfer Level in
HDL
Examples:
always @ ( negedge clock) Non-blocking
begin
procedural assignment
RA <= RA + RB;
RD <= RA;
end
8-2 Register Transfer Level in
HDL
HDL Operations
Operator type Symbol Operation performed
Arithmetic
+
addition
subtraction
*
multiplication
/
division
%
modulus
Logic
~
negation
(bit-wise or
&
AND
reduction)
|
OR
^
Exclusive-OR
8-2 Register Transfer Level in
HDL
HDL Operations
Operator type Symbol Operation performed
Logic
!
negation
&&
and
| |
or
Shift
>>
shift right
<<
shift left
{,}
concatenation
8-2 Register Transfer Level in
HDL
HDL Operations
Operator type Symbol Operation performed
Relational
>
greater than
<
less than
==
equality
!=
inequality
>=
greater than or equal
<=
less than or equal
8-2 Register Transfer Level in
HDL
Loop statements
Four types of loops :
Repeat, forever, while and for
initial
begin
clock = 1'b0;
repeat (16);
#5 clock = ~ clock;
end
The repeat loop
executes the
associated
statements a
specified number
of times.
8-2 Register Transfer Level in
HDL
Loop statements
initial
begin
clock = 1'b0;
forever
# clock = ~ clock;
end
The forever loop
causes a continuous
repetitive execution
of the procedural
statement.
8-2 Register Transfer Level in
HDL
Loop statements
Interger count;
initial
begin
count = 0;
while ( count < 64)
count = count + 1;
end
The while loop
executes a
statement or block
of statement
repeatedly while an
expression is true.
8-2 Register Transfer Level in HDL
Loop statements
//description of 2x4 decoder
//using for-loop statement
module decoder (IN, Y);
input [1:0] IN; //Two binary inputs
output [3:0] Y; //Four binary outputs
reg [3:0] Y;
integer I;
//control variable for loop
always @ (IN)
for (I = 0; I <= 3; I = I + 1)
if (IN == I) Y[I] = 1;
else Y[I] = 0;
endmodule
Output Y is
evaluated in a
procedural
statement, it
must be
declared as reg
type.
8-2 Register Transfer Level in
HDL
Logic Synthesis
Logic synthesis is the automatic process of
transforming a high level language description
such as HDL into an optimized netlist of gates that
perform the operations specified by the source
code.
8-2 Register Transfer Level in
HDL
Logic Synthesis
The test
bench
provides the
stimulus
signals to the
simulator.
8-2 Register Transfer Level in
HDL
Logic Synthesis
If the result of
the simulation
is not
satisfactory,
the HDL
description is
checked again.
8-2 Register Transfer Level in
HDL
Logic Synthesis
If the result of
the simulation
shows a valid
design, the
RTL
description is
applied to the
logic
synthesizer.
8-2 Register Transfer Level in
HDL
Logic Synthesis
Gate-level
circuit
simulation
8-2 Register Transfer Level in
HDL
Logic Synthesis
If any
corrections
are needed,
the process
will be
repeated.
8-3 Algorithmic State Machine
(ASM)
The logic design of a digital system can be divided
into two distinct parts:
1. Design of the digital circuits that perform the
data processing operations.
2. Design of the control circuits that determines
the sequence in which the various actions are
performed.
8-3 Algorithmic State Machine
(ASM)
The relationship between two parts is shown as
follows,
Commands
External
input
Control
logic
Input
data
Data
path
Output
data
8-3 Algorithmic State Machine
(ASM)
A flowchart is a convenient way to specify the
sequence of procedural steps and decision paths
for an algorithm.
A special flowchart called an algorithmic state
machine (ASM) chart describes the sequence of
events as well as the timing relationship between
the states of a sequential controller and the events
that occur while going from one state to the next.
8-3 Algorithmic State Machine
(ASM)
ASM Chart
The ASM Chart is composed of three basic
elements: the state box, the decision box, and the
conditional box.
State Box
8-3 Algorithmic State Machine
(ASM)
Decision Box
Conditional
Box
8-3 Algorithmic State Machine
(ASM)
ASM Block
The ASM block is a structure consisting of one
state box and all the decision and conditional
boxes connected to its exit path.
The ASM chart is very similar to a state diagram.
It is convenient to convert the chart into a state
diagram and use sequential circuit procedures to
design the control logic.
8-3 Algorithmic State Machine
(ASM)
ASM Block
ASM Block
State diagram
equivalent to the
ASM chart
8-3 Algorithmic State Machine
(ASM)
Timing Consideration
The major difference
between a conventional
flow chart and an ASM
chart is in interpreting
the time relationship
among the various
operations.
8-3 Algorithmic State Machine
(ASM)
Timing Consideration
An ASM chart considers the entire block as one
unit. All the operations that are specified within the
block must occur in synchronism during the edge
transition of the same clock pulse.
8-4 Design Example
Design a digital system with two flip-flops, E and F,
and one 4-bit binary counter A. the individual flipflops in A are denoted by A4 ,A3 ,A2 ,A1 , with A4
holding the most significant bit of the count. A start
signal S initiates the system operation by clearing
the counter A and flip-flop F. the counter is
incremented by one starting from the next clock
pulse and continues to increment until the
operations stop. Counter bit A4 and A3 determine
the sequence of operations:
8-4 Design Example
Counter bit A4 and A3 determine the sequence of
operations:
If A3 = 0, E is cleared to 0 and the count continues.
If A3 = 1, E is set to 1; then if A4 = 0, the count
continues, but if A4 = 1, F is set to 1 on the next
clock pulse and the system stops counting.
Then if S = 0, the system remains in the initial state,
but if S = 1, the operation cycle repeats.
8-4 Design Example
ASM Chart
8-4 Design Example
Timing Sequence
Counter
Flip-Flops
A4 A3 A2 A1
E
F
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Conditions state
A3 =0,
T1
A4 =0
A3 =1,
A4 =0
8-4 Design Example
Timing Sequence
Counter
Flip-Flops
A4 A3 A2 A1
E
F
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
1
Conditions state
A3 =0,
T1
A4 =1
A3 =1,A4 =1
T2
T0
8-4 Design Example
Datapath
Design
8-4 Design Example
Register Transfer Representation
8-4 Design Example
State Table
Present Present
state
Inputs
state
symbol G1 G0 S A3 A4
T0
0 0
0 X X
T0
0 0
1 X X
T1
0 1
X 0 X
T1
0 1
X 1 0
T2
0 1
X 1 1
T2
1 1
X X X
Next
state
outputs
G1 G0
T0 T1 T2
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
8-4 Design Example
Control Logic
the following equation can be derived from the
the state table.
DG1 = T1 A3 A4
DG0 = T0 S + T1
T0 = G'0
T1 = G'1 G0
T2 = G1
8-5 HDL Description of Design
Example
Itstructural
is the mostdescription
abstract level. Some
of the constructs at this level might
not be synthesizable.
Three levels
RTL description
of design: It is the lowest and
most detailed level.
algorithmic-based
behavioral description
//RTL description of design example (Fig.8-9)
module Example_RTL (S,CLK,Clr,E,F,A);
//Specify inputs and outputs
//See block diagram Fig. 8-10
input S,CLK,Clr;
output E,F;
output [4:1] A;
//Specify system registers
reg [4:1] A;
//A register
reg E, F;
//E and F flip-flops
reg [1:0] pstate, nstate; //control register
//Encode the states
parameter T0 = 2'b00, T1 = 2'b01, T2 = 2'b11;
//State transition for control logic
//See state diagram Fig. 8-11(a)
always @(posedge CLK or negedge Clr)
if (~Clr) pstate = T0; //Initial state
else pstate <= nstate; //Clocked operations
always @ (S or A or pstate)
case (pstate)
T0: if(S) nstate = T1;
T1: if(A[3] & A[4]) nstate = T2;
T2: nstate = T0;
default: nstate = T0;
endcase
RTL Description
//Register transfer operatons
//See list of operations Fig.8-11(b)
always @(posedge CLK)
case (pstate)
T0: if(S)
begin
A <= 4'b0000;
F <= 1'b0;
end
T1:
begin
A <= A + 1'b1;
if (A[3]) E <= 1'b1;
else E <= 1'b0;
end
T2: F <= 1'b1;
endcase
endmodule
//Test bench for design example
module test_design_example;
reg S, CLK, Clr;
wire [4:1] A;
wire E, F;
//Instantiate design example
Example_RTL dsexp (S,CLK,Clr,E,F,A);
initial
begin
Clr = 0;
S = 0;
CLK = 0;
#5 Clr = 1; S = 1;
repeat (32)
begin
#5 CLK = ~ CLK;
end
end
initial
$monitor("A = %b E = %b F = %b time =
%0d", A,E,F,$time);
endmodule
Testing the Design
Description
The Clr signal is
set to 0 to
initialize the
control.
The $monitor
statement
displays the
values of A,E,F
every 10ns
//Structural description of design example
//See block diagram Fig. 8-10
module Example_Structure
(S,CLK,Clr,E,F,A);
input S,CLK,Clr;
output E,F;
output [4:1] A;
//Instantiate control circuit
control ctl
(S,A[3],A[4],CLK,Clr,T2,T1,Clear);
//Instantiate E and F flip-flips
E_F EF (T1,T2,Clear,CLK,A[3],E,F);
//Instantiate counter
counter ctr (T1,Clear,CLK,A);
endmodule
//Control circuit (Fig. 8-12)
module control
(Start,A3,A4,CLK,Clr,T2,T1,Clear);
input Start,A3,A4,CLK,Clr;
output T2,T1,Clear;
wire G1,G0,DG1,DG0;
Structural
Description
//Combinational circuit
assign DG1 = A3 & A4 & T1,
DG0 = (Start & ~G0) | T1,
T2 = G1,
T1 = G0 & ~G1,
Clear = Start & ~G0;
//Instantiate D flip-flop
DFF G1F (G1,DG1,CLK,Clr),
G0F (G0,DG0,CLK,Clr);
endmodule
Instantiate
three
components
//Structural description of design example
//See block diagram Fig. 8-10
module Example_Structure
(S,CLK,Clr,E,F,A);
input S,CLK,Clr;
output E,F;
output [4:1] A;
//Instantiate control circuit
control ctl
(S,A[3],A[4],CLK,Clr,T2,T1,Clear);
//Instantiate E and F flip-flips
E_F EF (T1,T2,Clear,CLK,A[3],E,F);
//Instantiate counter
counter ctr (T1,Clear,CLK,A);
endmodule
//Control circuit (Fig. 8-12)
module control
(Start,A3,A4,CLK,Clr,T2,T1,Clear);
input Start,A3,A4,CLK,Clr;
output T2,T1,Clear;
wire G1,G0,DG1,DG0;
Structural
Description
//Combinational circuit
assign DG1 = A3 & A4 & T1,
DG0 = (Start & ~G0) | T1,
T2 = G1,
T1 = G0 & ~G1,
Clear = Start & ~G0;
//Instantiate D flip-flop
DFF G1F (G1,DG1,CLK,Clr),
G0F (G0,DG0,CLK,Clr);
endmodule
Describe the
control and it
D flip-flop
//E and F flipf-lops
module E_F (T1,T2,Clear,CLK,A3,E,F);
input T1,T2,Clear,CLK,A3;
output E,F;
wire E,F,JE,KE,JF,KF;
//Combinational circuit
assign JE = T1 & A3,
KE = T1 & ~A3,
JF = T2,
KF = Clear;
//Instantiate JK flipflop
JKFF EF (E,JE,KE,CLK),
FF (F,JF,KF,CLK);
endmodule
//JK flip-flop
module JKFF (Q,J,K,CLK);
input J,K,CLK;
output Q;
reg Q;
always @ (posedge CLK)
case ({J,K})
2'b00: Q = Q;
2'b01: Q = 1'b0;
2'b10: Q = 1'b1;
2'b11: Q = ~Q;
endcase
endmodule
Structural
Description
//counter with synchronous clear
module counter (Count,Clear,CLK,A);
input Count,Clear,CLK;
output [4:1] A;
reg [4:1] A;
always @ (posedge CLK)
if (Clear) A<= 4'b0000;
else if (Count) A <= A + 1'b1;
else A <= A;
endmodule
Describe the E
and F and their
JK flip-flop
//E and F flipf-lops
module E_F (T1,T2,Clear,CLK,A3,E,F);
input T1,T2,Clear,CLK,A3;
output E,F;
wire E,F,JE,KE,JF,KF;
//Combinational circuit
assign JE = T1 & A3,
KE = T1 & ~A3,
JF = T2,
KF = Clear;
//Instantiate JK flipflop
JKFF EF (E,JE,KE,CLK),
FF (F,JF,KF,CLK);
endmodule
//JK flip-flop
module JKFF (Q,J,K,CLK);
input J,K,CLK;
output Q;
reg Q;
always @ (posedge CLK)
case ({J,K})
2'b00: Q = Q;
2'b01: Q = 1'b0;
2'b10: Q = 1'b1;
2'b11: Q = ~Q;
endcase
endmodule
Structural
Description
//counter with synchronous clear
module counter (Count,Clear,CLK,A);
input Count,Clear,CLK;
output [4:1] A;
reg [4:1] A;
always @ (posedge CLK)
if (Clear) A<= 4'b0000;
else if (Count) A <= A + 1'b1;
else A <= A;
endmodule
Describe the
counter
8-6 Binary Multiplier
When multiplication procedure is implemented
with digital hardware, it provides circuits for
the summation of only two binary numbers and
successively accumulate the partial products in
a register.
The partial product being formed is shifted to
the right.
When the corresponding bit of the multiplier is
0, there is no need to add all 0's the partial
product.
8-6 Binary Multiplier
Register Configuration
Multiplicand
n
Multiplier
Sum
Product
The P counter is
initially set to
hold the number
of bits in the
multiplier and is
decremented
after formation
of each partial
product.
8-6 Binary Multiplier
Register Configuration
The
multiplicand is
stored in
register B.
Multiplicand
n
Multiplier
Sum
Product
8-6 Binary Multiplier
Register Configuration
A parallel adder
adds the
contents of
register B to
register A.
Multiplicand
n
Multiplier
Sum
Product
8-6 Binary Multiplier
Register Configuration
Multiplicand
n
Multiplier
Sum
Product
The control
logic determines
whether to add
or not, based on
this input bit.
8-6 Binary
Multiplier
ASM Chart
8-7 Control Logic
The design
of a digital
system
The design of the register
transfers in the datapath and
the design of the control logic
The design of the control logic
It is a sequential circuit design problem.
It is convenient to formulate the state
diagram of the sequential control.
8-7 Control Logic
State diagram
for the binary
multiplier
8-7 Control Logic
When implementing the control logic, there are
two distinct aspects:
1. establish the required sequence
states
Controlof
block
diagram for
the
binary
multiplier
2. Provide signals to control
the
register
operations.
8-7 Control Logic
The Assignment of Coded Binary Values to the
States
State
T0
T1
T2
T3
Binary
00
01
10
11
Gray code
00
01
11
10
One-Hot
0001
0010
0100
1000
8-7 Control Logic
Sequential Register and Decoder
The Sequential Register and Decoder method
uses a register for the control states and a
decoder to provide an output corresponding to
each of the states.
The sequential circuit can be designed from
the state table by means of the classical
procedure presented in Chapter 5.
8-7 Control Logic
Sequential Register and Decoder
Present
state
G1 G0
0 0
0 0
0 1
1 0
1 1
1 1
Input
S Z
0 X
1 X
X X
X X
X 0
X 1
Next
state
G1 G0
0 0
0 1
1 0
1 1
1 0
0 0
outputs
T0 T1 T2 T3
1 0 0 0
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
0 0 0 1
8-7 Control Logic
Sequential Register and Decoder
The design can be simplified if the fact that the
decoder outputs are available for use in the
design is taken into consideration.
The following equation can be derived from
the state table,
DG1 = T1 + T2 + T3Z'
DG0 = T0 S2 + T2
8-7 Control Logic
DG1 = T1 + T2 + T3Z'
DG0 = T0 S2 + T2
8-7 Control Logic
One Flip-Flop per State
Advantages:
1. Simplicity
2. Saving in design effort
3. A possible decrease in the total number of gates
State diagram for
binary multiplier
8-7 Control Logic
There are four states in the state diagram. Four
flip-flops are chosen and their outputs are labeled
as T0 , T1 , T2 and T3.
The following equation can be derived from the
state table,
DT0 = T0 S' + T3Z
DT1 = T0 S
DT2 = T1 + T3Z'
DT3 = T2
8-7 Control Logic
DT0 = T0 S' + T3Z
DT1 = T0 S
DT2 = T1 + T3Z'
DT3 = T2
//RTL description of binary multiplier
//Block diagram Fig.8-13 and ASM chart Fig.8-14
//n = 5 to compare with Table 8-4
module mltp(S,CLK,Clr,Binput,Qinput,C,A,Q,P);
input S,CLK,Clr;
input [4:0] Binput,Qinput;
//Data inputs
output C;
output [4:0] A,Q;
output [2:0] P;
//System registers
reg C;
reg [4:0] A,Q,B;
reg [2:0] P;
reg [1:0] pstate, nstate;
//control register
parameter T0=2'b00, T1=2'b01, T2=2'b10, T3=2'b11;
//Combinational circuit
wire Z;
assign Z = ~|P;
//Check for zero
//State transition for control
//See state diagram Fig. 8-15(a)
always @(negedge CLK or negedge Clr)
if (~Clr) pstate = T0;
else pstate <= nstate;
always @(S or Z or pstate)
case (pstate)
T0: if (S) nstate = T1;
T1: nstate = T2;
8-8 HDL Description of
Binary Multiplier
RTL description
of binary
multiplier
T2: nstate = T3;
T3: if (Z) nstate = T0;
else nstate = T2;
endcase
//Register transfer operations
//See register operation Fig.8-15(b)
always @(negedge CLK)
case (pstate)
T0: B <= Binput;
//Input multiplicand
T1: begin
A <= 5'b00000;
C <= 1'b0;
P <= 3'b101;
//Initialize counter to n=5
Q <= Qinput;
//Input multiplier
end
T2: begin
P <= P - 3'b001;
//Decrement counter
if (Q[0])
{C,A} <= A + B;
//Add multiplicand
end
T3: begin
C <= 1'b0;
//Clear C
A <= {C,A[4:1]};
//Shift right A
Q <= {A[0],Q[4:1]};
//Shift right Q
end
endcase
endmodule
8-8 HDL Description of
Binary Multiplier
RTL description
of binary
multiplier
//Testing binary multiplier
module test_mltp;
//Inputs for multiplier
reg S,CLK,Clr;
reg [4:0] Binput,Qinput;
//Data for display
wire C;
wire [4:0] A,Q;
wire [2:0] P;
//Instantiate multiplier
mltp
mp(S,CLK,Clr,Binput,Qinput,C,A,Q,P);
initial
begin
S=0; CLK=0; Clr=0;
#5 S=1; Clr=1;
Binput = 5'b10111;
Qinput = 5'b10011;
#15 S = 0;
end
initial
begin
repeat (26)
#5 CLK = ~CLK;
end
8-8 HDL Description of
Binary Multiplier
Testing the
Multiplier
//Display computations and compare with
Table 8-4
always @(negedge CLK)
$strobe ("C=%b A=%b Q=%b
P=%b time=%0d",C,A,Q,P,$time);
endmodule
The $strobe system task provides a
synchronization mechanism to
ensure that are displayed only after
all assignments in a given time step
are executed.
8-8 HDL Description of Binary
Multiplier
Behavioral Description of Multiplier
//HDL Example 8-7
//--------------------------------//Behavioral description of multiplier (n = 8)
module Mult (A,B,Q);
input [7:0] B,Q;
output [15:0] A;
reg [15:0] A;
always @ (B or Q)
A = B * Q;
endmodule
8-9 Design with Multiplexers
Example
Consider the ASM of the
figure and implement with
multiplexers.
8-9 Design with Multiplexers
The purpose of
each multiplexer is
to produce an
input to its
corresponding
flip-flop equal to
the binary value of
the next state.
8-9 Design with Multiplexers
Present
State
Next
State
G1 G0
G1 G0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
1
1
1
1
0
1
1
1
0
1
Input
Condition
w'
w
x
x'
y
yz'
yz
y'z
y
y'z'
Inputs
MUX1
MUX2
0
w
1
x'
yz' +yz=y
yz
y +y'z'
= y +z'
y'z + y'z'
= y'
8-9 Design with Multiplexers
Design Example - Count the Number
of Ones in a Register
The digital system to be designed consists of
two registers, R1 and R2, and a flip-flop, E. The
system counts the number of 1's in the number
loaded into register R1 and sets register R2 to
that number.
8-9 Design with Multiplexers
The control uses one external
input S to start the operation
and two status inputs E and Z
from the datapath.
The binary number is loaded
into R1, and register R2 is set
to an all 1's value.
ASM Chart for Countof-Ones Circuit
8-9 Design with Multiplexers
Block Diagram for
Count-of-Ones Circuit
8-9 Design with Multiplexers
Multiplexer Input Condition
Present
State
Next
State
G1 G0
G1 G0
Inputs
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
Input
Condition
S'
S
Z
Z'
1
0
1
1
None
1
1
1
1
1
1
0
1
1
0
E'
E
E'
E
MUX1
MUX2
0
S
Z'
0
8-9 Design with Multiplexers
Control Implement
for Count-of-Ones
Circuit