Lecture 1
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Every Wednesday: 15:00 hrs to 18:00 hrs :هر اربع وڳي تائين6 وڳي کان3 شام DIGITAL INTEGRATED CIRCUITS FOR COMMUNICATION احسان احمد عرسا ِڻي My Introduction منهنجو تعارف Ahsan Ahmad Ursani Associate Professor Dept. of Telecommunication Engineering Office No: TL-117 Institute of Communication Technologies Email: Web page: احسان احمد عرساڻي ايسوسيئيٽ پروفيسر شعبو ڏور ربطيات TL-117 :دفتر نمبر انسٽيٽيوٽ آف ڪميونيڪيشن ٽيڪناالجيز :برق ٽپال ahsan.ursani@faculty.muet.edu.pk https://sites.google.com/a/fac :ويب صفحو ulty.muet.edu.pk/aau/home The Teaching Plan تدريس ي رٿا Pre-Requisite: IC Design S. No. Chapter Hours 1 Dynamc Combinational CMOS Logic 10 2 Designing Sequential Logic 17 3 Designing Memory and Array Structures 21 Total 48 The Textbook نصابي ڪتاب Digital Integrated Circuits A Design Perspective Jan M. Rabaey Chapter 6, 7, & 12 Chapter 1 باب پهريون S. No. Topic Hours 1 Introduction 1 2 Complementary CMOS 1 3 Ratioed Logic 1 4 Pass-Transistor Logic 1 5 Basic Principles of Dynamic Logic 1 6 Speed and Power Dissipation 1 7 Issues in Dynamic Design 1 8 Casdaing Dynamic Gates 1 9 Choosing a logic Design 1 10 Designing logic for Reduced Supply Voltages 1 Total 10 Static Vs Dynamic Static At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistance path. the outputs of the gates assume at all times the value of the Boolean function implemented by the circuit (ignoring, once again, the transient effects during switching periods). Dynamic Relies on temporary storage of signal values on the capacitance of highimpedance circuit nodes Static Vs. Dynamic Static Dynamic Basic concepts of a dynamic gate An n-type network AB+C Gate Dynamic Logic – Basic Principle Uses N+2 transistors N is the no. Of inputs Uses clock cycle Two phases Pre-Charge Pre-charge PMOS conducts Doesn’t implement logic during the pre-charge phase Evaluation Evaluation NMOS conducts Pre-Charge Unconditionally Charges out to 1 through Mp Evaluation Logically discharges out to 0 through Me and PDN Out CLK A B C CLK Properties of Dynamic Logic Advantages Faster than Static CS CMOS logic Less power consumption than ratioed logic No care in transistor sizing for proper functionality Glitching (or dynamic hazards) does not occur in dynamic logic Disadvantages More power consumption than Static CS CMOS logic There’s a Dead Zone Dynamic logic gates cannot be used during pre-charge phase Power Consumption in Dynamic Logic Non-ratioed logic No static power consumption Only dynamic power consumption During transitions Depends on the switching activity α01 = P0P1 α01 = P0(1) α01 = P0 α01 = N0 /2N N is the number of inputs There are 2N combinations in the TT N0 is the no. of zeros in the TT Problem 6.7: Activity Computation For the 4-input dynamic NAND gate, compute the activity factor with the following assumption for the inputs. Assume that the inputs are independent and pA=1 = 0.2, pB=1 = 0.3, pC=1 = 0.5, and pD=1 = 0.4. A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Page 278 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Comparing 2-input NOR Gates Switching Activity Static α01 = P1 P0 = ¼ ¾ = 3/16 Dynamic α01 = P0 = ¾ Truth Table A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0 4-input NAND gate Characteristics of 4-input Dynamic Gate VOH = VDD VIH = VTN NMH = VDD – VTN tpHL = 0.11 ns Proportional to the no. Of NMOS in PDN VM = VTN VOL = 0V VIL = VTN NML = VTN tpLH = 0 ns tpre = 0.083 nsec Pre-charge time Pre-charge time is a ‘Dead Zone’ Doesn’t apply logic It is the time proportional to the charging time CL Inversely proportional to the width of the precharge PMOS Mp wider Less resistance Less charging time Too large Mp might be slowdown the gate and increase the power dissipation of the clock signal May coincide with other system functions Basic concepts of a P-type dynamic gate A p-type network AB+C Gate Issues in Dynamic Design Charge Leakage Charge Sharing Capacitive Coupling Clock-Feedthrough Charge Leakage Periodic refresh Lower bound on operating frequency Solution Bleeder transistor Charge Sharing During precharge A=B=0 Ca s discharged During evaluation A makes 01 transition while B=0 Ma turns ON The charge stored originally on capacitor CL is redistributed over CL and Ca This causes a drop in the output voltage Charging sharing in 3-i/p XNOR Pre-charge A=0, Evaluation A=0, B=0, C=0 B=1, C=1 VDD =2.5 v Ca Cc V VDD Ca Cc C y 30 V 2.5v 0.94v 30 50 VT 2.5v 0.94v 1.56v Solution to Charge Sharing Precharging critical internal internal nodes The most common and effective approach to deal with the charge redistribution comes at the cost of increased area and capacitance. Capacitive Coupling High o/p impedance floating node very sensitive to crosstalk effects A wire routed over a dynamic node may couple capacitively Backgate coupling O/p Out2 Out1In to i/p coupling Out1 AB Capacitive Coupling High o/p impedance floating node very sensitive to crosstalk effects A wire routed over a dynamic node may couple capacitively Backgate coupling O/p Out2 Out1In to i/p coupling Out1 AB Clock-Feedthrough CC b/w Clock i/p of Preharge device and Dynamic o/p node Cascading Dynamic Gates Designing Logic for Reduced Supply Voltages Problem 6.7 Activity Computation For the 4-input dynamic NAND gate, compute the activity factor with the following assumption for the inputs. Assume that the inputs are independent and PA=1 = 0.2, PB=1 = 0.3, PC=1 = 0.5, and PD=1 = 0.4.
