CEN 226: Computer Organization
&
Assembly Language :CSC 225
(Lec#2)
By
Dr. Syed Noman
2
Course
• This course aims to teach the fundamentals of
computer organization and
architecture through assembly
language programming.
• Topics to be learned:
▫ Basic Computer Organization;
▫ Assembly Language.
3
Computer Architecture and
Organization
•
Architecture is concerned with attributes
visible to the programmer:
▫ Instruction set, number of bits used for data
representation, I/O mechanisms, addressing
techniques.
• Organization
is
how
features
are
implemented:
▫ Control
signals,
interfaces,
memory
technology.
4
Computer architecture
• Computer architecture deals with the functional
behavior of a computer system as viewed by a
programmer (like the size of a data type – 32
bits to an integer).
• All Intel x86 family share the same basic
architecture.
5
Computer organization
• Computer organization deals with structural
relationships that are not visible to the
programmer (like clock frequency or the size
of the physical memory).
• Organization differs between different
versions.
6
The Organization of a Computer
• Processor:
All computers have had 5 main
components:
Processor
Input
Control
Memory
Datapath
Output
▫ Data path - to do arithmetic
and
logic:
e.g.
adders,
multipliers, shifters, … .
▫ Control - to give directions to
the other components: e.g. tells
the data path, memory, and IO
devices what to do according to
the instructions of the program.
• Memory:
Holds
data
and
instructions: e.g. cache, main
memory, disk, … .
• Input: Sends data to the
computer: e.g. keyboard, mouse, …
.
• Output: Gets data from the
computer: e.g. screen, sound card,
printer, … .
7
The Von Neumann Model
• The von Neumann model consists of five major components:
(1) input unit;
(2) output unit;
(3) arithmetic logic unit;
(4) memory unit;
(5) control unit.
8
The Von Neumann Architecture
Named after John von Neumann,
Princeton, he designed a
computer architecture whereby
data and instructions would be
retrieved from memory,
operated on by an ALU, and
moved back to memory (or I/O)
This architecture is the basis for
most modern computers (only
parallel processors and a few
other unique architectures use
a different model).
Hardware consists of 3 units:
• CPU (control unit, ALU, registers);
• Memory (stores programs and data);
• I/O System (including secondary storage).
Instructions in memory are executed sequentially unless
a program instruction explicitly changes the order.
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The von Neumann Model
Instruction Cycle
• This is a general
depiction of a von
Neumann system:
• These
computers
employ a fetchdecode-execute
cycle
to
run
programs as follows .
..
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The von Neumann Model: fetch
• The control unit fetches the next instruction from
memory using the program counter to determine
where the instruction is located.
11
The von Neumann Model: Decode
• The instruction is decoded into a language that the ALU
can understand.
12
The von Neumann Model: Execute
• Any data operands required to execute the instruction
are fetched from memory and placed into registers
within the CPU.
13
The von Neumann Model: Execute
• The ALU executes the instruction and places results in
registers or memory.
14
Non-Von Neumann Models
• Conventional stored-program computers
have undergone many incremental improvements
over the years.
• These improvements include adding specialized
buses, floating-point units, and cache memories,
to name only a few.
• But enormous improvements in computational
power require departure from the classic von
Neumann architecture.
• Adding processors is one approach.
15
Non-von Neumann Models
• In the late 1960s, high-performance computer systems were
equipped with dual processors to increase computational
throughput.
• In the 1970s supercomputer systems were introduced with 32
processors.
• Supercomputers with 1,000 processors were built in the 1980s.
• In 1999, IBM announced its Blue Gene system containing over 1
million processors.
16
Non-von Neumann Models
• Parallel processing is only one method of providing
increased computational power.
• DNA computers, quantum computers, and dataflow
systems. At this point, it is unclear whether any of these
systems will provide the basis for the next generation of
computers.
17
Non-von Neumann Models
Leonard Adleman is often called the inventor of
DNA computers. His article in a 1994 issue of the
journal Science outlined how to use DNA to
solve a well-known mathematical problem, called
the "traveling salesman" problem. The goal of
the problem is to find the shortest route between
a number of cities, going through each city only
once. As you add more cities to the problem, the
problem becomes more difficult. Adleman chose
to find the shortest route between seven cities.
DNA computing is still in its infancy.
Harvard Architecture
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°
Data memory is separate from Program memory.
°
Allows data and program information to move separately and so is faster than von
Neumann.
Harvard
architecture uses
separate memory
for instruction and data.
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Von Neumann and Harvard architectures
• Von Neumann
▫ Allows instructions and data to be mixed and stored in the
same memory module;
▫ More flexible and easier to implement;
▫ Suitable for most of the general purpose processors (i.e.
Pentium is using an von Neumann architecture for the
external memory and is using a Harvard architecture for its
internal cache memory (allowing 8KB of cache for data and
anther (separate) 8kB of cache for instructions).
• Harvard:
▫ Uses separate memory modules for instructions and for
data;
▫ It is easier to pipeline;
▫ Higher memory throughput;
▫ Suitable for DSP (Digital Signal Processors).
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The Basic System Components
Typical Von Neumann system
For example, the 80x86 family uses the Von Neumann architecture )VNA).
21
The System Bus Model
• A refinement of the von Neumann model, the system
bus model has a CPU (ALU and control), memory, and an
input/output unit.
• Communication among components is handled by a shared pathway
called the system bus, which is made up of the data bus, the address
bus, and the control bus. There is also a power bus, and some
architectures may also have a separate I/O bus.
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System buses
• A bus is a set of wires, that interconnects all the
components (subsystems) of a computer.
• Source component sources out data onto the bus, the
destination component inputs data from the bus.
• A system may have a hierarchy of buses.
• The I/O controller may use a second bus, often
described as I/O bus or local bus to access a variety of
attached devices.
• PCI bus is an example of a very common local bus.
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Address bus
• CPU reads/writes data from the memory by
addressing a specific location; outputs the
location of the data on the address bus; memory
uses the address to access the proper data.
• Each I/O device (such as monitor, keypad, etc.)
has a unique address as well (or a range of
addresses); when accessing a I/O device, CPU
places its address on the address bus. Each
device will detect if it is its own address and act
accordingly.
• Devices always receive data from the CPU; CPU
never reads the address bus (it is never
addressed).
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80x86 Family Address Bus Sizes
Processor
Address Bus
Size
Max Addressable
Memory
In Words
8088
20
1,048,576
One Megabyte
8086
20
1,048,576
One Megabyte
80188
20
1,048,576
One Megabyte
80186
20
1,048,576
One Megabyte
80286
24
16,777,216
Sixteen Megabytes
80386sx
24
16,777,216
Sixteen Megabytes
80386dx
32
4,294,976,296
Four Gigabytes
80486
32
4,294,976,296
Four Gigabytes
80586 / Pentium (Pro)
32
4,294,976,296
Four Gigabytes
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Data bus
• When the CPU reads data from memory, it first
outputs the address on the address bus, then the
memory outputs the data onto the data bus; the
CPU reads the data from data bus.
• When writing data onto the memory, the CPU
outputs first the address on the address bus, then
outputs the data onto the output bus; memory then
reads and stores the data at the proper location.
• The process to read/write to a I/O device is similar.
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80x86 Processor Data Bus Sizes
Processor
Data Bus Size
8088
8
80188
8
8086
16
80186
16
80286
16
80386sx
16
80386dx
32
80486
32
80586 class/ Pentium (Pro)
64
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Control bus
• Address and data buses consist of n lines, which
combine to transmit one n bit value; control bus is a
collection of individual control signals.
• These signals indicate whether the data is to be read
into or written out the CPU, whether the CPU is
accessing memory or an IO device, and whether the
I/O device or memory is ready for the data transfer.
• This bus is mostly a collection of unidirectional
signals.