Analisis Rangkaian Digital
Sistem Komputer
Universitas Narotama
1
Topik 5 – Desain Rangkaian
Kombinasional
Task:
Given a description of problem (logical statement), find the
corresponding digital circuits that produce the output (answer)
given a set of inputs (condition).
Contoh-2:
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Parking lot controller
Elevator controller
Prime number indicator
Adder, subtractor, …
Brute-force approach
Design: given a description or truth
table, find the corresponding
Boolean expression and digital
circuit.
Brute-force design methodology:
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Truth table  canonical sum
 SoP or sum of minterms
 AND-OR / NAND-NAND
Example: prime number detector
F = SN3N2N1N0(1,2,3,5,7,11,13)
Row
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
N3 N2 N1 N0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
0 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
F
0
1
1
1
0
1
0
1
0
0
0
1
0
1
0
0
Minterm list -> canonical sum
Algebraic simplification
Recall (T8) X · Y + X · Y’ = X
Simplify equation to reduce number of gates & gate
inputs
Resulting circuit
Combinational circuit
design/minimization
Objective:
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Minimizing # logic gates
Minimizing # inputs to the logic gates
Note different logic gates may have different # transistors
General idea: simplify the Boolean expression using the
theorems, especially (T10, T10’, T13, T13’)
Karnaugh-map (K-map)
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Graphical representation of the truth table
Offers visualization of (T10, T10’)
Works for functions with less than 6 variables
Real world: use programs to minimize logic circuits

E.g., VHDL, Verilog, ABEL, …
Karnaugh-map usage
Plot 1s corresponding to minterms of function.
Circle largest possible rectangular sets of 1s.

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# of 1s in set must be power of 2
OK to cross edges
Read off product terms, one per circled set.

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Variable is 1  include variable
Variable is 0  include complement of variable
Variable is both 0 and 1  variable not included
Circled sets and corresponding product terms are called
`prime implicants’
Minimum number of gates and gate inputs
3 variable example: F = S(1,2,5,7)
Rules of thumb:
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
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Group (prime implicant) as
large (many 1s) as possible
As few groups as possible
Overlaps are OK
4 variable K-map example
Note how it maps to the
rows of the truth table
Prime-number detector revisited
Compare with the previous circuit
When we solved algebraically, we missed one
simplification- the circuit below has three less gate
inputs.
Design example: alarm controller
Problem statement:
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
The ALARM output is 1 if PANIC is 1, or if ENABLE is 1 and
the house is not secure.
The house is secure if WINDOW, DOOR, GARAGE are all 1
This can be put in logic expressions as follows:
ALARM = PANIC + ENABLE · SECURE’
SECURE = WINDOW · DOOR · GARAGE
ALARM = PANIC + ENABLE · (WINDOW · DOOR · GARAGE)’
Multiply out and use (T13), we get the SoP form
ALARM = PANIC + ENABLE · WINDOW’
+ ENABLE · DOOR’+ ENABLE · GARAGE’
K-map with don’t-cares
In some cases, the output of a combinational circuit
doesn’t matter for certain input combinations.
Such combinations are called don’t-cares and the output
is represented in the truth table and K-maps as `d’.
When using K-maps to minimize such functions:
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Allow d’s to be included when grouping sets of 1’s to make the
sets as large as possible.
Do not circle any set that only contains d’s.
Example with don’t-cares

Prime number detection for BCD numbers (takes value between 0-9) –
minterms 10-15 are treated as don’t-cares:
F(N3,N2,N1,N0) = S N3,N2,N1,N0 (1,2,3,5,7) + d(10,11,12,13,14,15)
From K-map:
N3’· N0
N3 N2
Prime Implicants:
N3’· N0
N2’· N1
00
N1 N0
N2 · N0
N3
0
01
11
12
4
00
10
N2 · N0
8
d
Distinguished 1-cells:
Cell 1 covered by N3’· N0
Cell 2 covered by N2’· N1
Here not all prime implicants are
essential prime implicants that
must be included minimum
SOP expression:
F = N3’ · N0 + N2’ · N1
01
1
13
5
1
d
1
9
N0
11
N1
3
2
10
15
7
1
1
1
6
11
d
14
10
d
N2
d
d
N2’· N1
5-variable K-maps
The K-map for a 5-variable logic function is organized
as two 4-variable K-maps:

Can be visualised as being one 4-variable map on top of
another 4-variable map
W
W
WX
WX
YZ
00
00
01
11
0
4
12
1
5
13
Y
00
9
15
7
11
11
2
00
8
01
3
YZ
10
14
6
10
10
01
11
16
20
28
24
17
21
29
25
19
23
31
27
18
22
30
26
01
Z
Y
11
10
X
V=0
10
X
V=1
Z
5-variable K-map example
F(V,W,X,Y,Z)
= S V,W,X,Y,Z(4,5,6,7,9,11,13,15,25,27,29,31)
W
W
WX
WX
YZ
00
00
01
0
4
1
5
01
3
Y
7
11
2
10
6
11
12
1
YZ
10
00
8
00
13
1
1
15
1
14
1
1
9
1
11
10
01
11
16
20
28
24
17
21
29
25
19
23
31
27
18
22
30
1
01
Z
1
Y
11
1
10
X
V=0
10
X
V=1
1
26
Z
1
5-variable K-map example – cont.
W
W
WX
WX
YZ
00
00
01
0
4
1
5
01
3
Y
7
11
2
10
6
11
12
1
YZ
10
8
00
13
1
1
15
1
14
1
1
9
1
11
1
Y
10
01
11
20
28
24
17
21
29
25
19
23
31
27
18
22
30
1
11
1
10
V=0
X
W·Z
10
16
01
Z
X
V’ · W’· X
00
V=1
Minimum SOP: F = V’ · W’· X + W · Z
1
26
Z
1
K-map product-of-sum minimization
Using K-map, find a minimal PoS expression for
F(X,Y,Z) = P X,Y,Z (0,3,4,7)
Truth Table
Row
0
1
2
3
4
5
6
7
X
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
X
F
0
1
1
0
0
1
1
0
XY
00
Z
0
11
6
2
10
4
0
0
0
1
01
1
3
0
7
Y
0
5
Z
K-map PoS minimization – cont.
(Y + Z)
X
XY
00
Z
0
0
Truth Table
F
0
1
1
0
0
1
1
0
1
11
6
2
10
4
0
0
1
Row X Y Z
0
0 0 0
1
0 0 1
2
0 1 0
3
0 1 1
4
1 0 0
5
1 0 1
6
1 1 0
7
1 1 1
01
3
5
7
0
0
Z
Y
(Y’ + Z’)
Minimum PoS: F = (Y + Z) · (Y’ + Z’)
K-map PoS minimization – another
example
Using K-map, find a minimal POS expression for
F(W,X,Y,Z) = P W,X,Y,Z (1,3,8,10,12,13,14,15)
W
WX
00
YZ
0
01
11
12
4
00
01
10
8
0
0
1
13
5
0
9
0
Z
11
Y
15
7
3
0
0
2
11
14
6
10
10
0
X
0
K-map PoS minimization – another
example
W
WX
00
YZ
0
01
11
12
4
00
01
(W + X + Z’)
11
Y
10
0
0
1
13
5
0
0
6
14
10
(W’ + X’)
11
0
0
2
9
Z
15
7
3
(W’ + Z)
8
10
0
0
X
Minimum POS: F = (W + X + Z’) · (W’ + Z) · (W’ + X’)
Combinational Circuit:
Transient vs. Steady-state Output
Timing Diagram
X
X
X’
1  0
X’
propagation delay
1
Time
0
1
0
Transient
output
Steady-state output
Transient output: the temporary output due to the gate propagation
delay(s)

Gate propagation delay: the time it takes to pull up (or down) the
output signals due to the change at the input – depends on the
transistor level implementation.
Hazards in combinational circuits
Output glitch: a momentary (transient) fluctuation in output signal
due to changes in input signal.
1
0
1
1
0
Static-0 Hazard
0
Static-1 Hazard
1
0
1
0
Dynamic Hazard Example
Static hazards:
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
Static-0 hazard: The output should be 0 but goes momentary to 1 as a
result of an input change – possible in AND-OR circuits
Static-1 hazard: The output should be 1 but goes momentary to 0 as a
result of an input change – possible in OR-AND circuits
Dynamic hazards: The output changes more than once as a result
of a single input change (impossible in 2-level circuits).
Example: static-1 hazard
A static-1 hazard exists in the following AND-OR circuit when X=1, Y=1
and Z changes from 1 to 0 (assume all gates have propagation delay D)
Extra propagation delay
between Z and Z’
Circuit
X
1
X · Z’
Z’
Z
1  0  1
0  1
1  0
Timing Diagram
Z
1
0
Z’
1
0
F
1  0
Y
1
K-map
Y·Z
Y·Z
1
0
X·Z’
1
0
X
XY
Z
00
01
11
0
2
6
1
3
7
0
1
1
Y
1
10
4
1
5
X · Z’
Z
1
Y·Z
F
1
0
D
D
D
Steady-state
output
Time
Eliminate static-1 hazard using K-map
Static-1 hazards are found using k-maps by finding adjacent 1 cells
that are covered by different product terms.
To eliminate static-1 hazards, additional product terms (prime
implicants) are needed to cover such cells thus covering the transition
of the variable causing the hazard.
For the previous example the static-1 hazard is eliminated by
including the additional product term X · Y
New F = X · Z’ + Y · Z + X · Y
X
X
X·Y
Z
00
0
01
11
6
2
0
1
1
Y·Z
3
7
1
Y
1
10
4
1
5
X·Z’
Z
Z’
X · Z’
X·Y
Z
1
X·Y
Y
Y·Z
F
Eliminate static-0 hazard using K-map
A static-0 hazard occurs in OR-AND circuits when an input
variable and its complement are connected to two different OR
gates.
The procedure to find and eliminate static-0 hazards using Kmaps is done in a dual way to finding static-1 hazards.
Static-0 hazards are found using k-maps by finding adjacent 0
cells that are covered by different sum terms.
To eliminate static-0 hazards, additional sum terms (prime
implicates) are needed to cover such cells thus covering the
transition of the variable causing the hazard.
Homework #2
Turn in: (show your steps)
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4.13 (f), 4.14 (f)
4.19 (e), 4.20 (e), 4.21 (e)
4.22 (d)
4.45
4.47 (refer to 4.46 for hints)
4.55 (a) (b) (c)
4.65
4.72 (f), 4.73 (f)
Self exercise: (you do not need to turn in these, but
think about them!!)
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4.48, 4.50, 4.52, 4.68, 4.71, 4.84, 4.85