Processor Design
Specifying the Actions
Internal Architecture of a Simple Processor
ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides6.ppt
Modification date: Oct 30, 2014
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Internal Architecture of a Simple Processor
(Not representative of modern computer, later on that)
Main memory
Control
signals
Data
Address
Program Counter
more accurately
called the Instruction
Pointer, IP.
System
bus
Internal bus
R0
IR
Processor
(representative)
ALU
Control
Unit
Control
signals
Registers
PC
Program counter
holding address
of next instruction
R31
Holds machine instruction
to be/being executed
Arithmetic and logic unit
for performing arithmetic
and logical operations
Main registers
holding operands
say R0 to R31
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MDR and MAR registers
Added to hold data or from memory and address to select memory
location:
Main memory
Control
signals
Data
Address
System
bus
MDR
Internal bus
MAR
IR
PC
ALU
Control
Unit
Control
signals
Registers
MAR
Memory
address
register
MDR
Memory
data
register
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Internal Operation
Operation of processor divided into two phases:
• Fetch cycle
Next instruction is fetched from memory
• Execute cycle
Fetched instruction is executed
Fetch cycle
Execute cycle
These cycles are repeated as each instruction is executed.
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Fetch Cycle
Select instruction:
Main memory
Control
signals
Data
Address
Select next
instruction
System
bus
MDR
Internal bus
MAR
IR
PC
ALU
Control
Unit
Control
signals
Registers
Processor
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Fetch instruction:
Main memory
Control
signals
Data
Address
Instruction
System
bus
MDR
Internal bus
MAR
IR
PC
ALU
Control
Unit
Control
signals
Registers
Processor
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Register Transfer Notation
Mostly, actions within processor can be described by the transfer of
the contents of one location to another location (registers or units).
Use a register transfer language (RTL) notation.
Example
To transfer the contents of register MDR to register IR, we write:
IR  MDR
IR
MDR
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May add time of action:
T2: IR  MDR
The transfer is to take place at time period T2.
IR
MDR
This occurs at time period T2
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Fetch Cycle
Fetch cycle actually breaks down into several steps:
T0: MAR  PC
Select next instruction
T1: MDR  [MAR] Memory read operation, get instr. from memory
T2: IR  MDR
Load instruction into instruction register
T3: PC  PC + 4
Increment program counter in preparation
for next fetch cycle
Could be done simultaneously
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Fetch Cycle
Fetch cycle with last two steps done simultaneously:
T0: MAR  PC
Select next instruction
T1: MDR  [MAR]
Mem. read op., get instr. from mem.
T2: IR  MDR; PC  PC + 4 Load instruction into instr. register
Increment prog. counter in prep.
for next fetch cycle
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Execute Cycle
Breaks down into several steps depending upon instruction fetched.
In our design, execution cycle steps start at T3.
To be able to specify certain steps, need to know machine instruction
format.
We will give representative formats, which will be used in
subsequent designs later.
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Source and destination registers
We will use the notation:
Rs1
Rs2
Rd
for the first source register
for the second source register
for the destination register
for register-register instructions as specified in the instruction.
Some instructions may only have one source register and/or no
destination register.
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Temporary registers
In some designs, it may be necessary to introduce temporary registers
to hold Rs1, Rs2, Rd, say called A, B, and C. Then:
A  Rs1
B  Rs2
Contents of first source register copied to A
Contents of second source register copied to B
will occur automatically whether or not they required by the
instruction. If not required, A and B are not accessed subsequently.
Similarly if C is loaded, the operation:
Rd  C
Copy C to destination register
occurs automatically.
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Execute Cycle for Add Instruction
Register-register addressing
Example:
ADD Rd, Rs1, Rs2
T3: Rd  Rs1 + Rs2
Perform addition and pass result back to Rd
Machine instruction format:
ADD
31
26 25
Rd
Rs1
21 20
Rs2
16 15
Not used
11 10
0
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Execute Cycle for Add Instruction
Immediate Addressing
ADDI Rd, Rs1, 123
T3: Rd  Rs1 + IR15-0 Perform addition and pass result back to Rd
IR15-0 means here bits 15 to 0 of IR register
Assumes bits 15 to 0 in IR holds the constant (123 above)
Machine instruction format:
ADDI
31
26 25
Rd
Rs1
21 20
Constant
16 15
0
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Other Arithmetic/Logic Instructions
Other arithmetic and logic instructions have similar sequences of
steps. Simply replace the add operation in:
T3: Rd  Rs1 + Rs2
Perform addition and pass result back to Rd
or
T3: Rd  Rs1 + IR15-0 Perform addition and pass result back to Rd
with the appropriate arithmetic or logic operation.
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Execute Cycle for Memory Reference Instructions
Load Instruction
LD Rd, 100[Rs1]
where 100 is a constant in the instruction (IR15-0)
T3: MAR  Rs1 + IR15-0 Compute memory address
T4: MDR  [MAR]
Memory read operation
T5: Rd  MDR
Get memory contents, load into Rd
Machine instruction format:
LD
ADDI
31
26 25
Rd
Rs1
21 20
Constant
16 15
0
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Store Instruction
ST 100[Rs1], Rs2
where 100 is a constant in the instruction (IR15-0)
T3: MAR  Rs1 + IR15-0 Compute memory address
T4: MDR  Rs2
Get contents of register
T5: [MAR]  MDR
Memory write operation
Machine instruction format:
ST
31
Rs2
26 25
Rs1
21 20
Constant
16 15
0
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Branch Instructions
Bcond Rs1, L1
where cond specifies the condition, E, NE, L, G, GE, or LE.
T3: Rs1 - 0
Compare Rs1 with zero
T4: if (condition TRUE)
PC  PC + IR15-0
Load PC with target address
Machine instruction format:
Bcond Not used
31
Rs1
Offset
16 15
0
Offset stored in instruction may need to be offset – 4 since PC already incremented
by 4 by this time. Also need to take into account the offset is a word offset - not
shown here.
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Jump Instruction
PC-Relative Addressing
J L1
T3: PC  PC + IR25-0 Load PC with target address
Machine instruction format:
J
31
Offset
26 25
0
Again offset stored in instruction may need to be offset - 4
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Jump Instruction
Register-Indirect Addressing
J 100[Rs1]
where the offset (100 above) is held in IR15-0
T3: PC  Rs1 + IR15-0 Compute effective address and load PC
with final target address
Machine instruction format:
J
31
Not used
26 25
21 20
Rs1
Offset
16 15
0
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Jump and Link Instruction
JAL L1
T3: R31  PC
Store return address in R31
T4: PC  PC + IR25-0 Goto L1
Machine instruction format:
JAL
31
Offset
26 25
0
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CALL/RET Instructions
Even though our design does not have CALL and RET instructions, let us
just list the steps for these instructions:
T3:
T4:
T5:
T6:
T7:
SP  SP – 4
MAR  SP
MDR  PC
[MAR]  MDR
PC  IR25-0
CALL proc1
Decrement stack pointer (by 4 if 32-bit addresses)
PC holds return address
Copy PC onto stack (return address)
Goto to procedure (address of proc1 held in IR25-0)
RET
T3:
T4:
T5:
T6:
MAR  SP
MDR  [MAR] Get return address from stack
PC  MDR
Return
SP  SP + 4 Increment stack pointer (by 4 if 32-bit addresses)
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State Diagram for Processor
After previous
instruction
executed or
processor reset
Fetch cycle
0
MAR  PC
1
MDR  [MAR]
2
Instruction decode
(assumed not needing a state)
IR  MDR
PC  PC + 4
Memory read
Assuming separate
logic to increment
PC (not using ALU)
......
Execute
cycles
Register-register Register-constant Memory
(Several)
(Several)
reference
(load/store)
Branch
(Several)
Jump
States numbered 0, 1 ...
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Register-Register Instructions
The arithmetic and logic instructions operating upon pairs of
registers - Could be many such instructions.
For simplicity, let us assume the following six operations:
ADD
SUB
MULT
DIV
AND
OR
Addition
Subtract
Multiply
Divide
Logical AND
Logical OR
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State diagram for register-register instructions
All very similar form:
ADD
3
SUB
AND
4
RdRs1 + Rs2
7
RdRs1 - Rs2
RdRs1AND Rs2
OR
8
RdRs1 OR Rs2
Return to fetch cycle
For simplicity of drawing state diagram:
Register-register
3-8
RdRs1<op>Rs2
MUL/DIV almost certain to require more that one cycle but this is ignored here.
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Register-Constant Instructions
The arithmetic and logic instructions operating upon one register and
an immediate constant For simplicity, let us assume the following six
operations:
ADDI
SUBI
ANDI
ORI
SHL
SLR
Addition
Subtract
Logical AND
Logical OR
Logical shift left (number of places given by constant)
Logical shift right (number of places given by constant)
The “I” is used here to indicate immediate addressing.
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State diagram for register-constant instructions
All very similar form:
13
10
9
RdRs1 + IR 15-0
SHR
SHL
SUBI
ADDI
RdRs1<< IR15-0
RdRs1 - IR 15-0
14
RdRs1 >> IR 15-0
Return to fetch cycle
For simplicity of drawing state diagram:
Register-constant
9 - 14
RdRs1<op> IR15-0
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State Diagram with Load and Store instructions
Register-register
3-8
RdRs1<op>Rs2
Register-constant
9-14
RdRs1<op>IR 15-0
Load
15
Store
18
MARRs1+IR 15-0
16
MARRs1+IR 15-0
19
MDR  Rs2
MDR[MAR]
17
20
Rd  MDR
[MAR] MDR
Return to fetch cycle
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Conditional Branch Instructions
Let us assume the conditional branch instruction of the format:
Bcond, Rs1, L1
(not using a CCR) and the following four operations:
BL
BG
BE
BNE
Branch if Rs1 less than zero
Branch if Rs1 greater than zero
Branch if Rs1 equal zero
Branch if Rs1 not equal zero
Question – is that sufficient?
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Execute Cycle for Branch Instruction
In this case we need to select on of two sets of actions:
• If branch condition true = do actions (alter PC)
• If branch condition false, generally do nothing.
Rs1 - 0;
Yes
Condition
True
No
PCPC+IR 15-0
Fetch instruction Fetch sequential
from target address instruction
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State Diagram of Branch Instructions
All of similar format:
BL
BG
21
BE
23
Rs1  0
25
Rs1  0
if Rs1 < 0
PCPC+IR 15-0
22
BNE
27
Rs1  0
if Rs1 > 0
PCPC+IR 15-0
24
Rs1  0
if Rs1  0
if Rs1 = 0
PCPC+IR 15-0
26
PCPC+IR 15-0
28
Return to fetch cycle
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State Diagram of Jump Instructions
Jump - PC relative
29
Jump - Reg. indirect
30
PCPC+IR25-0
JAL
31
PCRs1+ IR 15-0
R31  PC
32
PCPC+IR25-0
Return to fetch cycle
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Could combine states 22, 24, 26, and 28 into one state, and combine
states 29 and 32 into one state.
However in our design will only combine 29 and 32 to get 32 states in
total (0 to 31):
Jump - PC relative
JAL
31
Jump - Reg. indirect
30
R31  PC
PCRs1+ IR 15-0
29
PCPC+IR25-0
Return to fetch cycle
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Questions
Next step is to implement state diagrams.
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