Mustafa Khairallah
Boost Valley
Boost Valley Consulting
Universal Verification
Methodology (UVM) Benefits
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



Verification Needs
UVM Benefits
Example: I2S
Conclusion
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Outline
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Code Reuse
Test Cases &
Scenarios
Modification
Functional
Coverage
Calculation
Generating &
Managing
Reports
Debugging
Communication
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Verification Needs
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Code Reuse
Test Cases &
Scenarios
Modification
Functional
Coverage
Calculation
Generating &
Managing
Reports
Debugging
Communication
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Verification Needs - Development
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Code Reuse
Test Cases &
Scenarios
Modification
Functional
Coverage
Calculation
Generating &
Managing
Reports
Debugging
Communication
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Verification Needs - Compilation
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Code Reuse
Test Cases &
Scenarios
Modification
Functional
Coverage
Calculation
Generating &
Managing
Reports
Debugging
Communication
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Verification Needs - Runtime
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Code Reuse
Test Cases &
Scenarios
Modification
Functional
Coverage
Calculation
Generating &
Managing
Reports
Debugging
Communication
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Verification Needs - Debugging
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Verification Methodologies
 Do the same things the same way:
 Test/Test-bench separation:
 Compile once, run many times.
 Utilities:
 Functional coverage – reporting
mechanisms - … etc.
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 Ease of communication.
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UVM Benefits
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UVM Adoption
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Test/Test-bench separation
Test
• Test Writer:
Analysis
Agent
Test
Register Model
Configurations
Passive
Agent
Environment
Env
(Testbench)
• Selects sequences,
• Configures the
environment(s)
• Runs test.
• UVC User: Integrates
UVCs into environment
to test different
designs.
Active
Agent
Bus
Agent
DUT
UVCs
• Developer: UVC
Design
• Complication phase.
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Environment
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Test/Test-bench separation
Environment
Analysis
Agent
Register Model
Configurations
Passive
Agent
Active
Agent
Bus
Agent
Environment
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Test
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Configurability
 Configurations can be:
 Structural configurations.
 Runtime configurations.
 Provides topological flexibility:
 Components can be overridden, removed or
configured.
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 Controlled by the test writer.
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 UVM is compatible with the TLM 2.0 standard.
 Uses port/export communication.
 Hides communication details (pin level activities)
 Eases customization using configurations & overrides.
Block 1
Block
Block 2’
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TLM 2.0
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Constrained Randomization
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Coverage Collector
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Checker (Reference Model)
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Checker (Assertions)
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Built-in reporting mechanisms.
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Built-in reporting mechanisms.
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Practical Example :I S
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Introduction
 I2S Bus Purpose:
 Communicate PCM audio data between integrated circuits.
 Characteristics
 Separates clock and serial data signals.
 Lower Jitter.
 Can recover clock from data stream.
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 I2S stands for Inter-IC Sound,
 DUT is a slave I2S transceiver.
 It is around 2000 gates.
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UVM Test-Bench Architecture
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Runtime Comparison
> 10 Times
Reduction!!
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Time in
minutes
VHDL
UVM
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VHDL Test-Bench
UVM Test-Bench
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No. of test cases
0
2
20
200
2000
20000
200000
2000000
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Conventional Test-bench
UVM Test-Bench
• Mainly simulation-based
• Limited assertion-based
capabilities
• Simulation based
• Advanced assertion-based
in System Verilog & UVM
Mostly directed testing
Constrained random testing
& directed testing
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Summary
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Conventional Test-bench
UVM Test-Bench
Can’t automatically guarantee full
functional coverage
Supports functional coverage
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Summary
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Conventional Test-bench
UVM Test-Bench
Strongly coupled with DUT
Loosely coupled with DUT
Requires longer
development time
Reusability reduces
development time
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Summary
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Questions?
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Thank You
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