TRI-ADS:
Targeted Remote Information and Advertisement
Distribution System
Wade Pentz
Blake Orth
Grant Fritz
Andrew Gunn
Brian Weinstein
System Overview
 Network of targeted advertisement display modules
 Change display based on location, time of day, weather,
emergency status, etc
 Provide standard DVI output
 Modules communicate wirelessly with a base station
 Powered from 12V DC wall adapter or car outlet
Wade Pentz
System Overview
Wade Pentz
Primary
Secondary
Tertiary
• GPS data processing
• LCD display
• GPS based image change
•WiFi communication
• Base station
•Universal power board
•Second module
• Analog sensors
• Bluetooth
• Base station GUI
• Packaging
• Animation
Level 0 Functional Decomposition
Wade Pentz
Level 1Hardware Functional Decomposition
Wade Pentz
Command and Data Handling System
Overview
 Coordinate DVI output with CPLD and load image off of




SD card
Store GPS location and coordinate ad changes
Manage Wifi/3G link and remote update
Manage Bluetooth communications between display
modules
Gather temperature/accelerometer data and coordinate ad
changes
Grant Fritz
CDH Functional Decomposition
Grant Fritz
Command and Data Handling System
Hardware
 Using NGW-100 as main board
 AT32AP7000 microprocessor
 2.6 Linux Kernel
 Resource Management
 Modular process software design
 Utilize standard libraries
Grant Fritz
Software Functional Diagram
Grant Fritz
CDH Software Functional
Decomposition
Level 0
Module
Inputs
Outputs
Functionality
Test Procedure
Grant Fritz
RunBabyRun (Level 0)
- Raw GPS data
- Inter-module Bluetooth data
- Configuration data
- Monitor display data
- Inter-module Bluetooth data
- Status data
This process is the primary control and data processor for the TRI-AD system. It
takes in raw GPS data through serial, processes it to understand its current location.
Receives raw analog sensor data through the I2C bus. Receives update information
and status requests through Inter-Process Communication. Negotiates display
information with the CPLD through the SPI bus and coordinates with the DVI Chip
through the I2C bus. Finally this module also does the primary logic of the system
where which image is selected to be displayed.
Level 1 Software Decomposition
Grant Fritz
CDH SFT Functional Decomposition
Level 1
Logic
Module
Inputs
Outputs
Functionality
CParse
Logic (Level 1)
- GPS Coordinates
- Temperature
- Time
- Configuration Data Matrix
- Image name to Display
This takes in GPS coordinates, temperature, and time and determines which image
from the configuration data to display.
Test Procedure
GPS (Level 1)
- Raw Serial GPS Data
- GPS Coordinates
Takes in raw serial data, parses the serial char string and writes the data to
variables.
Test Procedure
Functionality
Test Procedure
Module
Inputs
Outputs
Functionality
Inter-Process Communication Receive (Level 1)
- IPC Messages
- Control
Takes in IPC Messages from a message queue and processes the message with the
given command. The commands will consist of PING, SETIMAGE, CLEARIMAGE,
HEALTH&STATUS, UPDATECONFIG, and SLEEP.
Test Procedure
Analog Sensors
Display
Module
Inputs
Outputs
CParse (Level 1)
- Configuration File name
- Configuration Data Matrix
Takes in the configuration file address and then parses the data into a data matrix
for easy reference.
Inter-Process Communication Receive
GPS
Module
Inputs
Outputs
Functionality
Module
Inputs
Outputs
Functionality
Display (Level 1)
- Image filename
- I2C commands to DVI Chip
- SPI commands and image data to CPLD
Takes in an image filename and converts it to a matrix of RGB triplets before
transmitting the data over SPI to the CPLD.
Test Procedure
Grant Fritz
Module
Inputs
Outputs
Functionality
Test Procedure
Analog Sensors (Level 1)
- Raw I2C Analog Sensor Data
- Processed Sensor Data
Takes in raw I2C data and processes the data to a nice output.
Display System Overview
 Use DVI for easy interface to screens of various sizes
 DVI prioritized over VGA to allow for future expandability
 Custom display hardware will allow for a simple embedded
solution
 Removes the need to interface and power a full rendering graphics
card
 Current image stored to on-board SRAM for fast access
 Will be implemented using TFP410 DVI Trasmitter, Altera MaxII
CPLD and 6MB SRAM
Blake Orth
Display Functional Decomposition
Blake Orth
CPLD
 Programmed using Verilog through JTAG
 Clocked at 165MHz
 Takes care of all Video memory Operations
 Reads pixel data from SRAM chips and presents it at 24-bit DVI
chip input
 Write new image data to SRAM chips
 Receives new image data from the microcontroller via SPI
 Manage all SRAM and DVI control lines
Blake Orth
EPM570T144C5N
 Max II – 570 Series 144-TQFP
 Selected for fast pin-to-pin propagation delay ( down to 4.5ns)
 440 macro-cells allows for reasonably complex logic
 Good performance for current draw – at most draws 250mA
 Development board being used to develop Verilog code
Blake Orth
Display System Hardware
 Use TI TFP410 PanelBus DVI Transmitter
Blake Orth
TI TFP410 DVI Transmitter
 Basic configuration through I2C
 Allows settings for resolution, DE generator, and data de-skew
 Takes 24-bit True Color pixel data and control signals
 Encodes and serializes pixel data to PanelBus DVI and
outputs to a standard Single Link DVI Connector
Blake Orth
SRAM
 Stores current image data (1 image)
 24-bit True Color for each pixel
 8-bits for each color part (RGB)
 Three SRAM units will be used
 RGB pixel data stored in parallel
 One unit for each color
 Shared 20-bit address bus
 All parts of a single pixel will have a shared address
 Shared 8-bit data bus
 Bus control handled with output/write enable pins
Blake Orth
SRAM Selection
 ISSI IS61WV102416
 1M x 16b SRAM
 8 ns access time
 Using 3 modules totals to 6MB of storage
Blake Orth
SRAM Modes
 SRAM has ability for 16-bit data bus
 We are using in 8-bit data bus mode
 20-bit address selects a 16-bit word
 Uses /LB and /UB pins to select upper or lower byte
Blake Orth
Read Cycle Timing Diagram
Notes: - Upper/Lower byte selection control pins not shown here
- /CE will be tied active
Blake Orth
Brian
COM Functional Decomposition
Andrew Gunn
GPS
 Primary Objective
 GPS location used to provide optimal advertisement

RS232 Interface

GPS Handler script


Input a character string
Outputs global variables taken from the char string
Andrew Gunn
GPS Handler
$GPGGA,184149.00,4000.43877,N,10515.72492,W,1,05,1.68,01633,M,-020,M,,*5C
 Type = GPGGA
 Time = 18hr 41min 49secs Zulu Time
 4000.43877 North Latitude
 10515.72492 West Longitude
 GPS Quality 0=No GPS, 1=GPS, 2=DGPS
 Number of Satellites 5
 Altitude in Meters 01633
Andrew Gunn
GPS
 Status Update
 Full Circle & Fully Functional
GPS Module Receives Data From Satellites
Microprocessor Receives Data String
GPS Handler Parses & Saves Information
 Where From Here
 Implement Position Logic
 If in this Location -> Display This Ad
Andrew Gunn
Wifi
 Used to update the Display Module with new advertisements &
information
 Initial Wifly utilizes telnet exclusively
 Telnet is completely unsecure
 Telnet is Great for sending small strings across local network but not so
great at sending large files over internet.
 Breakdown, Encrypt, Pack, Transmit, Decrypt, Unpack
 In addition to writing the serial and wifi drivers
Andrew Gunn
Wiport Wifi Module
 Interface RS 232 to UART or Ethernet
 Wiport - Breakdown, Encrypt, Pack, Transmit, Decrypt,
Unpack
 Serial and Wifi Drivers
 Wifi Software
 Input a character string to change networks
 Outputs information or files through Ethernet
Andrew Gunn
Bluetooth
 Tertiary objective
 RS232 thus we can reuse serial driver from GPS
 Milestone 2 objective
 Overall COM Board
 Connects module headers to board stacks
 Board Designed in Altium in progress
Andrew Gunn
Power Functional Decomposition
Wade Pentz
Power System
 Each board has its own power stage
 Allows each board to be tested separately
 Uses linear regulator to provide needed voltage rails
 All IC’s use 3.3V
 If time allows, a power board will be created
 Route IC power
 Provide DVI display power using boost converter
Wade Pentz
Power Stage
 Power switch for each board
 Bridge rectifier IC (DF10S)
 1.5 Amp average current rating
 1.1 Volt forward drop
 LM317 adjustable linear regulator
 1.5 Amp average current rating
 Uses voltage divider to set output voltage
 Extremely accurate regulation
 Additional protection diodes
Wade Pentz
Power Stage
Wade Pentz
LM317 Linear Regulator Circuit
For 3.3V:
R1 = 220 Ohms
R2 = 330 Ohms
Brian
Hi Res. Display
Base Station
 Current Status
Outbox
Ad Uploaded
Base Station
Image_handler
 Image_Handler
 Converts input to JPG
 Multiple Copies based on Resolution
 Places in Outbox
 Auto SSH with RSA
 Pushing configurations & images to display units
 Where we want to go
 Optimize and increase functionality
 GUI if time allows
Andrew Gunn
Low Res. Display
Milestone 1
• Serial Driver
• I2C Driver
• GPS Driver
•Wifi Driver
• Skeleton framework
• Board populated
• CPLD programmable
• Initial CPLD code written
•Write to and read from SRAM
•Wifi working
•GPS working
• Board populated
• Individual board power functional
System
CDH
Milestone 2
• CPLD SPI interface
• JPEG conversion and display
•Wireless image download
Display
• Interface with DVI chip
• Update image based on location
Comm
COM
• Bluetooth working
• Receive image updates through wifi
• Send updates to basestation
Power
• Power board (tentative)
Expo
 Complete system working
 Display images through DVI
 Change images based on location
 All devices talking with CDH
 Full communication with base station over wireless
 Bluetooth communication functional
 Power board if necessary and time allows
 Second module if time allows
 User’s manual
Brian Weinstein
Division of Labor
Task
Wade
CDH Software
EPS Board
DVI Board Layout
CPLD Software
Documentation
Brian Weinstein
Blake
Secondary
Primary
Secondary
Secondary
Secondary
Secondary
Primary
Primary
Secondary
Secondary
Brian
Secondary
Secondary
Secondary
Primary
Primary
Secondary
Secondary
Primary
Secondary
Secondary
Primary
Secondary
Secondary
Secondary
Primary
Primary
Secondary
Secondary
Secondary
COM Firmware (Wifi, GPS, Bluetooth)
Base Station Programming
Grant
Primary
COM Board
COM Software ( DHCP, SSH, etc)
Andrew
Schedule
Brian Weinstein
Schedule Highlights
 CPLD Code Development Begins
 Goal: Monday February 28th
 Order Display and Com Boards
 Goal: March 1st
 Schedule Multitasking and Dependencies
 Integration of Hardware and Software
Brian Weinstein
Budget
Brian Weinstein
Item
Cost
NGW100 Dev Board
$120
Board Fabrication
$120
DVI Chip (TFP410)
$7.50
GPS with Breakout Board
$116.90
Bluetooth
$74.95
Wiport
$123
SRAM x 3
$75
CPLD
$6
Miscellaneous Components
$100
Printing Expenses
$100
Sub-Total
$738.35
UROP Funding
$-960
Sparkfun Donation
$-150
Total
$-371.65
Risk Management
 (303) 55-RILEY
Risk
Brian Weinstein
Questions?
Thank you!