Xilinx CPLDs Low Cost Solutions At All Voltages CPLD Product Portfolio Complete Solutions for all Markets 0.50u 0.35u XC9500 5.0V 5.0 ns tPD 288 mcells Lowest Cost 3.3V XC9500XL 3.3V 5.0 ns tPD 288 mcells XPLA3 3.3V 5.0 ns tPD 512 mcells Low Power 0.25u 0.18u XC9500XV 2.5V 5.0 ns tPD 288 mcells Lowest Cost 1.8V CoolRunner-II 1.8V 3.0 ns tPD 512 mcells Lowest Power Xilinx CPLD Feature Comparison Feature CoolRunner-II CoolRunner XPLA3 9500XL / XV Core Voltage Low Power 1.8 RealDigital+ DataGATE 3.3 3.3 / 2.5 Low power mode Global Clock 3 P-Term Inputs 40 Divide, DualEDGE & CoolCLOCK LVTTL, LVCMOS, HSTL, SSTL Clock Management I/O Standards RealDigital 4 3 40 54 None None LVTTL, LVCMOS LVTTL, LVCMOS I/O Banks 1 to 4 1 1 to 4 (XV) , 1 (XL) Macrocells 32-512 32-512 36-288 TPD / FMAX 3.5 / 333 5 / 200 4.0 / 250 Security Multiple levels 1 level 1 level Process Technology 0.18u 0.35u 0.35u / 0.25u The RealDigital CPLD A New Class of CPLD: High Performance & Ultra Low Power The RealDigital CPLD Advantage RealDigital Features 0.18 design with 100% digital core Advanced I/O’s Superior clock management Enhanced security Advanced packaging Easy prototyping Single world class software environment Benefits High performance up to 385MHz (32mc) Ultra low power of 20uA typical standby, 12mA dynamic (128mc) with no price premium Scalable for faster technology migration to lower voltage & power 500mV input hysteresis for improved noise immunity LVTTL, LVCMOS, SSTL, HSTL standards (1.5v to 3.3v capable) DataGATE for lower power consumption DualEDGE for increased performance 500MHz toggle rate Clock divide & CoolCLOCK for reduced power consumption Multiple levels of security for ultimate design protection Smallest footprint chip scale High performance BGA with higher I/O per macrocell density CoolRunner-II design kit to verify design on known hardware One software system for all Xilinx products Free web download or CD - WebPACK Design fit optimizing - WebFITTER Power estimator - XPower CoolRunner-II Family Overview Features XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512 Macrocells 32 64 128 256 384 512 FToggle (MHz) 500 454 416 416 416 416 FSYSTEM (MHz) 385 270 263 238 217 217 Max I/O 33 64 100 184 240 270 I/O Banks 1 1 2 2 4 4 LVCMOS, LVTTL 1.5, 1.8, 2.5, 3.3 Yes Yes Yes Yes Yes Yes HSTL, SSTL No No Yes Yes Yes Yes DualEDGE Yes Yes Yes Yes Yes Yes DataGATE, CoolCLOCK No No Yes Yes Yes Yes Standby Power (uW) 28.8 30.6 34.2 37.8 41.4 45.0 Multiple Levels of Security Yes Yes Yes Yes Yes Yes Packages (size, type) VQ44 (10 x 10mm, leaded) PC44 (16.5 x 16.5mm, leaded) CP56 (6 x 6mm, chip scale) VQ100 (14 x 14mm, leaded) CP132 (8 x 8mm, chip scale) TQ144 (20 x 20mm, leaded) PQ208 (28 x 28mm, leaded) FT256 (17 x 17mm, BGA) FG324 (23 x 23mm, BGA) Maxium User I/O 33 33 33 33 33 45 64 80 100 100 80 106 118 173 184 118 173 212 240 173 212 270 CoolRunner-II Flexibility XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512 I/O Banks 1 1 2 2 4 4 LVTTL33, LVCMOS 33, 25, 18, 15* SSTL3-1(3.3v), SSTL2-1 (2.5v), HSTL1 (1.5v) Input hysteresis control Slew rate control CoolCLOCK DataGATE DualEDGE Clock divider Bus hold output Hot pluggable Programmable Grounds Note: 1.5v inputs need hysteresis Design Kit • • A complete design kit for: • Logic designers new to CPLDs • CPLD designers new to Xilinx • ASIC designers Simple, inexpensive demo board • Battery or AC outlet power source • Parallel printer cable for programming • LED's for simple testing • Dual in line I/O header for easy connections • Jumpers for easy modifications • Multiple device selection on a single board (CoolRunner-II or XC9500XL) Quick Start Training • • • • All materials now released! Full day of training at recent FAE conference World-wide roll out complete Set up your customer training now Quick Start Modules Get up to speed on CoolRunner-II features and new applications Module 1: CoolRunner-II Technology & Architecture Module 10: Compact Flash for CoolRunner-II CPLDs Module 2: CoolRunner-II Advanced Features - I Module 11: CoolRunner-II CPLDs in Security Module 3: CoolRunner-II Advanced Features – II Module 12: XPower for CoolRunner XPLA3 CPLDs Module 4: CoolRunner-II In Cell Phone Security Module 13: XPower for CoolRunner-II CPLDs Module 5: Cell Phone Handsets Module 14: CoolRunner-II Low Cost Solutions Module 6: CoolRunner-II in PDAs Module 15: Digital Camera Design Module 7: DDR SDRAM Memory Interface Module 16: Low Power Memory Module 8: PicoBlaze CPLD Microcontroller Module 17: Smart Card Reader Module 9: Powering CoolRunner-II CPLDs Module 18: CryptoBlaze Quick Start Modules at: http://www.xilinx.com/products/cpldsolutions/quickstart.htm The CoolRunner XPLA3 CPLD Family Low Power and 3.3V Operation CoolRunner XPLA3 - The Lowest Power 3.3V CPLD Solution • Low power, high performance CPLD – – – – 5V tolerant I/O <100uA standby power Full JTAG compliance Industrial temp grade operates from 2.7V • Ultra-small chip scale packaging – Perfect for portable applications • Robust architecture delivers great ISP – Superior pin-locking • WebPACK & ISE software support The XC9500XL CPLD High Performance and 3.3V Operation XC9500XL Key Features • I/O Flexibility – XL: 5v tolerant; direct interface to 3.3v & 2.5v • Input hysteresis on all pins for improved signal integrity • Easy ATE integration for ISP & JTAG – Fast, concurrent programming times • 36 to 288 macrocell densities • Complete IEEE 1149.1 JTAG • Space-efficient chip scale packaging XC9500XL Family Macrocells Usable Gates tpd (ns) XC9500XL tpd (ns) XC9500XV Registers fSYSTEM XC9500XL XC9500XV Packages XC9536XL XC9572XL XC95144XL XC95288XL 36 800 5 4 36 178 200 72 1600 5 5 72 178 178 144 3200 5 5 144 178 178 288 6400 7.5 6 288 125 151 PC44 PC44 CS48 CS48 VQ44* VQ44* VQ64 VQ64 TQ100 TQ100 TQ144 TQ144 CS144 PQ208 BG256 FG256* CS280* Aggressive Cost Management It’s More Than Just Process and Product Technology Innovation Cost = Design + Product Cost + P W S A T I P COS D = Value Customer The Complete CPLD Solution • 1.8 volts to 5 volt operation • Low power/high performance • Low cost