SYNTHESIS
 It is a process if converting RTL into Gate-Level Netlist
 It can be optimized for
1. Timing: gate sizing, buffer insertion, logic rewrite, retiming, using faster cells
(lvt)
2. Area: using smaller cells(hvt), logic simplification, remove unused paths
3. DFT:
4. Power:
5. Runtime:
Synthesis Inputs:
RTL
Technology libraries
Constraints