Exp No:14
AES128 Cryptographic System
Date:
Aim: Type a Verilog code to run an Adder and a Counter using IP catalog and upload
the code on a FPGA.
Tools and Hardware: Vivado, Arty A7 100t FPGA Board
Theory:
AES128 is a symmetric-key cryptographic algorithm used for secure data encryption
and decryption. In this experiment, AES128 encryption and decryption datapaths were
implemented on FPGA using Verilog HDL and verified using Xilinx Vivado and Vivado ILA.
Procedure:
1. Open Xilinx Vivado and create a new RTL project for the Arty A7-100T FPGA board
2. Add all AES Verilog source files including aes_system_top, aes_encrypt_round,
aes_decrypt_round, subbytes, inv_subbytes, shiftrows, inv_shiftrows, mixcolumns,
inv_mixcolumns, sbox, and inv_sbox modules
3. Add S-Box and inverse S-Box memory files (sbox.mem and inv_sbox.mem) to the project
4. Open IP Catalog, search for “ILA”, and generate the Integrated Logic Analyzer IP core
5. Instantiate AES encryption, AES decryption, and ILA modules in the top-level Verilog module
6. Connect plaintext, SubBytes, ShiftRows, MixColumns, ciphertext, InvMixColumns,
InvShiftRows, InvSubBytes, recovered plaintext, round key, and control signals to ILA probes
7. Add and edit the FPGA constraint (.xdc) file and set aes_system_top.v as the top module
Once the Verilog code is typed and constraint file is edited proceed with the following steps:
1. Run Synthesis
2. Run Synthesis
3. Run Implementation
4. Generate Bitstream
5. Open Hardware Manager
6. Auto-connect the FPGA Board
7. Program the FPGA Board using generated bitstream
8. Observe all AES encryption and decryption stages using Vivado ILA waveforms
AES128 Encryption:
1. AES Encryption Top RTL:
2. Aes round RTL
3. SubBytes RTL
4. S-Box RTL
5. ShiftRows RTL
6. MixColumns RTL
7. Encryption Testbench
Constraint File:
AES128 Decryption:
1. aes_decrypt_top RTL
2. AES_decrypt_round RTL
3. inv_mixcolumns RTL
4. inv_shiftrows RTL
5. inv_subbytes RTL
6. inv_sbox RTL
7. Decryption Testbench
Constraint File:
Implemented Design:
Encryption ILA Waveform:
Decryption ILA Waveform:
Conclusion:
The AES128 Encryption and Decryption System was successfully implemented and
verified on FPGA using Verilog HDL, Xilinx Vivado, and Vivado ILA. All AES encryption
and decryption stages were successfully analyzed through RTL design, simulation, and
real-time hardware verification.