An Integer-First FastViT-T8 NPU: Technical Route
and SKY130 Evaluation
Chen Chen1 , Yu Hao1 , Letian Huang1 , Chaoyue Zheng1
1 University of Electronic Science and Technology of China, Chengdu, China
Email (Chen Chen): 202522310931@std.uestc.edu.cn
Abstract—We present an integer-first FastViT-T8 neural
processing unit (NPU) whose complete 53-layer graph is
mapped to RTL. The route combines an external INT8 interface, W8/A16 internal arithmetic, a 16 × 16 output-stationary
array, a dedicated depthwise engine, shared nonlinear lookup
tables, and a banked SRAM/DMA path. The software integer
reference reaches 75.736% Top-1 on the full 50,000-image
ImageNet-1K validation set, while five complete RTL inferences reproduce 5,000 logits bit-exactly. At a 10 ns synthesis
constraint, the measured schedule is 314.331 ms per image
(3.181 image/s); SRAM-inclusive SKY130 synthesis reports
38.561 mm2 cell area and 1383.4 mW estimated dynamic
power. A compact performance table separates software accuracy, RTL latency, and synthesis-stage PPA. Detailed evidence,
reproducibility logs, and implementation records are supplied
as competition materials.
Index Terms—neural processing unit, vision transformer,
post-training quantization, bit-exact verification, gate-level
power analysis, SKY130, design automation agent
I. OVERVIEW AND CONTRIBUTIONS
FastViT-T8 is a compact hybrid vision transformer [1],
but a complete accelerator must implement the whole graph
rather than only its dominant convolutions. The design reported here starts with the public fastvit_t8.apple_in1k
checkpoint and ends with 1,000 signed INT16 class scores.
The central engineering problem is to make quantization,
heterogeneous compute, nonlinear functions, and activation
movement obey one integer contract from software through
RTL.
The main results are an external INT8 interface with
W8/A16 internal arithmetic, a full 53-layer/83-boundary
RTL graph, and an SRAM-inclusive SKY130 synthesis
candidate. The integer reference reaches 75.736% Top-1 on
all 50,000 ImageNet-1K [2] validation images, only 0.450
percentage points below the matched FP32 graph. Five
complete RTL images reproduce 5,000 INT16 logits bitexactly. At a 10 ns synthesis constraint, the measured RTL
schedule uses 31,433,129 cycles per image, corresponding
to 314.331 ms and 3.181 image/s for the single-inference
interface. The synthesized candidate reports 38.561 mm2 cell
area and 1383.4 mW estimated dynamic power [3], [4].
A. Agent framework and design loop
The implementation is organized as a four-layer closed
loop. A contract layer lets the human planner freeze the
checkpoint, numeric and memory interfaces, tool boundaries,
and promotion gates. An execution layer lets a persistent
executor generate the integer graph, RTL, vectors, and
VCS/DC/Power Compiler/Formality runs from that contract.
An evidence layer records source/configuration hashes, semantic checks, counters, and limitations for every run. A
feedback layer classifies a failed check as functional, PPA,
or resource/tool related, then records alternatives, rollback
conditions, and a bounded rerun or escalates a scope decision
to the planner. The normal iteration is therefore task →
implement → verify → diagnose → record → rerun; tool
exit status alone never promotes a candidate.
This loop separates routine execution from human control. The planner chooses architecture and numeric-contract
boundaries; the executor owns reproducible generation, regression, synthesis, and diagnosis; human intervention is
reserved for contract changes, architecture promotion, timeout/licence/resource recovery, and evidence-scope decisions.
The four planner decisions, three decision requests, 18
material executor decisions, and raw status/log records are
retained in the competition materials, including representative interaction entries and manual interventions.
The hardware contribution is the end-to-end contract
produced by this loop: a 16 × 16 output-stationary array,
a dedicated depthwise path, shared nonlinear tables, and a
banked SRAM scratchpad. The external interface accepts
one contiguous 1 × 3 × 256 × 256 signed-INT8 image; internal
tensors are signed A16 in HWC16 order and the classifier
writes 1,000 INT16 scores. Host preprocessing is outside the
core-latency window, which starts at command acceptance
and ends at the first done_valid assertion.
II. MAIN TECHNICAL ROUTE
A. From model to an integer graph
Structural reparameterization folds training-time
branches and batch normalization into a graph with
3,996,040 parameters, 52 convolutions, and one Gemm.
The graph has 685,160,448 MACs per image; pointwise
layers account for 88.16% and depthwise layers for 7.33%,
so a single homogeneous array would waste cycles on
depthwise work. The route is therefore: reparameterize the
checkpoint; calibrate scales on the training split; lower
every operator to fixed-point arithmetic; map the resulting
53 layers and 83 boundaries to a frozen schedule; then
generate parameters, descriptors, test vectors, and RTL
from that same contract.
The adopted numeric format follows integer-inference
practice [5] and keeps the competition-mandated INT8 image input and the first convolution in A8, while using
W8 weights and A16 activations after the input boundary.
Host interface
Command / completion
Tag, base addresses, status
Control and operation dispatch
Descriptor decode; 83-row schedule ROM
Address/lifetime checks; 10 fused groups
External memory
INT8 RGB input
256 × 256, NCHW
53 descriptors
4,144,448 B parameters
Activation spill arena
1,000 INT16 output scores
Main compute path
16 × 16 output-stationary
A16 activations,
W8 weights
INT32 accumulation
Q31 requantization
DMA and scratch mover
128-bit data path
Up to 16 beats / burst
4 KiB boundary splitting
Input adapter; parameter loader
Measured RTL DMA
Read: 43,099,424 B
Write: 9,198,224 B
per complete image
Depthwise path
16 channels × 7 taps
3 × 3 / 7 × 7 kernels
Line buffers; INT32
Shared nonlinear and tensor services
GELU: 2,049 entries; sigmoid: 769 entries
Residual add; ReduceMean; final SE / pooling
Banked activation scratchpad: 176 KiB
16 banks × 5,632 words × 16 bits
88 SKY130 macros, each 32 bits × 512 words
Solid arrows summarize data exchange; dashed arrows summarize control. Compute engines are separately scheduled.
Fig. 1. Main data and control route. The host supplies the INT8 image, descriptors, parameters, and activation spill space; the fixed schedule dispatches
each graph boundary to the compute or nonlinear service; the banked scratchpad closes the loop before the INT16 classifier output is written back. Solid
arrows denote data movement and dashed arrows control.
Convolution and Gemm products accumulate in INT32. A
positive Q31 multiplier followed by a binary shift performs
requantization; round-to-nearest ties-to-even is applied before narrow-range saturation. Residual branches are aligned
in an 8-bit guard domain and rounded once. This choice
avoids the severe accuracy loss of uniform W8/A8 while
keeping the hardware datapath integer-only. The shared
GELU table has 2,049 entries and the shared sigmoid table
769 entries; each uses linear interpolation and is checked
against the exact integer oracle with at most one LSB error.
Quantization candidates were eliminated by end-to-end
accuracy rather than by operator-level error alone. Uniform
W8/A8 damages the early feature maps, while the adopted
W8/A16 graph keeps the mandated INT8 boundary and
limits A8 MACs to the input path. Bias correction was
evaluated as a refinement, but the final graph keeps one
canonical parameter package so that exported weights, software vectors, and RTL table packages cannot diverge. The
shared nonlinear tables are a second form of co-design:
the GELU table replaces 16 fully enumerated A16 oracles
and the final sigmoid table is reused across the SE path.
Exhaustive code-domain checks bound interpolation error
before any full-image RTL run.
B. From the graph to hardware
The hardware route follows the data lifetime and reuse
principles used in prior dataflow accelerators [6], [7]. A
512-bit descriptor identifies the operation, tensor geometry,
parameter offsets, residual boundary, and scratch/external
addresses. A fixed 83-row schedule ROM and an address/lifetime checker then dispatch the descriptor to one
of three paths:
1) the 16 × 16 output-stationary array handles pointwise
and ordinary spatial convolutions with INT32 accumulation and Q31 requantization;
2) a 16-channel, 7-tap engine handles 3×3 and 7×7 depthwise layers without forcing one useful lane through the
main array;
3) shared GELU, sigmoid, residual-add, ReduceMean,
SE, and pooling services implement the non-MAC
boundaries and feed the next tile.
The DMA path streams the INT8 input, packed parameters, and A16 activations through a 16-bank scratchpad.
The measured high-water mark is 5,632 words per bank, or
176 KiB, implemented by 88 SKY130 SRAM macros. Ten
depthwise–fc1–GELU–fc2–residual groups are represented
as atomic schedule entries, but the current baseline still
counts repeated halo and parameter reads; the analytical
traffic reduction is consequently kept as a design hypothesis
rather than reported as a measured speedup.
The external memory contract is intentionally simple.
Each layer has one 64-byte-aligned descriptor; a descriptor names the operation, tensor geometry, residual source,
parameter offset, and logical scratch/external addresses. The
128-bit DMA master permits at most one outstanding burst
and splits transfers at 4 KiB boundaries. The narrow protocol
makes every backpressure event visible to the counters and
TABLE I. PERFORMANCE, ACCURACY, LATENCY, AND PPA COMPARISON
UNDER THE RECORDED FASTVIT-T8 CONTRACT
Design point / Top-1 / Top- Cycles / latency Rate
scope
5 (%)
(img/s)
FP32 software 76.186/
(50k)
93.052
Integer software 75.736/
(50k)
92.944
Compute-only
—
bound
Proposed NPU 75.736∗
(INT8
in; 92.944∗
W8/A16)
PPA / traffic / evidence
—
45.367†
software reference
—
2.881†
software reference
3,001,584 issue —
cycles
/ 31,433,129
3.181
cycles; 314.331
ms
analytical; ideal compute only
38.561
mm2 ;
1383.4
mW;
434.8 mJ; 235,944
requests/image;
5
RTL images / 5,000
logits exact
∗ The NPU Top-1/Top-5 values are the software integer reference for the same
arithmetic contract; RTL was replayed on five images and matched all 5,000 logits.
† Software throughput is a host rate, not NPU performance. The compute-only row
is an analytical issue bound and omits memory, control, nonlinear, and stall cycles.
The NPU latency and throughput use the met 10 ns synthesis constraint, so they are
implementation estimates rather than silicon measurements; dynamic energy is power
times latency for the same inference window.
simplifies replay, but it also exposes memory stalls in the latency. The control plane is therefore part of the performance
path: the fixed schedule, address resolver, and operation
coalescer determine when compute, nonlinear service, and
spill traffic may proceed.
The width choice was made with same-constraint component synthesis. The adopted 16 × 16 array plus depthwise
path has 3,001,584 compute-only issue cycles and a summed
component area of 1,770,881.74 𝜇m2 . A 16 × 32 alternative
reduces the issue bound to 1,804,944 cycles but raises
area to 3,074,544.76 𝜇m2 , giving an area–cycle product of
1.04401× the baseline; it was not promoted to the top.
III. RESULTS AND PERFORMANCE COMPARISON
Table I compares the software references, the analytical
compute bound, and the implemented NPU in their measurement domains. The NPU latency is the complete singleinference RTL schedule.
The integer graph preserves 92.944% Top-5 accuracy
and loses only 0.108 percentage points against FP32. In
VCS, ten arithmetic and compute primitives pass bit-exact
checks, subsystem suites pass, and five complete top-level
images produce 5,000/5,000 matching INT16 logits with
zero mismatches. The schedule is data-independent across
those samples: each uses 31,433,129 cycles and the same
scratchpad high-water mark.
The PPA run links all 88 SRAM macros. It reports
38.561 mm2 of synthesis cell area at 100 MHz and
1383.4 mW dynamic power from one complete inference
activity window. SRAM contributes 64.93% of cell area,
which makes activation capacity the dominant physical cost.
The measured RTL schedule is about 10.5 times longer than
its compute-only issue bound because the one-outstandingburst memory contract exposes DMA stalls; this is the
primary optimization target.
Verification has four levels: full-set FP32/integer software references; ten directed VCS primitive suites containing 1,207,630 records; subsystem regressions for descriptors,
DMA, compute, elementwise services, and scheduling; and
five complete RTL images with every class value compared.
The last level supports the bit-exact claim; the 50,000-image
accuracy remains a software reference and is not promoted
to 50,000 RTL simulations.
A. Evaluation basis
The reported results are organized by evidence level:
full-set software accuracy, complete RTL functional replay
on five fixed images, and synthesis-stage PPA under the
recorded 100 MHz contract. This separation keeps the accuracy, bit-exact functional evidence, latency, area, and power
figures directly comparable. Detailed logs, hashes, verification matrices, and reproduction commands are retained in
the competition materials.
IV. CONCLUSION
An integer-first route turns the complete FastViT-T8
graph into an executable RTL NPU: calibrated W8/A16
arithmetic feeds specialized compute engines, shared nonlinear services, and a banked SRAM/DMA path under a
frozen descriptor schedule. The resulting design reaches
75.736% Top-1 in the full software reference, reproduces
five complete RTL inferences bit-exactly, and provides a
quantified 3.181 image/s, 38.561 mm2 synthesis-area, and
1,383.4 mW dynamic power point under the recorded 100
MHz assumptions. The competition materials retain the
detailed verification records and implementation notes for
reproducibility and the next iteration.
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