Synthesis
© Radiant Semiconductors Confidential
1
Agenda
• What is Synthesis
• Goals of Synthesis
• EDA Tools used for Synthesis
• Synthesis Flow
• Inputs For Logic And Physical Aware Synthesis
What is Synthesis..?
• Synthesis is the process of mapping RTL(Register transfer level)
which was written in Verilog(.V) to a technology dependent Gate
Level Netlist along with optimized PPACS (Power, Performance,
Area, Congestion, Schedule).
Goals of Synthesis
• To generate a Gate Level Netlist
• Inserting clock gates
• Logic Optimization
• Inserting DFT Logic
• Logic Equivalence between RTL and Netlist should be maintained.
EDA Tools For Synthesis
Synopsys:
Design Compiler
Design Compiler Graphical
Cadence :
Genus
Synthesis Flow...
Importing Input files (RTL code and .lib files)
Elaborate
Read SDC file
Sanity checks (check_design, check_timing)
Generic mapping
Technology mapping
Optimization
DFT (Design For Testability) implementation (Done by DFT team)
Incremental optimization
Generating outputs
Logic & Physical Aware Synthesis Inputs
• Specifying Libraries
• Reading the RTL
• SDC
• UPF
• ScanDef
• Additional Inputs for Physical AwareSynthesis
• Technology File
• TLU + File
• Layer Map File
• Floor plan Def
Timing Library
• Library file Content:
• Library name and technology name
• Units (time, power, voltage, current, resistance and capacitance).
• Operating condition ( process, voltage and temperature) – Max, Min and Typical.
• Slew transition.
• Setup and Hold time requirements.
• Cell information .
• Cell name.
• PG Pin name.
• Area of a cell.
• Pin Details
• Pin name.
• Pin Direction.
• Capacitance.
RTL ( Register Transfer Level)
RTL description captures the intended functionality of the digital
circuit.
Which was written in Hardware Description Language (HDL) like
Verilog or VHDL.
After the RTL code is written inorder to make sure that this code is
matching the functional requirements or not. We need to do functional
simulations on RTL if it is passing then only it need to be provided for
the Synthesis.
Unified power Format
• UPF file contents
• Power PG Net Information.
• Power domain Information.
• Power Switches
• Power supply nets , pins.
• Level Shifters.
• Isolation cells.
• Retention flop.
• Always ON cells.
SDC(Synopsys Design Constraints)
Clock Definitions
• create_clock
• create_generated_clock
• Create_clock -Vir
Clock related constraints
• Uncertainty
• Jitter
• Latency
Timing Exceptions
• False path
• MCP(Multi Cycle Path)
• Max/Min delay
• Disable timing
• Case Analysis
Technology File
• The technology library contains detailed information about all the metal layers,
vias and their design rules.
• Contents of tech file
• Manufacturing Grid
• Layer information
• Pitch of metal layers
• Width
• Spacing
• Resistance
The technology file used by the Cadence tool is .techlef format and .tf format
by Synopsys tool.
TLU + (Table Look Up) File
• The TLU + file R&C(Resistance & Capacitance) coefficient values
which was provided from the foundry and the file format is in
binary.
• This contains unit of R&C values for each metal layer, via and for
RC extraction of nets in different physical design tools also this tlu +
file is been used.
• As it is in binary only the DC Graphical & Fusion Compiler can read
this file and do the RC extraction for computing net delays.
• For net delay in LAS(Logic Aware Synthesis) we will be relaying on
wire load model present in the timing library files given by foundry.
Layer Map File
The naming Convention of each metal layer between the Technology
file(.tf) and TLU+ file.
In technology file the naming is M1 and TLU+ nameing is metal then
inorder to tell the synthesis tool that M1 and metal 1 both are same
between these two files we need this layer map file.
If the metal layers are same between these files then we will not need
layer map file.
Floor Plan Def
The DEF contains the physical information of the design like :
• Die area
• Row definition
• Macro definition
• STD cell definition
• Nets
• Ports
• Blockages
• Module Constraints
• Power information
Thank You