W1 L1
Introduction to
ELEC 422/527
VLSI Systems
Design
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Rice ELEC 422/527 Intro
 Syllabus is posted on Esther and also on the Canvas page
 We will use the 3rd edition of the textbook primarily. Most of the lecture
notes are intended for the 4th edition, so either is fine for background.
 We will use mostly Linux design tools for our projects.
– Tools are on the Rice CLEAR Linux cluster
– Mix of public domain (magic and irsim) and commercial CAD tools
from Synopsys (Design Compiler / Hspice), Mentor Graphics
(Modelsim/Questa), and Cadence (EDI Encounter/Innovus)
– MobaXterm (Windows) or Xquartz (Mac) for Xwindows access
– Windows WSL2 is helpful for public tools.
 We intend to prepare VLSI chip designs suitable for foundry fabrication,
such as through the MOSIS service or Skywater 130.
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Course Topics
 Multiple aspects of the course which focuses on Digital VLSI Systems
 Mask level VLSI circuit design, simulation, and test
 Computer Aided Design tools using Verilog HDL
 System design through synthesis / place and route
 Group Design Project on your own concept
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Course Tasks
 Six individual homework assignments on circuits, layout, timing,
simulation, logic families, I/O pad routing
 Major course design project – groups of 2 or 3 depending on class size
– Chip Design component – Start forming groups now!
– Presentation and report with simulation and verification analysis
– Due the last day or finals
 ELEC 527 students have an additional survey report or homework, TBD.
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Design Project Topics
 About 5000 transistors ~ 1000 gates
 Semester design process top-down specification -> bottom-up design
 “Small” processors, encoders/decoders, games
 Typical possible project topics examples (groups of 2 or 3 students):
– TinyRISC – control unit focus
– Cipher chip – encoder – decoder
– Small AES encryption engine
– Tetris-like game
– Blackjack game
– Two-dimensional parity-check
– Digital filter / frequency detector
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Design Layout
 Start with full custom
NAND / NOR, static latch
for cell library design
 Core design from Verilog
to standard cells
 Verilog used to express
datapath and finite state
machines
 Synthesis and place and
route core targeted for
“standard cell” libraries
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Padframe and Core
 Design core needs to
interact with external system
 I/O Pads provide interface
and signal conditioning
 I/O Pads are grouped to
form a perimeter frame
 Vdd and GND routing to
power the core
 Clock signal routing for finite
state machine control
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Package / Bonding Map
 Many prototype chips
are packaged in a Dual
Inline Package or “DIP”.
 40 Pin DIP packaging
has been used for class
projects.
 External pin numbers
are important for final
simulation and
verification.
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Project Milestones
 Detailed timeline to be posted in Files>Administration_Notes
 Outline is:
– January: Project topic, definition, algorithm
– February: Finite State Machine design and simulation along with
Data Path creation
– March: CAD tool mask layout and integration and simulation
– April: Additional testing and simulation; integration into I/O padframe;
final density checks
– May: Final report on project; CIF/GDS layout file ready for potential
foundry submission – last day of exams – May 5
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Course Goals
 Understanding of VLSI design layout and logic cells
– Standard CMOS and dynamic logic including timing and simulation
– CMOS processing step and layout design rules
 Use of Verilog HDL to model datapath and finite state machine controllers
 CAD Design tools for layout, simulation and timing, place and route
 System Integration issues including local and global power and ground
routing, clock distribution, antenna and layer density rules, I/O pad design
and integration.
 Basically, how to design your own custom VLSI ASIC chip!
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Questions???
 Let’s stop for
 Questions
 Introductions
 Your Interests and Ideas
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VLSI Introduction
 Integrated circuits: many transistors on one chip.
 Very Large Scale Integration (VLSI): Thousands of transistors!
 Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors
 Today: Summary of how to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
 Rest of the course: How to build a complete CMOS chip
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Digital Design Tools
 Computer Aided Design tools handle complexity.
 Needed to abstract transistor performance.
 Needed to build hierarchical designs.
 Based on geometry of VLSI process layers, metal, polysilicon,
diffusion area.
 Characterized for rise time, fall time, and delay.
 Cell libraries contain these basic logic gates.
 Place and route tools can array and connect cells.
 Verilog can be synthesized to a netlist of cells.
 Chips can be expressed and simulated in Verilog
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Design Tool Flow
 Create Verilog model of design
 Simulate behavior with Modelsim/Questa
 Synthesize design with Design Compiler
 Simulate behavior with cell models in Modelsim/Questa
 Place and route with Cadence EDI Encounter/Innovus
 View Chip Layout GDS file
 Import GDS file to Berkeley Magic
 Gate level simulation with Irsim and Hspice/Saber
 Integrate into I/O Padframe
 Final simulation with Irsim
 “Tape Out” and send GDSII file to foundry
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Transistors as Switches
 We can view MOS transistors as electrically controlled switches
 Voltage at gate controls path from source to drain
d
nMOS
pMOS
g=0
g=1
d
d
OFF
g
ON
s
s
s
d
d
d
g
OFF
ON
s
s
s
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CMOS Inverter – n and p devices
A
Y
0
1
1
0
VDD
A
0
1
OFF
ON
Y
ON
OFF
A
Y
GND
16
17
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CMOS Inverter – n and p devices
A
Y
00
11
11
00
VDD
A
0
1
OFF
ON
Y
ON
OFF
A
Y
GND
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CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
ON
OFF
OFF
ON
A
B
1
0
0
1
1
0
OFF
ON
Y
ON
OFF
OFF
ON
ON
OFF
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21
22
23
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CMOS NOR Gate
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
A
B
Y
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3-input NAND Gate
A
0
0
B
0
0
C
0
1
Y
1
1
0
0
1
1
0
1
1
1
1
1
1
0
0
1
0
1
0
1
1
1
1
1
1
0
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0
A
Y
B
C
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CMOS Fabrication
 CMOS transistors are fabricated on silicon wafer
 Lithography process similar to printing press
 On each step, different materials are deposited or etched
 Easiest to understand by viewing both top and cross-section of wafer in
a simplified manufacturing process
 Top view is what we will see in the Magic layout editor
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Inverter Top View
 Transistors and wires are defined by masks
 Cross-section taken along dashed line
A
Y
GND
VDD
nMOS transistor
substrate tap
pMOS transistor
well tap
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Inverter Cross-section
 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors
A
GND
VDD
Y
SiO2
n+ diffusion
n+
n+
p substrate
nMOS transistor
p+
p+
n well
p+ diffusion
polysilicon
metal1
pMOS transistor
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CLEAR Linux Environment
 Short introduction demo of connection to CLEAR for “inverter” cell
 On Windows, using MobaXterm which is on Ryon B22 and PCF3 lab
machines and available for download for free “Home Edition” version
 Connect to ssh.clear8.rice.edu only with your Rice NETID
 Class files are in the “elec422” account
– Home directory is /clear/courses/elec422
– Quick look at the inverter and ring oscillator folders
– UC Berkeley “Magic” layout editor is used for design
– http://opencircuitdesign.com/magic/
– Irsim is used for “switch level” digital simulation
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CAD Tool Demo
 On CLEAR, in ~elec422/2026_spring/inverter
 And in ~elec422/2026_spring/ringosc
 Basic inverter cell. Replication for ring oscillator.
 Through the semester, demos will be in ~elec422
 ~ is the home directory, in this case of elec422
 cd ~
takes you to your home directory.
 To copy the demo to your directory to read/write:
 mkdir demo
 cp –r ~elec422/2026_spring/inverter demo/inverter
 cp –r ~elec422/2026_spring/ringosc demo/ringosc

There is a space between the command “cp” and the option “-r” and another space between
that and the source and destination folder names.
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CAD Tool Examples
 Now in your home directory folder, cd demo/inverter
 Magic will show mask layers and design rule errors.
 Circuit extraction finds transistors for simulation.
 If you type:
pwd
ls -l
You will see the .mag files which we can open but only the owner can write. If you
copied them to your folder, then that is you, and you can edit. Linux has strict user
permissions. “rwx” are permission “bits.”
Now type:
magic inverter
:extract all
:ext2sim –t!
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Inverter Example
To simulate, type: irsim inverter.sim
then in the console window: source inverter.cmd
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17 Stage Ring Oscillator
 First stage is a NOR gate followed by 16 inverter cells
 Why an odd number? (so it will oscillate)
 Long polysilicon feedback is usually bad, so changed layer to Metal1
 Irsim will show (digital) oscillations, Hspice will show more analog
behavior
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About these Class Notes
 Modified for Rice CAD tools and environment, demos, examples, and
homework by Joseph Cavallaro
 Some lecture notes from textbook by © David Money Harris
 Those notes may be used and modified for educational and/or noncommercial purposes so long as the source is attributed.
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Next Class
 Begin to form project groups and “one paragraph” topic
 CMOS process technology and fabrication
 CMOD process design kits
 CMOS design rules
 Brief intro to Linux
 Tutorial and demo on design tools on CLEAR
– Set up of accounts using lab computers or laptops
• If your laptop, strongly suggest three button mouse
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