The Incredible Shrinking Transistor – Shattering Perceived Barriers and Forging Ahead
Tahir Ghani and Pushkar Ranade
Intel Corporation, USA email: tahir.ghani@intel.com, pushkar.ranade@intel.com
Abstract – 2025 will mark the 60th anniversary of Gordon
Moore’s prescient observation that became the catalyst for
transistor scaling and the modern digital age [1]. This paper
discusses the evolution of the transistor over the last six
decades, spanning multiple eras of computing. The likely
evolution of the transistor over the next ten years is discussed,
along with a call to action to develop a revolutionary transistor
that will enable the era of pervasive Artificial Intelligence (AI).
I.
INTRODUCTION
We will witness a remarkable milestone by the end of this
decade – one trillion transistors within a tiny microprocessor
package. This paper takes a sweeping view of multiple waves
of innovations that drove transistor scaling over the last six
decades before outlining critical innovations that will be
necessary for continued scaling over the next ten years.
Breakthrough innovations in materials and architectures will
be needed to overcome the most daunting challenge in the
coming years – lowering energy consumption to enable
sustainable deployment of the exponentially growing demand
for AI compute.
II.
industry found itself facing fundamental barriers to continued
transistor scaling.
III. SECOND ERA : 2005 - PRESENT
During the last 20 years, technologists shattered multiple
seemingly insurmountable barriers to transistor scaling,
including perceived limits to dimensional scaling, limits to
transistor performance, and limits to Vdd reduction. This era
marked the emergence of mobile computing, which shifted the
focus of transistor development from chasing raw performance
(frequency) to maximizing performance within a fixed power
envelope (performance-per-watt).
Exponential growth in transistor count continued unabated,
albeit without the tailwinds of Dennard scaling, thus presenting
another challenge – how best to utilize an abundance of
transistors to improve performance while staying within a fixed
power budget. This constraint was addressed by an architectural
solution – core-level parallelism (Figure 3). Even with multicore architectures, increasing power density eventually
rendered sizeable blocks of transistors unusable at any given
time (also known as “dark silicon”).
FIRST ERA : 1965 – 2005
The first four decades of Moore’s Law saw exponential
growth in transistor count and enabled multiple eras of
computing, starting with the mainframe and culminating in the
PC (Figure 1). Moore’s Law and the scaling physics established
by Dennard [2] in 1974 led to consistent dimensional scaling
with progressively higher transistor performance. This happy
marriage between Moore’s Law and Dennard scaling ushered
in a golden era of computing (Figure 2). This era was made
possible by numerous innovations in materials and process
engineering, most important being the consistent scaling of gate
dielectric thickness (Tox) and the development of progressively
shallower source/drain (S/D) extensions, which enabled scaling
of gate lengths from micron-scale to nanometer-scale while
lowering transistor threshold voltage (Vt).
This period required a significant reduction in transistor
operating voltage (Vdd) from 5V (up to the early 1990s) to 1.2V
(around 2005) to maintain product reliability with progressively
thinner Tox. These transistor innovations enabled chip clock
frequencies to increase from tens of kHz to 3GHz, as
summarized in Figure 2 [3]. Over time, the quest for raw
performance forced faster Tox and effective channel length
(Leff) scaling compared to Vdd scaling, thus increasing electric
field across the device. Furthermore, additional Vdd scaling
became limited by off-state leakage (Ioff). This led to
progressively higher power densities and, eventually, the
breakdown of Dennard scaling. Power density was pushed to
the limit (Figure 2) allowed by the economics of packaging and
thermal dissipation capabilities of the day. By 2005, the
Concurrently, the transistor also reached physical limits of
silicon dioxide Tox scaling and a progressive degradation in
silicon channel mobility, which threatened to limit further gains
in performance and power efficiency (Figure 4). Radical
transistor innovations would become necessary to surmount
these perceived fundamental barriers.
IV. SEMINAL TRANSISTOR INNOVATIONS
Starting in the early 2000s, technologists at Intel pioneered
the use of novel transistor materials and architectures. They
expedited the progress of groundbreaking ideas from research
to development and high-volume manufacturing. These
innovations ushered in an era of astonishing progress in
transistor technology over the following two decades.
A. Mobility Enhancement  Uniaxial Strained Silicon
Figure 5 shows the novel transistor structure introduced by
Intel at the 90nm node (2004) to incorporate compressive
strain for PMOS mobility enhancement [6]. Intel’s uniaxial
strain approach was in stark contrast to the biaxial strain
approach pursued by the research community and turned
out to be superior for performance and manufacturability.
Moreover, this architecture proved scalable and enabled
progressively higher strain and performance over the years.
B. Tox limit  Hi-K Dielectrics and Metal Gate Electrodes
Intel explored multiple approaches to introduce Hi-K gate
dielectrics coupled with metal gate electrodes, including
“gate-first,” “replacement-gate,” and even fully-silicided
gate electrodes. The replacement metal gate flow adopted
by Intel at the 45nm node (2007) continues to be used in all
advanced node processes to this day (Figure 6) [7].
C. Planar transistor limit  FinFETs
The scaling of the planar transistor finally ran out of steam
after five decades, mandating a move to the 3D FinFET.
Intel was the first to introduce FinFETs into production at
the 22nm node (2011) [8]. Nanometer-scale fin widths
enabled superior short-channel effects and, thus, higher
performance at lower Vdd. Figure 7a shows the evolution
of the fin profile over the last 15 years. The 3D structure of
fins resulted in a sharp increase in effective transistor width
(Zeff) within a given footprint, leading to vastly superior
drive currents (Figure 7b).
V.
LOOKING AHEAD : THE NEXT DECADE
The seventh decade of Moore’s Law coincides with the
emergence of yet another computing era. AI will redefine
computing and is already causing a tectonic shift in the enabling
silicon platform from general-purpose processors (CPUs) to
domain-specific accelerators (GPUs and ASICs).
This shift in computing platform also coincides with yet
another inflection in transistor architecture. Figure 8a depicts
the Gate-all-Around (GAA) transistor, poised to replace the
FinFET. The GAA transistor delivers enhanced drive current
(Figure 8b) and/or lower capacitance within a given footprint,
superior short-channel effects, and a higher packing density.
The GAA architecture will likely be succeeded by a stackedGAA architecture (Figure 9) with N/P transistors stacked upon
each other to create more compact, monolithic 3D compute
units [10]. Beyond stacked silicon CMOS, 2D transition metal
chalcogenide (TMD) films are being investigated as channel
material for further Leff scaling, but many issues persist [11].
Worldwide energy demand for AI computing is increasing
at an unsustainable pace (Figure 10). Furthermore, transitioning
to chiplet-based System-in-Package (SiP) designs with 3D
stacked chips and hundreds of billions of transistors per
package will increase heat dissipation beyond the limits of
current best-in-class materials and architectures. Breaking
through this impending “Energy Wall” will require coordinated
and focused research toward reducing transistor energy
consumption and improving heat removal capability.
VI. CALL TO ACTION : NEW TRANSISTOR
A focused effort is necessary to develop a new transistor
capable of operating at ultra-low Vdd (< 300mV) to improve
energy efficiency. However, ultra-low Vdd operation can lead
to significant performance loss and increased sensitivity to
variability, requiring circuit and system solutions to be more
resilient to variation and noise. This highlights the need for a
strong collaboration between the device, circuit, and system
communities. Improving transistor performance at ultra-low
Vdd requires the development of a super-steep sub-threshold
slope transistor (Figure 11) and the use of high-mobility
channel materials. Potential options for a super-steep subthreshold slope transistor include Tunnel FET (TFET),
Negative Capacitance FET (NC-FET), and Ferroelectric FET
(FE-FET), each with unique challenges. TFETs have been
perennially plagued with low drive current and less-thanprojected improvement in sub-threshold slopes [12]. The NCFET relies on a ferroelectric gate insulator [13]. Negative
differential capacitance in ferroelectrics can amplify changes
in surface potential in response to gate voltage (Figure 12).
This leads to lower sub-threshold slopes and lower equivalent
oxide thickness (EOT), as shown in the equation below:
=
+
This was followed by the discovery of a stable ferroelectric
(FE) phase in HfO2−ZrO2 mixed oxide [14]. Figure 13 shows
experimental results demonstrating significant EOT scaling for
an NC-FET using FE HfO2–ZrO2 gate stack [16]. A long-term
challenge for NC-FET is to extend scaling to a “negativeEOT” regime to enable < 60 mV/decade sub-threshold slope.
While NC-FET is designed for hysteresis-free operation,
FE-FET is hysteretic. Figure 14 illustrates the operation of FEFET, which relies on ferroelectrics with low coercive voltage
to generate an “effective” ultra-steep sub-threshold slope.
Given the significant loss in drive current due to low gate
overdrive, high-mobility channel materials could boost the low
drive at ultra-low Vdd. A targeted introduction of highmobility channel materials such as Germanium (Figure 15),
III-Vs, and carbon nanotubes (Figure 16) into existing mature
silicon substrates is expected to yield rich dividends.
VII. SUMMARY
The number of transistors in a package will continue to
increase substantially over the next ten years. Developing an
ultra-low Vdd transistor will help address one of the most
significant contributors to AI energy consumption and thermal
concerns in the trillion transistor era.
At every significant inflection in the past, when challenges
to continued transistor scaling seemed too daunting,
technologists across industry and academia forged new paths to
enable the arc of exponential progress to continue unabated.
There is no reason to believe that this trend will not continue
well into the future. There is still plenty of room at the bottom.
REFERENCES
[1] G.E. Moore, Electronics, vol. 38, no. 8, 1965, pp. 114-117.
[2] R. Dennard et al., IEEE J. Solid-State Circuits, v. 9, 5, pp. 256-268, 1974
[3] 42 Years of Microprocessor Trend Data | Karl Rupp
[4] T. Ghani et al., Symp. VLSI Tech. Digest, pp. 174-175, 2000
[5] S. Thompson, IEDM Short Course, Washington, D.C., 1999
[6] T. Ghani et al., IEDM Tech. Digest, pp. 978-980, 2003
[7] K. Mistry et al., IEDM Tech. Digest, pp. 247-250, 2007
[8] C. Auth et al., Symp. VLSI Tech. Digest, pp. 131-132, 2012
[9] W. Hafez et al., Symp. VLSI Tech. Digest, pp. 1-2, 2024
[10] M. Radosavljević et al., IEDM Tech. Digest, pp. 1-4,2023
[11] W. Mortelmans et al., Symp. VLSI Tech. Digest, pp. 1-2, 2024
[12] Y. Zhai et al., Mater. Horiz., pp.1601-1617, 2021
[13] S. Salahuddin et al., Nano Letters, 8, pp. 405-410, 2008
[14] J. Müller et al., Nano Lett. 12, 8, pp. 4318-4323, 2012
[15] S. Chaudhary et al., HB of Emerging Mat. for Semi Industry, pp. 577-596
[16] S. Cheema et al., Nature 604 (7904), pp. 65–71, 2022
[17] W. Rachmady et al., IEDM Tech. Digest, pp. 29.7.1-29.7.4, 2019
[18] C. Qiu et al., Science 355, 271-276 (2017)
Fig. 1. Transistor count within a package is
expected to reach the one trillion milestone by
2030, enabled by multi-chip System-inPackage (SiP) integration.
Fig. 2. Moore’s Law and Dennard scaling enabled a
golden era of computing. Adapted from [3].
Fig. 3. Core-level parallelism enabled
continued performance enhancement even in
a post-Dennard scaling era.
Fig. 4 (a) Fundamental limits to gate oxide
thickness scaling and (b) rapid degradation
in NMOS universal mobility due to
increasing electric field [4] [5].
Fig. 5. SiGe in the source/drain regions allowed
uniaxial strain to be introduced into transistor
channels, providing a significant boost to PMOS
transistor drive current at the 90nm node in 2004.
Fig. 6. Hi-K dielectrics and metal gate electrodes
represented the most fundamental change to the
transistor and integrated circuits since the 1960s.
350
2011
2024
30 0
FinFET
250
Zeff (nm)
Intel 3
200
FinFET
Intel 22nm
150
3.6X
10 0
50
Planar transistor
0
0
20
40
60
80
100
Top Footprint (nm)
Fig. 7a. Fin profiles have seen dramatic
improvement from the original (2011) [8] to
the most recent process (2024) [9]. Straight fin
profiles enable superior electrostatic control.
Fig. 7b. FinFET transistors allowed for a massive
increase in effective transistor width (Zeff) within a
given footprint, while also improving electrostatic
scalability to lower gate lengths.
Fig. 8a. Gate-all-around (GAA) transistor improves
electrostatic scalability compared to the FinFET by
completely wrapping the gate around the channel.
350
300
NMOS
4.4X
250
Zeff (nm)
12nm
FinFET
200
25nm fin pitch
4 high
150
Ribbon
PMOS
100
3 high
Ribbon
50
0
0
20
40
60
Top Footprint (nm)
Fig. 8b. Gate-all-around transistor also enables
significantly higher effective channel width
for a given footprint or a footprint reduction
for a given effective width.
Fig. 9. A cross-section of a stacked-GAA
transistor with NMOS stacked over PMOS [10].
Stacking N/P transistors enables significant
compaction of CMOS footprint.
Fig. 10. Worldwide energy demand for AI
computing is increasing at an unsustainable pace.
(adapted from Wells Fargo and AEP)
Fig. 11. A sub-threshold slope < 60mV/decade
enables Vt reduction at a given Ioff and
improves performance at ultra-low Vdd.
Fig. 12. New ferroelectric based transistors
offer a path to lower operating voltages to
reduce total energy consumption [15].
Fig. 13. Ultrathin HfO2–ZrO2–HfO2 (HZH)
gate stack showing large improvement in EOT
at constant gate leakage [16]. This enables
drive current and electrostatics improvement.
Fig. 14. Schematic to illustrate NMOS
ferroelectric FET (FE-FET) behavior with ultralow switching voltage ferroelectric enabling an
effective sub-threshold slope < 60mV/decade.
Fig. 15. TEM cross-section of germanium
channel transistor showing high measured hole
mobility for improved PMOS performance [17].
Fig. 16. TEM cross-section of CNT transistor
showing higher drive current at Vdd=0.4V
compared to a traditional FinFET. Adapted
from [18].