Sign In High-Speed Design Resources High-Speed Design Sea… The IEEE P370 Standard for High Speed PCB Interconnects The IEEE P370 Standard for High Speed PCB Interconnects Zachariah Peterson | Created: November 13, 2020 | Updated: November 14, 2020 Table of Contents Digging into the IEEE P370 Standard Test Structures De-embedding S-parameter Quality Placing Test Structures on Your PCB High speed PCB interconnects have continued to remain an active challenge in modeling and simulation, particularly when dealing with broadband signals. The IEEE P370 standard is a step towards addressing the challenges faced by many designers in determining broadband S-parameters for high speed structures up to 50 GHz. Although this standard has been in the works since 2015, it finally passed board approval and appears as an active draft standard. So what are the challenges addressed by this standard, and how will signal integrity engineers benefit? If you’re like me, you approach signal integrity problems from a different direction than someone like Heidi Barnes or Jason Ellison. One side of signal integrity is prediction from empirical models or analytical formulas, while the other side is about evaluation and characterization from signal behavior measurements. IEEE P370 addresses challenges on the test and measurement side, particularly for gathering specific measurements from complex test structures on PCBs. Try Altium Designer Thank you, you are now subscribed to updates. Get Altium Designer for free for 2 weeks Get Altium Designer for free for 2 weeks Digging into the IEEE P370 Standard Get Altium Designer for free for 2 weeks Sign In The IEEE P370 standard deals with test and measurement procedures for characterization of electrical interconnects up to 50 GHz. As part of testName* and measurement tasks for a device under test at high frequencies, any instrument needs to interface with the DUT. High frequency First High-Speed Design instruments like time domain reflectometers (TDRs) and vector network analyzers (VNAs) typically use a coaxial connector to gather accurate measurements, but many real structures on a PCB or other electronic packages are not coaxial once they create an interface with the DUT. Last Name* As part of the standard, IEEE P370 aims to address interconnect modeling and characterization challenges in three key areas of high speed Company design: Email* Acknowledging Altium’s Privacy Policy, I consent that Altium processes my Personal Data to send me communications, including for marketing purposes, via email and to contact me by phone. High-Speed PCB Design Simple solutions to high-speed design challenges Next Step Explore Solutions Test fixture design. Test fixtures interfacing between an instrument and the DUT (in this case, an electrical interconnect) cause the measured S-parameters of the DUT to be different from the real S-parameters. The same applies to other parameter sets used in device characterization. De-embedding. The process for retrieving the S-parameters of the DUT is with de-embedding. Unfortunately, different instruments and software tools have different algorithms for de-embedding. Part of this problem is that a DUT and its test fixtures form a cascaded Nport network, and S-parameters do not cascade nicely in the same way as ABCD parameters. Ensuring S-parameter quality. The three primary problems in S-parameter quality are ensuring reciprocity, passivity, and causality. By standardizing the first two points, we get closer to some standardization in the third point. This third area of high speed interconnect modeling is one that remains challenging for even the most experienced engineers due to the inherently band-limited nature of broadband measurements. IEEE P370 aims to address these inconsistencies with the solutions outlined in the following table. Area Solution Test fixture design Specific structures needed for de-embedding, their electrical requirements, recommended layout practices are provided De-embedding Heavily validated S-parameters are provided in a library for standardized test structures to ensure consistent de-embedding across instruments. S-parameter quality A procedure for evaluating S-parameter quality and acceptable limits on S-parameter artefacts are provided. Easy, Powerful, Modern The world’s most trusted PCB design system. Explore Solutions Let’s look at each of these areas a bit closer to see how things may soon change for signal integrity engineers. Test Structures This area of the IEEE P370 standard is divided into two broad areas: test structure design and calibration. By using standardized test structures and calibration structures, we can be reasonably assured that two different engineers with two different (yet comparable) instruments can produce the same S-parameter results for a given DUT using a standard procedure. The 2x-thru test structure is recommended under P370; take a look at this Signal Integrity Journal article to learn more about the 2x-thru structure and how it’s used in de-embedding. There are two standardized structures in IEEE P370 that can be used for calibration and fixture de-embedding verification: the line and Try Altium Designer you, you are updates. Beatty standards. The line structure is just Thank a transmission line,now forsubscribed which the to S-parameters can be determined from the line’s ABCD Get Altium Designer for free for 2 weeks Get Altium Designer for free for 2 weeks parameters. The Beatty structure is a resonant cavity located along the center of a transmission line, which has a particular return loss and Get Altium Designercan for free for 2 weeks Sign In insertion loss spectrum for a given length. This structure (see below) be placed on a test coupon or prototype for instrument calibration as its S-parameters are well-known. High-Speed Design Acknowledging Altium’s Privacy Policy, I consent that Altium processes my Personal Data to send me communications, including for marketing purposes, via email and to contact me by phone. Beatty structure and its resonances. De-embedding The de-embedding procedure uses an open access library of gold-standard S-parameters for standard test structures specified in the IEEE P370 standard. Because the test structure S-parameters are known or supplied by the standard, then the test structure S-parameters can be removed from the (DUT + test structure) S-parameters. This gives just the S-parameters of the DUT, as shown in the example below. De-embedding example and results. [Source] S-parameter Quality The quality of an S-parameter matrix is defined in the following three areas: Causality. When used to construct an impulse response with a standardized method, the S-parameters should not produce causal artifacts in the time-domain response. Reciprocity. If the DUT in question is indeed reciprocal, then the S-parameters must also be reciprocal, i.e., the S-parameter matrix is equal to its own transpose. Passivity. This is related to reciprocity in that a reciprocal network must also be a passive network. S-parameters need to be evaluated for passivity, meaning they are not functions of the input signal strength. By setting limits on these quality metrics, designers who receive S-parameter data for their components or who place passive structures on their PCBs can be assured their simulations will be accurate. This solves a major problem of inconsistent S-parameter data. Placing Test Structures on Your PCB The standards outlined here are only design and analysis standards as part of test and measurement, which will ultimately aid simulation in field solvers. When you’re ready to create your PCB with the test structures shown here, the advanced PCB layout utilities you’ll find in Altium Designer® can be used to create accurate test structures for high speed PCBs. You’ll also be able to quickly prepare your boards for manufacturing and assembly. Once you’ve created your board or test coupon with IEEE P370 compliant test structures, you can share your design data on the Altium 365® platform, giving you an easy way to work with a remote team and manage your design data. We have only scratched the surface of what is Try Altium Designer Thank you, you are now subscribed to updates. Get Altium Designer for free for 2 weeks Get Altium Designer for free for 2 weeks possible to do with Altium Designer on Altium 365. You can check the product page for a more in-depth feature description or one of the OnGet Altium Designer for free for 2 weeks Demand Webinars. Sign In High-Speed Design Acknowledging Altium’s Privacy Policy, I consent that Altium processes my Personal Data to send me communications, including for marketing purposes, via email and to contact me by phone. What is High Speed Design? High Speed PCB Layout Intro to High-Speed Design (Webinar) Transmission Lines and Terminations Key Elements of High-Speed PCB Design High-Speed PCB Design PCB Layout & High Speed Design using Altium Designer About Author Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2000+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators. More content by Zachariah Peterson RELATED RESOURCES Guide to Low-Dk PCB Materials Low-Dk PCB materials are often recommended for highspeed PCB design, but do you always need these? We’ll examine this question. Read Article How to Use SFP Connectors in Your PCB Layout Engineering a Layer Stack Up for High Speed Design DDR5 vs. DDR6: Here's What to Expect in RAM Modules SFP connectors are used to route data into fiber optic transceiver modules, which are normally found in highspeed networking Read Article equipment. Today, however, I’ve had multiple design requests that involve the use of fiber transceivers outside of a data center environment. Newer systems in sensor fusion, MIMO systems, rugged OpenVPX switches, and some industrial robotics need to stream huge amounts of data back to a workstation or server, with data Most of your board's simpler EMI/EMC problems, signal integrity problems, and power integrity problems can be solved Read Articleor reduced with the right layer stackup. In highspeed PCB design and in RF PCB design, the layer stackup is the first place to start engineering the board to ensure it will operate within the intended operational parameters. But like any engineered component, a high-speed layer stackup must balance many functional goals, as well What can designers expect in DDR5 vs DDR6 RAM? Here’s what you can expect for your next memory device. Try Altium Designer Thank you, you are now subscribed to updates. Get Altium Designer for free for 2 weeks Read Article Get Altium Designer for free for 2 weeks RELATED TECHNICAL DOCUMENTATION Get Altium Designer for free for 2 weeks Sign In High-Speed Design Using the Signal Using the PDN Analyzer Working with a SPICE Working with the Integrity Panel to Drive Panel to Drive PDN Netlist in Altium Simulation UI in Altium SI Analysis in Altium Analysis in Altium Designer Designer Acknowledging Altium’s Privacy Policy, I consent that Altium processes my Personal Data to send me communications, including for marketing purposes, via email and NEXUS NEXUS This page looks at the user to contact me by phone. This page details the Signal Integrity panel, used to perform SI analysis on a design. Read Documentation Use to screen all nets in a design against defined signal integrity rules, to identify problem nets. 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