# Op Amp Design

```Figure 13.1 The basic two-stage CMOS op-amp
configuration.
Figure 13.8 Bias circuit for the CMOS op amp. Note that Q8
is the same Q8 in the circuit of Fig. 13.1.
Op Amp Design Procedure v.1
All transistors are operated at the same VOV and gm6 = 5gm1
1) Choose a “good” ππππππ value that satisfies the gain and slew rate specifications,
by using these two expressions: ππππππππ =
πππ΄π΄
ππππππ
ππππππ ππππ = 2ππππ‘π‘ ππππππ
2) Assuming infinite value for fZ, use the PM to choose a “good” value for fP2,
and use fP2 to find gm6
3) Calculate the value of gm1 (= 0.2gm6) and use this together with πππ‘π‘ to find CC
4) Use the values of the transconductances overvoltage gm and ππππππ to find the
currents ID of transistors M1 – M8, and use the currents (together with ππππππ )
to find the sizes (W/L) of transistors M1 – M8
5) Check to make sure your results agree with [(W/L)6/(W/L)4] =2[(W/L)7/(W/L)5]
6) Use the expressions in your textbook to find ranges of VICM and VOUT, and the
values of the CMRR, and the PSRR7) Find the dc power dissipation from Pdiss = ITOT.(VDD+VSS) where ITOT = ID8+ID5+ID7
For the design of the bias circuit you may NOT assume that all transistors
are operated at the same overvoltage! To design the bias circuit, follow the
method described in exercise D13.8 below:
See solution on next page
Exercise 13–2
gm13 = gm8 = 0.6 mA/V
(b) From Eq. (13.34), we have
R=
gm12 =
1
1
=
= 500 Gm2
2 &times; 10−3
=
(c) From Eq. (13.35), we have
fP2 =
2μn Cox &times; 4(W/L)13 IREF
= 2gm13 = 1.2 mA/V
Gm2
2π C2
Now,
−3
2 &times; 10
=
= 318 MHz
2π &times; 1 &times; 10−12
φP2 = −tan−1
2
RB = √
2μn Cox (W/L)12 IREF
ft
fP2
=
100
318
= −tan−1
2μn Cox (W/L)12 IREF
(W/L)12
−1
(W/L)13
√
2
( 4 − 1)
−3
1.2 &times; 10
= 1.67 k
= −17.4β¦
From Example 9.6, we have
PM = 90 − 17.4 = 72.6β¦
VDD = VSS = 2.5 V
IREF = 90 μA
Ex: 13.6 Using Eq. (13.47), we obtain
Vtn = 0.7 V
SR = VOV 1 ωt
|Vtp | = 0.8 V
= 0.2 &times; 2π &times; 100 &times; 106
|VOV 8 | = 0.3 V
= 126 V/μs
IREF RB = 0.09 &times; 1.67
Using Eq. (13.45),
= 150 mV
SR =
Since
I
CC
gm13 =
−12
⇒ I = 126 &times; 10 &times; 1.6 &times; 10
6
= 200 μA
0.6 =
2IREF
VOV 13
2 &times; 0.09
VOV 13
⇒ VOV 13 = 0.3 V
Ex: 13.7
2
RB = √
2μn Cox (W/L)12 IREF
=
√
2
2 &times; 90 &times; 10−6 &times; 80 &times; 10 &times; 10−6
= 5.27 k
Using Eq. (13.61), we obtain
2
(W/L)12
−1
gm12 =
RB
(W/L)13
80
2
−1
=
5.27
20
= 0.379 mA/V
=
8
40
0.8
gm8 = 0.6 mA/V
80
−1
20
VGS13 = 0.3 + 0.7 = 1 V
VG13 = −VSS + VGS13
= −2.5 + 1 = −1.5 V
VGS11 = VGS13 = 1 V
VG11 = VG13 + VGS11
= −1.5 + 1 = −0.5 V
VSG8 = |Vtp | + |VOV 8 |
= 0.8 + 0.3 = 1.1 V
VG8 = VDD − VSG8
= 2.5 − 1.1 = +1.4 V
Ex: 13.9 Total bias current = 300 μA = 2IB
Ex: 13.8 From Example 9.6, Q8 has
W
L
(W/L)12
−1
(W/L)13
⇒ IB = 150 μA
IB = ID1 + ID3
150 = ID1 + 0.25ID1
⇒ ID1 = 120 μA
SEDRA-ISM: “E-CH13” — 2015/1/13 — 11:48 — PAGE 2 — #2
Op Amp Design Procedure v.2
It is assumed that the following quantities are given: dc gain Av, unity-gain
frequency ft, input voltage common-mode VICM range, output voltage range VOUT,
load capacitance CL (= C2), slew rate SR, and power dissipation Pdiss.
1. Assuming z1 = 10ft, and a phase margin 75o, it can be shown that Cc ≥ 0.61C2
and gm6 = 10 gm2. (See if you can prove this ππ!)
2. Choose a “good” value for Cc that satisfies Cc ≥ 0.61C2.
3. Determine current I from I = (SR).(Cc).
4. Use (VICM)min to get VOV3,4, then gm3,4 and (W/L)3,4.
5. Calculate the value of gm1 = (2πft).(Cc). Use gm1 to get VOV1, then (W/L)1,2.
6. Use (VICM)max to get VOV5 and use this to get (W/L)5.
7. From (1) above, gm6 = 10 gm1,2. From current mirror Q3-Q4-Q6,VOV6 = VOV3,4.
Use gm6, gm4 and (W/L)4 to get (W/L)6 = (W/L)4 (gm6/gm4)
8. (W/L)7 = (W/L)5 (I7/I5) where I7 = I6.
9. Check to make sure your results agree with [(W/L)6/(W/L)4] =2[(W/L)7/(W/L)5]
10. Check if the power dissipation Pdiss = (I8 +I5 + I7)(VDD + VSS) and the
gain = gm1(ro2βro4)gm6(ro6βro7) specifications are met.
10. If gain specification is not met, increase all (W/L) values by the same factor,
remembering that larger L means larger gain.
11. Use the expressions in your textbook to find ranges of VICM and VOUT, and
the values of the CMRR, and the PSRR-.
12. Verify and “fine-tune” your design by spice simulations.
To design the bias circuit, follow the method described in exercise D13.8 below:
See solution on next page
Exercise 13–2
gm13 = gm8 = 0.6 mA/V
(b) From Eq. (13.34), we have
R=
gm12 =
1
1
=
= 500 Gm2
2 &times; 10−3
=
(c) From Eq. (13.35), we have
fP2 =
2μn Cox &times; 4(W/L)13 IREF
= 2gm13 = 1.2 mA/V
Gm2
2π C2
Now,
−3
2 &times; 10
=
= 318 MHz
2π &times; 1 &times; 10−12
φP2 = −tan−1
2
RB = √
2μn Cox (W/L)12 IREF
ft
fP2
=
100
318
= −tan−1
2μn Cox (W/L)12 IREF
(W/L)12
−1
(W/L)13
√
2
( 4 − 1)
−3
1.2 &times; 10
= 1.67 k
= −17.4β¦
From Example 9.6, we have
PM = 90 − 17.4 = 72.6β¦
VDD = VSS = 2.5 V
IREF = 90 μA
Ex: 13.6 Using Eq. (13.47), we obtain
Vtn = 0.7 V
SR = VOV 1 ωt
|Vtp | = 0.8 V
= 0.2 &times; 2π &times; 100 &times; 106
|VOV 8 | = 0.3 V
= 126 V/μs
IREF RB = 0.09 &times; 1.67
Using Eq. (13.45),
= 150 mV
SR =
Since
I
CC
gm13 =
−12
⇒ I = 126 &times; 10 &times; 1.6 &times; 10
6
= 200 μA
0.6 =
2IREF
VOV 13
2 &times; 0.09
VOV 13
⇒ VOV 13 = 0.3 V
Ex: 13.7
2
RB = √
2μn Cox (W/L)12 IREF
=
√
2
2 &times; 90 &times; 10−6 &times; 80 &times; 10 &times; 10−6
= 5.27 k
Using Eq. (13.61), we obtain
2
(W/L)12
−1
gm12 =
RB
(W/L)13
80
2
−1
=
5.27
20
= 0.379 mA/V
=
8
40
0.8
gm8 = 0.6 mA/V
80
−1
20
VGS13 = 0.3 + 0.7 = 1 V
VG13 = −VSS + VGS13
= −2.5 + 1 = −1.5 V
VGS11 = VGS13 = 1 V
VG11 = VG13 + VGS11
= −1.5 + 1 = −0.5 V
VSG8 = |Vtp | + |VOV 8 |
= 0.8 + 0.3 = 1.1 V
VG8 = VDD − VSG8
= 2.5 − 1.1 = +1.4 V
Ex: 13.9 Total bias current = 300 μA = 2IB
Ex: 13.8 From Example 9.6, Q8 has
W
L
(W/L)12
−1
(W/L)13
⇒ IB = 150 μA
IB = ID1 + ID3
150 = ID1 + 0.25ID1
⇒ ID1 = 120 μA
SEDRA-ISM: “E-CH13” — 2015/1/13 — 11:48 — PAGE 2 — #2
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