University of Southern California
Department of Electrical Engineering - Systems
EE 477 Laboratory #1A Combinational Logic Design
Due 10/22/21 5:00 PM Via the D2L Online Assignment Function (100 points, worth 5% of
final grade. 1B will be assigned early, in a week and will be due 10/29/21). You will have 2
weeks to complete both labs, not including the fall recess.
YOU MUST WORK INDEPENDENTLY ON THE LABS: THERE ARE NO PROJECT
GROUPS. Do not work together.
Part A: Combinational Circuit Design and Simulation
A.1. COMBINATIONAL CIRCUIT DESIGN: Use CADENCE Virtuoso schematic capture
to design complementary CMOS logic gates at the transistor circuit level for the following
functions:
1.
2.
3.
4.
3 inverters,
transmission gate,
2-input NAND, and
a compound gate that implements the function
COMPOUT = NOT {[(A+B+C)*(D+E+F)]*(G+H)}
You will not do layout of these gates until Lab 2.
SIZING RULES:
Your lab technology lambda is 100 nm. Assume Vdd = 1.8v. For your schematic and
layout you must make the transistor dimensions in multiples of .5 lambda. Include all
transistor sizes in your report. Other parameters like thresholds and k’s might be
different from those used in lectures and homework.
A. The Basic Inverter #1: The NMOS transistors in the inverter should be 400nm
wide and 200nm long, and the PMOS transistors should be sized so that PMOS
channel resistance is about the same as the NMOS channel resistance, according to
your calculations and experiments.
1. B. The Larger Inverter #2: Size both the transistors in this inverter 4 times as
wide as in the basic inverter transistors. Remember that you can put two or more
unit-sized transistors in parallel in place of widening a single transistor if it helps
keep your methodology consistent.
C. The Largest Inverter #3: Size both the transistors in this inverter 4 times as
wide as Inverter #2. For inverter #3, experimentally perform a rough estimate for
transistor k (beta) ratio by looking at rise and fall times and taking transistor sizes
into account.
D. The Transmission gates: Size the transistors the same as the inverter #1
transistors.
E. The NAND gates: For the 2-input NAND gate, use the same size NMOS
transistors as the first inverter and make the PMOS transistors wide enough to have
rise and fall times within 1.5x each other in the worst case. In other words, rise
time < 2 x fall time or fall time < 1.5x rise time.
F. The compound gate: For the compound gate, experiment with transistor
widths that give output rise and fall times within 2 x each other, in the worst
case. Note that the sequence of inputs that give worst-case timing might be
different from the required input sequences specified below. Note also that when
you have adjusted the critical path, other paths may need adjustment as
well. Worst-case timing and critical paths will be discussed in class. You can
manipulate the Boolean equation as desired. Include your choice of worst-case
path in your discussion.
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A.2. CIRCUIT SIMULATION: a) Simulate your transistor circuits (Cadence circuits)
using SPECTRE to determine that they function properly, and to obtain information for device
sizing as described above.
SIMULATION RULES:
Rule 1: Label your inputs A, B, C and so on. For example, the 2-input gates have inputs A
and B. Label your outputs INV1OUT, NAND2OUT, etc.
Rule 2: Attach your inverter #1 design to the output of each gate (including the
inverter) prior to simulation to provide a load capacitance. The output you should plot
is the input to this load inverter.
Rule 3: Simulation timing: Assume .05ns rise and fall time for your inputs. Hold all input
values stable for at least 1.8ns.
Rule 4: Show simulations of each gate (including the transmission gate) except compound
gate with all possible combinations of inputs.
Rule 5: Simulate the gates, and change the inputs in the following manner:
a) Inverters: Start with input low then raise then lower again. Also plot input
vs. output as an input/output transfer curve (TA will tell you how to do this).
b) For Inverter #1, change the sizing of the devices to move point C to the right.
Show the resulting input/output transfer curve. (you might have to make a
big change to see a difference).
c) 2-input NAND: For the 2-input gates AB = 00, AB = 01, etc.
d) Compound gate: For the compound gate, simulate all combinations of A, B,
C and D from 000 to 111, counting up in binary 0000, 0001, 0010, etc. ,
while holding E=1 and all other inputs to 0.
e) In another test for the compound gate, hold ABC=010 and DEF to 110,
while holding all other inputs 0, and then change G and H from 0 to 1.
f) For the transmission gate, simulate the input and control signal in the
following order: 00, 01, 10, 11.
Please change the inputs in the order given so that we can grade what you are
doing easily.
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LAB REPORT CONTENTS
Submit your lab report. The lab report is worth 20% of the Lab 1 grade.
Your lab report should be a .pdf file. Please do not submit a .doc or .docx file. Name
the report as follows: LastnameLab1.pdf
Lab Report Contents (in order):
1. Title page with your name, date you submitted the lab, title, and student number.
2. Transistor schematics (circuit diagrams) of gates taken from Cadence. Submit
your final schematic images without the load inverter attached to the output.
3. Discussion and explanation of how you sized transistors, including measured rise
and fall times.
4. SPECTRE input and output waveforms for each gate schematic transient
simulation in the form of images showing the waveforms.
5. Images of the Vout-Vin transfer curve for the inverters and results of the current
computations.
6. Conclusions about the lab, especially about sizing the transistors in the compound
gate.
Make sure that any images you use are readable and we can zoom in to see details without
excessive pixellation. Use the "tar function" on UNIX or the Zip function to put all the files
including the report into a single file. Do not put into rar format. Students submitting
multiple files will lose points. Your reports must be in pdf format and zipped with the
other files.
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Instructions on how to print your waveform images in color:
To get pictures from Cadence in your report:
For schematics: Use File-->Export Image. Enter a name and save as PNG
For waveforms: Please click on them, otherwise they are very hard to see.
File -> Save Image -> Image Options -> Create exact copy of window
Then enter a name and save in PNG format.
Some Guidance from the previous TAs:
Please be sure to use alphabetic characters to begin signal names. Cadence might have trouble
with names like /A or 3A.
Cadence is case sensitive. Case sensitive means that the labels in your schematic should be
consistent with the labels in your layout. For example, if in my schematic I use A for the input of
the inverter then in the layout I should use A for the input of the layout inverter (If I use a instead
of A it won’t work).
************ Rise/Fall time
There is an option in the rise time window that allows you to measure all the rise times in a
simulation. It is the # of occurrences. The default is “single”, you can change it. If you can't
compute the rise time or fall time using the calculator function, you can always measure it
manually. It will take some practice until you get used to managing the calculator.
Good luck!