# 博士班資格考 超大型積體電路系統設計 (15%) Sketch a 3

## 超大型積體電路系統設計

1.

(15%)

Sketch a 3-input NOR gate with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter. Compute the rising and falling propagation delays of the NOR gate driving h identical NOR gates using the

Elmore delay model. Assume that every source or drain has fully contacted diffusion when making your estimate of capacitance.



(20%)

An output pad contains a chain of successively larger inverters to drive the relatively enormous off-chip capacitance. If the first inverter in the chain has an input capacitance of 20 fF and the off-chip load is 10 pF, how many inverters should be used to drive the load with least delay? Estimate this delay, expressed in

FO4 inverter delays.

3.

(15%)

(a) (5%) Sometimes the substrate is connected to a voltage called the substrate bias to alter the threshold of the nMOS transistors. If the threshold of an nMOS transistor is to be raised, should a positive or negative substrate bias be used?

(b) (5%) A 90 nm long transistor has a gate oxide thickness of 16

Å

. What is its gate capacitance per micron of width?

(c) (5%) Does the body effect of a process limit the number of transistors that can be placed in series in a CMOS gate at low frequency? Why?

4. (15%)

(a) (5%) Sketch HI-skew and LO-skew 3-input NAND and NOR gates. What are the logical efforts of each gate on its critical transition?

(b) (5%) Design an asymmetric 3-input NOR gate that favors a critical input over the other two. Choose transistor sizes so the logical effort on the critical input is 1.5.

What is the logical effort of the noncritical inputs?

(c) (5%) Sketch dynamic footed and unfooted 3-input NAND and NOR gates.

Label the transistor widths. What is the logical effort of each gate?

5. (15%)

(a) (3%) What are power rails?

(b) (3%) What does the term weak ‘ 1’ mean?

(c) (3%) Please draw a CMOS negative-edge-triggered D flip-flop using transmission gates and inverters.

(d) (3%) What is the self-aligned process?

(e) (3%) Why do we need layout design rules for IC design?

6. (20%)

Consider a 5 mm long, 4

-wide metal2 wire in a 0.6

 m process. The sheet resistance is 0.08

/ □ and the capacitance is 0.2 fF/

 m. A 10x unit-sized inverter drives a 2x inverter at the end of the 5 mm wire. The gate capacitance is C =2 fF/

 m and the effective resistance is R =2.5 k

 ·  m for nMOS transistors. Estimate the propagation delay using the Elmore delay model; neglect diffusion capacitance.