1. Addressing memory on Intel 8086.
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Address bus: 20 bits, which mean the hardware is limited to 220 𝑏𝑖𝑡𝑠 = 1𝑀𝐵
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Register size is 16 bits
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Effective address and segmentation of memory.
2. Memory segmentation.
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A segment is just an area in memory.
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The total memory (RAM) is divided into segments of various sizes.
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The process of dividing memory into different segments is called
segmentation: Code, data, stack, extra.
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These registers are 16-bit in size.
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Each register stores the base address (starting address) of the corresponding
segment.
3. Effective address.
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The 20-bit address of byte is called its effective address (physical address)
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It is specified as a logical address.
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Logical address is in the form of: Base: Offset.
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8086 uses 2 registers to form the effective 20-bit address.
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One of these registers is one of segment register (CS, DS, SS, ES) and the
other is called the offset register.
4. Architectural model of 8086.
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Instructions are stored in RAM & must be fetched.
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Then decoded into micro instructions.
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Then executed using ALU.
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Results are written either to register or to RAM.
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The 8086 CPU is divided into two independent functional parts: the bus
interface unit (BIU) and the execution unit (EU).
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Bus Interface Unit.
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BIU fetches instruction codes.
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It stores fetched instruction codes in a FIFO register called QUEUE.
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It handles transfer of data and addresses between the processor and
memory/IO on the buses.
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It reads data from memory and I/O devices.
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It writes data to memory and I/O devices.
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It computes and sends out addresses.
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BIU contains:
 Segment register (CS, DS, SS, ES) – A segment points to the starting
address of a memory segment (Ex: the code segment register points to
the starting address of the code segment). The maximum capacity of a
segment may be up to 64KB.
 Instruction pointer: points to the address (offset) of the next
instruction to be executed. Its content is automatically incremented
when the execution of a program proceeds further. The contents of the
IP and code segment register are used to compute the memory address
of the instruction code to be fetched. This is done during the fetch
cycle.
 6-byte instruction queue.
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Execution Unit (EU)
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The execution unit is responsible for decoding and executing all the
instructions.
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It receives opcode of an instruction from the QUEUE.
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It decodes it and then executes it.
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It tells BIU where to fetch the instructions or data from.
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It has 16-bit ALU, which can perform arithmetic and logical operations on
8-bit as well as 16-bit data.
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Execution unit contains: general purpose registers, stack pointer, base
pointer, index registers, ALU, flag register, instruction decoder, timing &
control unit.