1. What do you understand by a 16 bit microprocessor? Give examples
In computer architecture, 16-bit integers, memory addresses, or other data units are those that are 16
bits or 2 bytes wide. Likewise, 16-cycle CPU and ALU architectures are those that depend on registers,
address transports, or information transports of that size. 16-cycle microcomputers are computers in
which 16-bit microprocessors were the standard. A 16 bit processor- memory locations can
straightforwardly get to 64 KB (65,536 bytes) of byte-addressable memory.
Example : Intel 8086, Zilog Z8000
Extra info :
https://www.chegg.com/homework-help/questions-and-answers/understand-bus-system-computer-briefly-describeunderstand-address-bus-data-bus-control-bu-q93594606?trackid=sLcPU7RU
2. Mention the sizes of address and data buses of 8086 and 8088 microprocessors and comment
on their importance/significance? Also comment on their impacts on processors’
performance.
Ans:
8086 Address Bus 20-bit & Data Bus 16-bit
8088 Address Bus 20-bit & Data Bus 8-bit
Both can access 1MB of memory.
8088 is very much similar 8086. The EU is same but BIU is slightly different.
8086 can read/write 8/16-bit data at a time. But 8088 can only do so for 8-bit data
The Instruction Queue of 8086 is 6-bit long and that of 8088 is 4-bit long
So, 8088 will see some performance downgrade when the instruction will be longer.
3. What do you understand by instruction fetch? List the steps involved in instruction fetch.
Ans:
A program runs with many instructions. But for that CPU has to fetch instruction from ram.
Instruction fetching means reading the program instruction so that the cpu knows what or what
not to do. Which is usually in 1 and 0. There are few steps involved in fetching instructions,
Step 1 : The address of the next instruction to be executed is in the Program Counter(PC).
Step 2: The address in the program counter is moved to the memory address register (MAR)
Step 3: The address in MAR is placed on the address bus, now the control unit issues a READ
command on the control bus, and the result appears on the data bus and is then copied into the
memory buffer register(MBR). Program counter is incremented by one, to get ready for the next
instruction.
Step 4: The content of the MBR is moved to the instruction register(IR).
Thus a simple fetch cycles completes.
4. What do you understand by bus system of computer, briefly describe.
Ans:
A bus system is an electrically connected path between major components of a computer which is
used to transfer data. The bus gives a correspondence way to the information and control signals
moving between the significant parts of the computer system. The system bus works by consolidating
the elements of the three primary buses: to be specific, the information, address, and control buses.
Every one of the three buses has its different attributes and obligations.
The system bus consolidates the elements of the three fundamental buses, which are as per the
following:
The control bus conveys the control, timing, and coordination signs to deal with the different
capacities across the system.
The address bus is utilized to determine memory areas for the information being moved.
The information bus, which is a bidirectional way, conveys the real information between the
processor, the memory, and the peripherals.
5. What do you understand by Address bus, data bus and control bus? State the function,
significance and direction of signal flow for each.
Ans:
Address bus carries the to location where it should be stored. Address bus is a part of the computer
system bus that is dedicated for specifying a physical address. Address bus is unidirectional.
A data bus simply carries data. Data Bus is used for both read/write operations. The data bus is
bidirectional bus, means the data can be transferred from CPU to main memory and vice versa.
The data transport is bidirectional in light of the fact that data stream in the two bearings, from the
microprocessor to memory or I/O
The control bus conveys the control, timing, and coordination signs to deal with the different
capacities across the system. The control transport is unidirectional.
In Simple term :
 Data Bus: Carries the data that needs processing
 Address Bus: Determines where data should be sent
 Control Bus: Determines data processing
6. What do you understand by register? How does it affect the performance of a processor?
Ans:
https://www.chegg.com/homework-help/questions-and-answers/understand-register-affect-performanceprocessor-define-stack-ii-program-counter-iii-index-q93559797?trackid=fYJIqk07
7. What do you understand by clock cycle/clock speed of a microprocessor?
Ans:
https://www.chegg.com/homework-help/questions-and-answers/understand-register-affectperformance-processor-define-stack-ii-program-counter-iii-index-q93559797?trackid=fYJIqk07
8. What do you understand by Bus cycle of a processor? How it is related to processor’s clock
cycle?
Ans:
https://www.chegg.com/homework-help/questions-and-answers/understand-register-affect-performanceprocessor-define-stack-ii-program-counter-iii-index-q93559797?trackid=fYJIqk07
9. List CPU registers within execution unit and state their special/default uses in assembly
language programming.
Ans:
Registers in EU

4 General purpose registers -(AX, BX, CX, DX);
Each of these is a combination of two 8-bit registers which are separately accessible as
AL, BL, CL, DL (the "low'' bytes) and AH, BH, CH, and DH (the "high'' bytes).
1. AX register:
It holds operands and results during multiplication and division operations. Also
an accumulator during String operations.
2. BX register:
It holds the memory address (offset address) in indirect addressing modes.
3. CX register:
It holds count for instructions like loop, rotate, shift and string operations.
4. DX register:
It is used with AX to hold 32 bit values during multiplication and division.

4 Special purpose registers
1. Stack Pointer:
Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH, POP,
CALL, RET etc.
2. Base Pointer:
BP can hold offset address of any location in the stack segment. It is used to access
random locations of the stack.
3. Source Index:
It holds offset address in Data Segment during string operations.
4. Destination Index:
It holds offset address in Extra Segment during string operations.
 Flag/Status Register (16 bits).
It has 9 flags that help change or recognize the state of the microprocessor.
6 Status Flag & 3 Control FLags
10. List CPU registers within BIU and state their special/default uses in assembly language
programming.
Ans:
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a prefetch queue and an
Address Generation Circuit.
4 Segment registers:
1. Code Segment register:
CS holds the base address for the Code Segment. All programs are stored in the Code
Segment and accessed via the IP.
2. Data Segment register:
DS holds the base address for the Data Segment.
3. Stack Segment register:
SS holds the base address for the Stack Segment.
4. Extra Segment register:
ES holds the base address for the Extra Segment.
Instruction Pointer (IP):
It is a 16 bit register. It holds offset of the next instructions in the Code Segment.
11. What is flag register? Briefly describe the functions of each flag bit of 8086.
Ans:
The Flag register is a Special Purpose Register. Depending upon the value of result after any
arithmetic and logical operation the flag bits become set (1) or reset (0).
There are total 9 flags in 8086 and the flag register is divided into two types:
6 Status flags:
1. carry flag(CF) - This flag is set, when there is a carry out of MSB in case of addition or a borrow
in case of subtraction.
2. parity flag(PF) - This flag is set to 1, if the lower byte of the result contains even number of 1’s ;
for odd number of 1’s set to zero.
3. auxiliary carry flag(AF) - Half-carry between bits 3 and 4, used with BCD arithmetic.
4. zero flag(Z) - This flag is set to 1 when result is zero. For non-zero result this flag is set to 0.
5. sign flag(S) – This flag set to 1 when result is negative. When result is positive it is set to 0. (This
flag takes the value of the most significant bit.)
6. overflow flag (O) - This flag is set, when the result of a signed operation is large enough to
accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16- bit sign operations, then the overflow
will be set.
3 Control flags:
1. Trap flag(TF)- - Turns trapping interrupt (for program debugging) on/off
2. Interrupt flag(IF) - Causes the 8086 to recognize external mask interrupts; clearing IF disables
these interrupts.
3. Direction flag(DF) - This flag is specifically used in string instructions. If DF is set (1), then access
the string data from higher memory location towards lower memory location.If DF is reset (0),
then access the string data from lower memory location towards higher memory location.
12. State the functions of control flag bits? List some instructions used to set/reset the control
flag bits.
Ans:
Among total 9 flags in 8086, there are 3 Control Flag registers. This flags are used to enable
or disable some basic operations of the microprocessor.
1. Trap flag(TF)
2. Interrupt flag(IF)
3. Direction flag(DF)
Flag Bits
T
I
D
Functions
This trap flag is used for on-chip debugging. When T = 1, it will work in a single step
mode. After each instruction, one internal interrupt is generated. It helps to execute
some program instruction by instruction.
This is interrupt flag. If I = 1, then MPU will recognize the interrupts from peripherals.
For I = 0, the interrupts will be ignored
This flag is specifically used in string instructions. If D =1 then access the string data
from higher memory location towards lower memory location. If D=0 then access the
string data from lower memory location towards higher memory location.
13. State the significance of flag register and flag bits? How/why these are used in programs.
Ans:
The flag register is one of the specific purpose registers. The flag bits are changed to 0 or 1 relying
on the worth of result after number-crunching or sensible activities.
8086 has a 16-bit flag register, and there are 9 substantial flag bits. These flags are further divided
into two categories
1)Status Flag - In 8086 there are 6 unique flags that are set or reset after 8-digit or 16-bit operations
bits
2)Control Flags - In 8086 there are 3 unique flags that are utilized to empower or handicap a few
fundamental tasks of the chip.
The flag register is the status register that contains the present status of a CPU. The size and
implications of the flag bits are engineering subordinate. It as a rule mirrors the consequence of
number-crunching activities as well as data about limitations put on the CPU activity at the current
time.
14. Describe how the 8086/8088 calculates memory addresses. Give example.
Ans:
8086 has a 20bit location line. So the greatest worth of address that can be tended to by 8086 is 2^20
= 1MB. 8086 has an idea of Memory Segmentation. It is a technique where the entire memory is
sectioned into more modest parts called portions. For memory address calculation:




Step-1: Segment must be specified and segment register (CS/SS/DS/ES) should be specified
accordingly.
Step-2: Source of OFFSET/Logical address should be specified based on Segment.
Step-3: Base Address/Starting Address of Segment is formed by converting the 16 bit contents
into 20 bits(4 digits in Hex) by adding 4 zeros (a zero in Hex)to the right to the contents of
segment register.
-Example: CS = [1000H]
-Base address = 10000H
Step-4: OFFSET/Logical address is added to Base address to form the Physical address
Example: IP= [500H]
Physical address = 10000H + 500H = 10500H
15. List the registers and other parts in the 8086/8088 execution and bus interface unit.
Ans:
Registers in EU



General purpose registers -(AX, BX, CX, DX);
Special purpose registers
- Stack Pointer, Base Pointer, Source Index, Destination Index
Flag/Status Register.
Other parts of EU


ALU
Instruction Register and Instruction Decoder
Regsiter used in BIU are



CS - Code Segment register
DS - Data segment register
SS - Stack segment register

ES - Extra segment register
Other parts of BIU –



Instruction Pointer
Prefetch queue
Address Generation Circuit
16. Describe the function of the 8086 instruction queue. State its benefits. Also indicate its
possible drawback, if any.
Ans:
The Instruction Queue:
The execution unit (EU) is supposed to decode or execute an instruction. When EU is busy in decoding
and executing an instruction, the BIU fetches up to six instruction bytes for the next instructions. These
bytes are called as the pre-fetched bytes and they are stored in a first in first out (FIFO) register set,
which is called as a queue.
The fetching of opcodes well in advance, prior to their need for execution increases the overall
efficiency of the processor boosting its speed. The processor no longer has to wait for the memory
access operations for the subsequent instruction opcode to complete.
Instruction queue is 6 bytes so that it can store the longest instruction.
Benefit :-The processor no longer has to wait for the memory access operations for the subsequent
instruction opcode to complete.
Drawbacks:
Here, first process will get the CPU first, other processes can get CPU only after the current
process has finished it’s execution. Now, suppose the first process has large burst time, and other
processes have less burst time, then the processes will have to wait more unnecessarily, this will
result in more average waiting time
17. What do you understand by pipelining? What is its advantage?
OR What is pipelining and how it improves performance?
Ans:
Pipelining is an implementation technique where multiple instructions are overlapped in execution.
The computer pipeline is divided in stages. Each stage completes a part of an instruction in parallel.
The stages are connected one to the next to form a pipe - instructions enter at one end, progress
through the stages, and exit at the other end.
Advantages of pipelinings :-Advantage: Lets assume that BIU and EU units require 5 seconds each for Fetch and Execution of
each instruction. So processing of each instruction requires: 5 + 5 = 10 seconds. In a non-pipelined
processor, processing of 500 instructions would require: 500 X 10 = 5,000 seconds.
In a pipelined processor, to get the output of 1st instruction, we have to wait for 10 seconds. For the
remaining instructions, we get outputs after each 5 seconds! So the processing of 500 instructions
would require:
10 sec (for 1st instructions) + 499 X 5; (remaining instructions 500-1 X 5 seconds) = 2505 Seconds
In short pipelining eliminates the waiting time of EU and speeds up the processing.
So we can see the speed up factor is almost doubled.
18. How does 8086 microprocessor calculate physical addresses of memory locations within code
segment and stack?
Ans:
8086 has a 20bit location line. So the greatest worth of address that can be tended to by 8086 is 2^20
= 1MB. 8086 has an idea of Memory Segmentation. It is a technique where the entire memory is
sectioned into more modest parts called portions. For memory address calculation:




Step-1: Segment must be specified and segment register (CS/SS/DS/ES) should be specified
accordingly.
Step-2: Source of OFFSET/Logical address should be specified based on Segment.
Step-3: Base Address/Starting Address of Segment is formed by converting the 16 bit contents
into 20 bits(4 digits in Hex) by adding 4 zeros (a zero in Hex)to the right to the contents of
segment register.
-Example: CS = [1000H]
-Base address = 10000H
Step-4: OFFSET/Logical address is added to Base address to form the Physical address
Example: IP= [500H]
Physical address = 10000H + 500H = 10500H
The 20-bit physical stack address is calculated from the Stack Segment (SS) and the Stack Pointer
(SP) for stack instructions such as PUSH and POP.
19. What is IP? What is its function?
Ans:
IP stands for Instruction Pointer, it is a part of BIU. To get to directions the 8086 uses the registers
CS and IP. It is a 16 bit register. It holds offset of the next instructions in the Code Segment. IP is
incremented after every instruction byte is fetched. IP gets a new value whenever a branch
instruction occurs. The Address of the next instruction is calculated as CS x 10H + IP.
20. State the number of stages of pipelining used in 8086. How does it affect the CPU
performance?
Ans:
It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves
performance. Fetch stage can prefetch up to 6 bytes of instructions and stores them in the
queue. Execute stage executes these instructions. Each stage completes a part of an instruction
in parallel. For this technique the processor performance increases almost double.
21. State the benefits of memory segmentation technique used in 8086/8088.
Ans:

Programs use offsets as logical address, independent of where segments are located
(relocatable)
• Allows easy and efficient relocation of code and data.
• To relocate code or data, only the number in the relevant segment register needs to be
changed.
22. List the segment registers and default registers used to hold offset addresses in memory
address calculation. Also mention purpose for each case.
Ans:
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers called as Segment
Registers.
The following below are the segment registers:

Code segment register (CS): is used for addressing memory location in the code segment
of the memory, where the executable program is stored.

Data segment register (DS): points to the data segment of the memory where the data is
stored.

Extra Segment Register (ES): also refers to a segment in the memory which is another
data segment in the memory.

Stack Segment Register (SS): is used for addressing stack segment of the memory. The
stack segment is that segment of memory which is used to store stack data.
The list of default registers or the general purpose registers are as follows:

AX – This is the accumulator. It is of 16 bits and is divided into two 8-bit registers AH and
AL to also perform 8-bit instructions. It is generally used for arithmetical and logical
instructions but in 8086 microprocessor it is not mandatory to have accumulator as the
destination operand.

BX – This is the base register. It is of 16 bits and is divided into two 8-bit registers BH and
BL to also perform 8-bit instructions. It is used to store the value of the offset.

CX – This is the counter register. It is of 16 bits and is divided into two 8-bit registers CH
and CL to also perform 8-bit instructions. It is used in looping and rotation.

DX – This is the data register. It is of 16 bits and is divided into two 8-bit registers DH and
DL to also perform 8-bit instructions. It is used in multiplication an input/output port
addressing.
23. What is the maximum size of a segment? How many segments can be used in a program?
Briefly state.
Ans:
Maximum size of segment can be 64 kB (Minimum size of a segment can be 16 bytes). the greatest
worth of address that can be tended to by 8086 is 2^20 = 1MB. It’s 20 bit address bus can address
1MB of memory, it segments it into 16 64kB segments. But 8086 works only with four 64KB segments
within the whole 1MB memory.
25. Given the contents of following register pairs, calculate the physical address of main memory
location pointed by each:
Calculate Physical Address of Main memory
• Given the contents of CS:IP = [3000H]:[100H]
Ans:
PA = Starting Address of CS*10H + IP
= 3000H*10H+100H
= 30100H
• Given the contents of SS:SP = [50A0H]:[300H]
Ans:
PA = Starting Address of SS*10H + SP
= 50A0H*10H+300H
= 50D00H
• Given the contents of ES:DI = [60C0H]:[200H]
Ans:
PA = Starting Address of ES*10H + DI
= 60C0H*10H+200H
= 60E00H
• Given the contents of DS:SI = [A1C0H]:[2F00H]
Ans:
PA = Starting Address of DS*10H + SI
= A1C0H*10H+2F00H
= A4B00H
• Given the contents [CS]:[IP]=[1F0AH]:[15A6H]
Ans:
PA = Starting Address of CS*10H + IP
= 1F0AH*10H+15A6H
= 20646H
• Given the contents [SS]:[SP]=[82FFH]:[0FA1H]
Ans:
PA = Starting Address of SS*10H + SP
= 82FFH*10H+0FA1H
= 83F91H
Extras:
1. What are the differences between a register and a memory location?
Ans:
Difference between a CPU register and a memory location are as follows :

Any program in execution requires operands, instructions and data. Register holds the
operands or instructions whereas memory location holds the data.

Types of register are Accumulator register, Program counter, Instruction register, Address
register, etc. types of memory are RAM , ROM.

CPU accesses memory at the slower rate than register.

Register generally can accommodate small data, of size around 32-bits to 64-bits whereas
memory of the computer ranges from some GB to TB generally.
2. For the memory location whose physical address is specified by 1256Ah, given the address
in segment: offset form for segments 1256h and 1240h. Find the offset addresses.
Ans:
As given in the problem, lets say X, Y are the offsets of segment 1256h and 1240.
Then
For X: 1256Ah = 12560h + X
So A = 000Ah
For Y: 1256Ah = 12400h + B,
So B = 016Ah
3. What is the purpose of segment register?
Ans: A segment register keeps track of which memory address matches a particular segment.
There are several types of segment registers. There are code segments (CS), data segments
(DS), stack segments (SS), and extra segments (ES).
4. Draw the internal architecture of 8086 microprocessor? Done
5. What are the functions of Interrupt, trap, and overflow register?
Ans:
Functions of Interrupt It is a control flag. This flag register is for the interrupts. If I is 1, then our operation system will
recognize there is a interrupt request from some device. but if I is 0, it will not see any request and
avoid it. (determines whether or not the CPU will respond immediately.)
Functions of Trap It is a control flag. The trap flag register enables trapping via a debugging feature. If the T flag is 1
means enabled, the microprocessor interrupts the flow of the program on conditions as indicated by
the debug registers and control registers and it will be run instruction by instruction. If the T flag is 0,
the trapping feature would be disabled. Eg. The Visual C++ debugging tool uses the trap feature and
debug registers to debug faulty software.
Functions of Overflow register It is a conditional flag. Overflows occur if there are any signed numbers being added or subtracted.
An overflow means that the result has exceeded the capacity of the machine means number of bits.
Eg., if 7FH ( +127 ) is added using an 16-bit addition to 01H ( +1 ), the result is 80H (–128) which
means overflow. It is a condition which shows there is a overflow by overflow flag for signed
operatiosn.. For unsigned operations, the overflow flag is ignore
6. Where the offset address of the CS (code segment) and SS (stack segment) remains ?
Ans:
For CS (code segment),
The offset address remains in IP (instruction pointer) and is for calculating the instruction adress.
For SS (stack segment)
The offset address remains in BP (base pointer) or SP (stack pointer) and is for calculating the
stack adress.
8. State the benefits of memory segmentation technique used in 8086/8088?
Ans:
The benefits of memory segmentation technique are:
i) It provides a strong and faster memory management mechanism.
ii) The code related operations could be easily happen in separate code segments.
iii) It lets you to extend the address ability of the processor, means segmentation lets you use
of 16 bit registers to give an addressing capability of 1 Megabytes. If it will not be there, it
would require 20 bit registers.
iv) One could easily process and share data.
v) No internal fragmentation as internally we have already allotted some area for a specific
segment, so there would be not any internal fragmentation.
9. What is memory segmentation technique?
Ans:
Memory segmentation technique is an operating system technique so that it could manage memory
by dividing computer's primary memory into some segments. It is just for increasing the speed of the
any type of execution happening in computer system. And also by this technique, process easily
fetches the data from memory.
10. What are the functions of BIU? List the register of BIU.
Ans:
BIU (bus interface unit) which take care of data and any type of address transfers on the buses like
fetching instructions, sending data, reading data from the ports as well as writing data to the ports
etc. It generates 20 bit physical address for accessing memory.
Regsiter used in BIU are
4 Segment registers:




CS - Code Segment register
DS - Data segment
SS - Stack segment
ES - Extra segment
Instruction Pointer (IP):
It is a 16 bit register. It holds offset of the next instructions in the Code Segment.
11. What is the disadvantage of segmentation technique?
Ans:
Disadvantages of segmentation technique:
i)The memory management mechanism or algorithms will be costly as obviously we are separating
the memory into segments for different purposes.
ii) Address computation delay for every memory access
iii) Software limitation: Program size limited by segment size (64KB with the 8086)
12. List the components in EU?
Ans:
The main components of the EU are,





General purpose registers -Four general purpose registers(AX, BX, CX, DX);
ALU
Special purpose registers – Special purpose registers (SP, BP, SI, DI)
Instruction Register and Instruction Decoder
Flag/Status Register.