BenADDA-16
High-Performance Data Acquisition & Processing
™
The BenADDA-16 integrates multi-channel, high speed
analog I/O with the extreme processing of an FPGA.
The DIME-II™ module combines a Xilinx® Virtex™-5 SXT or
LXT FPGA with two Linear Technology 16-bit, 180 MSPS
ADCs and a single Texas Instruments dual channel 16-bit
1GSPS DAC. Two independent banks of QDR-II SRAM
directly coupled to the Xilinx Virtex-5 FPGA are capable of
double buffering ADC data prior to processing.
The result is a high performance data acquisition and
processing platform in a proven COTS solution.
The BenADDA-16 is the ideal solution for easy, low risk
system integration or in-field deployment.
16-Bit Dual ADC & DAC Data Acquisition Module
Key features
Benefits
• DIME-II expansion module
• High-speed analog capture coupled to Xilinx FPGA
• Dual 16-bit, 180 MSPS analog capture channels
• Dual 16-bit, 1GSPS analog output channels
• External clock input and onboard high accuracy fixed
oscillator clocking options
• Onboard Xilinx Virtex-5 SXT or LXT user FPGA
• 18 MB QDR-II SRAM – 2 independent banks
Easy to implement analog and processing capability
• Commercial-off-the-shelf (COTS) hardware
Shorten time to market and reduce risk
• Compatible with multiple FPGA design flows
Select the appropriate design flow for the application
• Compatible with all Nallatech DIME-II motherboards
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The Leader in FPGA
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Accelerated Computing
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www.Nallatech.com / contact@nallatech.com
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BenADDA-16
Technical specification
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Xilinx Virtex-5 FPGA
Standard options – XC5VSX95T-2,
XC5VLX155T-2
Available on request XC5VFX100T-2
www.xilinx.com
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FPGA programming
3 programmable clock domains
driven from DIME-II motherboard
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Analog I/O
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Two analog input channels
16-bit, 180 MSPS Linear
Technology LTC2209IUP#3BCPBF
ADCs – www.linear.com
Single-ended, DC coupled
MMCX connectors
Two analog output channels
16-bit, 1 GSPS Texas Instruments
DAC5682z DAC – www.ti.com
Single-ended, DC coupled
MMCX connectors
8-pin 2mm pitch digital header for
trigger and synchronization
•• 2 differential pairs (2.5V LVDS)
• 2 single-ended (2.5V LVTTL)
• 2 ground
Additional analog configurations
available on request. Specifically:
• Differential inputs/outputs
• AC coupling
Analog clocking
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Host bandwidth
• Up to 2.2GB/s aggregate Host
bandwidth using BenONE-PCIe
• Actual performance is host
computer chipset and operating
system dependent
DIME-II buses
• Adj In : 80-bits @ 200MHz
• Adj Out : 80-bits @ 200MHz
• Local Bus : 40-bits @ 66MHz
• Plink 0 : 12-bits @ 133MHz
• Plinks 4 & 6 : 4 GTP links @
2.5Gbps
Off-module
• 2 SATA headers : 1 GTP link
per header @ 2.5Gbps
Two tri-color user LEDs
Power consumption is application
dependant.
Application development software
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Supports multiple design flows
®
including VHDL, Verilog and
®
System Generator
Compatible with all major synthesis
design flows
Compatible with Xilinx ISE
Implementation software
Supported in optional Nallatech
DIMEtalk design tool
Software
Nallatech FUSE API for runtime
FPGA programming, hardware
control, and communication
• C/C++, TCL and GUI
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XILINX VIRTEX-5
USER FPGA
P LINK 0 (12 BITS)
P LINK 6
(2* 2.5Gbps GTP)
P LINK 4
(2* 2.5Gbps GTP)
ADJ IN (80 BITS)
ADJ OUT (80 BITS)
LOCAL BUS (40 BITS)
QDR-II SRAM
QDR-II SRAM
Plinks 4 & 6 can only be used in conjunction with other Virtex-5 DIME-II
modules and are not supported on PCI-104 DIME-II motherboards
Environmental
Cooling
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FPGA active cooling fan or passive
heatsink provided for user FPGA
(specify when ordering)
Passive heatsink requires adequate
forced-air cooling
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Cooling: Air convection
Operating temperature: 0°C to 45°C
Storage temperature: -20°C to 80°C
Relative humidity: 45 to 95% (noncondensing)
Ordering and deliverables
Ordering
Deliverables
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BenADDA-16 module
Software documentation CD
QDR-II SRAM FPGA IP Core
5 MMCX coaxial cables
30 days product maintenance
• Technical support helpdesk
• Online support lounge access
Quality
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ADC
SATA
Electrical
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MMCX connector for external clock
input
External clock input via Analog
Devices AD9516-3 synthesizer
External clock input fed directly to
clock distribution section of
AD9516-3
External Clock range from 10MHz
to 1GHz
Corporate Offices
741 Flynn Road
Camarillo, CA 93012, USA
Tel: (805) 383-8997
Toll Free: 1-877-44-NALLA
Fax: (805) 384-4899
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ADC
SATA
MOTHERBOARD DIME-II
INTERCONNECT FABRIC
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LOCAL
OSC
DAC
MOTHERBOARD DIME-II
INTERCONNECT FABRIC
FPGA clocking
CLOCK
CONTROL
Digital I/O
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EXTERNAL
CLOCK
MODULE CONNECTORS
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Embedded SELECTMAP and JTAG
programming using FUSE API
software functions (motherboard
dependent)
Onboard FLASH PROM option
available upon request
18 MB QDR-II SRAM
Two independent 9 MB banks
36-bit data bus per bank
Operating frequency: 250 MHz
Max. bandwidth per bank: 4.5 GB/s
Max. total bandwidth: 9 GB/s
QDR-II SRAM controller IP core
included
MODULE CONNECTORS
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DIGITAL
TRIGGER
SRAM memory
User FPGA
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Functional diagram
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Contact Nallatech for leadtime and
pricing information.
Refer to the DIME-II Product
Ordering Guide for product order
codes
Additional options
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DIMEtalk design tool software
FUSE Toolbox for MATLAB
Manufactured to IPC610 Class II
Designed and supplied to
ISO9001:2000 certification
ROHS compliant
1 Napier Park
Cumbernauld
G68 0BH, UK
Tel: +44 (0)1236 789567
Fax: +44 (0)1236 789599
Technical specifications (e.g. FPGA type,
size, external memory capacity etc.) can be
modified to meet the exact needs of
commercial customer applications as
off-the-shelf product available to the
general market.
www.Nallatech.com / contact@nallatech.com