AN E/D NMOS TECHNOLOGY FOR
EDUCATIONAL AND MULTI-PROJECT CHIP
ACTIVITIES
Leandro T. Manera, José A. Diniz, Peter J. Tatsch and Jacobus W. Swart
DSIF/FEEC and CCS - UNICAMP, C.P.6165, CEP 13083-970 Campinas, São Paulo, Brasil
E-mail: manera@led.unicamp.br
Abstract
An enhancement and depletion (E/D) nMOS
technology for educational and multi-project chip
activities has been performed. The nMOS device
fabrication process and electrical parameter simulations
were obtained by SUPREM IV and PISCES2,
respectively. So, E/D nMOS devices, such as capacitors,
transistors and inverters, were fabricated and their
electrical parameters extracted using a HP4145B
parameter analyzer. These experimental results were
used to obtain the SPICE MOSFET level-3 static model.
The SUPREM, PISCES2 and SPICE simulations were
employed to obtain an (E/D) nMOS device design kit.
The experimental and simulated results of nMOS
transistor and inverter were compared to validate the
design kit. Based on this kit, a multi-project chip with
seven different projects was fabricated.
1. Introduction
The circuit simulation is mandatory to develop
integrated circuit projects [1-2]. Based on simulation,
circuit behavior can be extracted electrical parameters
and performance before the device fabrication, which
reduces project and re-project cycles. Process fabrication
and electrical parameter simulation softwares of
semiconductor devices, such as SUPREM, PISCES2 and
SPICE, have been used in MOS technology [1-2]. The
SUPREM-IV.GS, which models GaAs and its dopants in
addition to modeling silicon fabrication technology, is an
advanced 2D-process simulator originally developed for
submicron silicon structures [3]. PISCES-2ET is a
electrical
device
simulator
for
Silicon
and
heterostructures [4]. Orcad PSPICE 9.1 is a simulation
program that models the behavior of a circuit that
contains analog-digital devices. These programs permit
to develop a MOS device design kit. In this work, based
on this kit, an enhancement and depletion (E/D) nMOS
educational and multi-project chips were fabricated.
There are seven different Brazilian institution projects in
this multi-project chip. In Latin America the simulation
and development of these chips has reduced the gap in
education on microfabrication technologies [5]
presents an enhancement nMOS PISCES2 characteristic
curve simulation (area of L=8µm/W=20µm), where
ID,VDS and VGS are defined as drain-source current,
drain-source voltage and gate-source voltage,
respectively. VDS and VGS bias ranging from 0 to 5V
were used. Figure 2 presents IDxVGS device curve
simulation for VGS ranging from 0 to 3V and Vds of
0.1V. An enhancement threshold voltage VTe of 0.8V
was obtained. For a depletion nMOS transistor (area of
L=8µm/W=20µm), Figures 3 and 4 present channel
Arsenic doping profile and IDxVGS device curve (VGS
ranging from -3 to 0V and Vds of 0.1V) PISCES2
simulations, respectively.
A maximum Arsenic
concentration of 4.5x1016cm-3 and a depletion threshold
voltage VTd of –1.2V were obtained, respectively.
Based on these simulations, the nMOS technology
CCS educational chip (Figure 5) formed by E/D
transistors with areas ranging from 8µm x 12µm to
200µm x 200µm, MOS capacitors with area of 350µm x
350µm and others devices, such as resistors, diodes,
inverters, flip-flop, ring oscillators and NOR gates, was
fabricated with five lithography steps. This educational
chip was formed on p-type single-crystal Si (100) wafers
with resistivities ranging from 1 to 10 Ω.cm. The
substrates were cleaned by RCA method between each
process step. Boron ion implantation (65keV B+ ions and
dose of 3x1013 ions/cm2) and dopant activation annealing
(1000oC for 20 min in N2) were performed to correct the
threshold voltage. Phosphorus ion implantation (65keV
P+ ions and dose of 5x1015 ions/cm2) and dopant
activation annealing (1000oC for 20 min in N2) were
used to source and drain junction formation.
2. Experiments, SUPREM and PISCES
simulations, and Educational Chip.
SUPREM and PISCES programs were used to
obtain nMOS device fabrication process step and
electrical caracteristic simulations, respectively. Figure 1
Figure 1 – E nMOS transistor (L=8µm/W=20µm)
IdxVds Curve
Arsenic ion implantation (30keV As+ ions and dose
of 1x1012 ions/cm2) and dopant activation annealing
(1000oC for 20 min in N2) were used to the D nMOSFET
channel depletion layer formation. The substrates were
oxidized (1000oC for 280min in O2+H2O(v)) to grow a
1µm field silicon oxide. 0.3µm thick aluminum was
evaporated by e-beam process to form the MOS structure
top contacts. Following, the wafer backside was etched
in buffered HF and a 0.3µm thick Al film was
evaporated. Finally, Al contact sintering was performed
at 430ºC in N2+H2O(v).
Figure 4– D nMOS transistor (L=8µm/W=20µm)
IdxVgs curve
Figure 2 – E nMOS transistor (L=8µm/W=20µm)
IdxVgs curve
Fig 5 – nMOS technology CCS Educational chip
3. Results and discussions.
3.1. Electrical Measurements and Spice
Simulation.
Figure 3 – Depletion transistor channel doping profile
A HP4145B analyzer was used to extract the
nMOSFET parameters, such as threshold voltages (Vth),
transconductances (gm) and sub-threshold swings, from
the transistor characteristic curves, and to obtain nMOS
inverter transfer curves. MOS capacitor C-V curves
(BOONTON 72-B capacimeter) were performed at 1
MHz to evaluate the insulator-semiconductor interface
and bulk properties.
L=8µm x W=20µm) curves. A sub-threshold slope of
125mV/decade was obtained. VDS of 0.1V and VGS bias
ranging from 0.0V to 1.8V were applied. SPICE level 3
parameters (Table I) were extracted from experimental
nMOSFET results presented in Figures 6 and 7. Figure 7
also presents the comparisons between SPICE simulation
and measurements of sub-threshold region nMOSFET
logIDxVGS (area of L=8µm x W=20µm) curves, these
results indicate a good fitting lower than 10%. This error
is similar to obtained result by reference [6].
Figure 6 – Comparisons between: (a) PISCES and (b)
SPICE simulated and experimental E nMOS transistor
(L=8µm/W=20µm) IdxVds curves
Depletion nMOS
Transistor
.MODEL ninvd NMOS
+ LEVEL=3
+ L=8.000E-6
+ W=12.000E-6
+ VTO=-1.2
+ RSH=10.65
+ TOX=56.00E-9
+ GAMMA=1.1484
+ UO=1056
+ CJ=140E-6
+ XJ=1.89E-6
+ LAMBDA=19.8E-3
+ IS=1e-9
+ NSUB=1.86e16
+ NSS=3e10
+ NFS=3e10
+ LD=1.32e-6
+ THETA=0.1308
+ TPG=0
+ VDD=5
+RDS=60e3
Enhancement nMOS
Transistor
.MODEL ninve NMOS
+ LEVEL=3
+ L=8.0000E-6
+ W=12.000E-6
+ VTO=0.8
+ RSH=10.65
+ TOX=56.00E-9
+ GAMMA=1.1484
+ UO=1056
+ CJ=140E-6
+ XJ=1.89E-6
+ LAMBDA=19.8E-3
+ IS=1e-9
+ NSUB=1.86e16
+ NSS=3e10
+ NFS=3e10
+ LD=1.32e-6
+ THETA=0.1308
+ TPG=0
+ VDD=5
+ RDS=60e3
Table I – E/D nMOS inverter Spice level 3 simulation
parameters
Figure 7- Comparisons between SPICE level 3 simulated
and experimental E nMOS transistor (L=8µm/W=20µm)
IdxVds curves
Figures 6(a) and 6(b) present the comparisons
between PISCES2 and SPICE simulations and
nMOSFET IDxVDS (area of L=8µm x W=20µm)
measurements, respectively. VDS and VGS bias ranging
from 0 to 5V were used. Figure 7 presents measurements
of sub-threshold region nMOSFET logIDxVGS (area of
Figure 8 - Comparisons between SPICE simulated and
measured E/D nMOSFET (areas of L=8µm x W=12µm)
inverter transfer curves.
3.2. Multi-project Chips and Inverter
Circuit Simulation.
Based on these experimental and simulated
results, layout design chips rules for minimum size of
8µm and obtained SPICE parameters (Table 1), a metal-
gate nMOS technology multi-project chip (Table 2) was
fabricated with five lithography steps by CCS staff. The
five masks used in these lithography steps were
fabricated by e-beam lithography equipment of
ITI/Brazil. These layout rules and SPICE parameters
(Table 1) form the CCS design kit and can be obtained in
CCS World Wide Web (http://www.ccs.unicamp.br). In
this multi-project chip, there are seven different
Brazilian institution projects: Operational Amplifier
(CCS/UNICAMP), Educational Chip (UNIMAR), test
devices to verify SPICE models (DSIF-FEECUNICAMP), power MOSFETs (ITI), step motor control
(EEL), four bit adder (CCS/UNICAMP), surface
acoustic wave (SAW) device and Operational Amplifier
(UFPE).
The inverter circuit formed by E/D nMOSFETs
with areas of L=8µm x W=12µm of test devices (Table
2) to verify SPICE models (DSIF-FEEC-UNICAMP)
was used to obtain SPICE simulated and measured
transfer curves. Figure 8 presents the comparisons
between SPICE simulated and measured E/D nMOSFET
inverter transfer curves, indicating the good fitting lower
than 10%. This error is similar to obtained result by
reference [6].
4.Conclusions
An enhancement and depletion (E/D) nMOS
technology for educational and multi-project chip
activities has been performed The SUPREM, PISCES2
and SPICE simulations were employed to obtain an
(E/D) nMOS device design kit. The experimental and
simulated results of the nMOS transistors and inverter
were compared to validate the design kit. Good fitting
results lower than 10% were obtained. Based on this kit,
a multi-project chip with seven different projects was
fabricated. Therefore, nMOS circuit behavior can be
extracted before the device fabrication, which reduces
project and re-project cycles. Futhermore, the
development of an educational and a multi-project chips
has contributed to education on microfabrication
technologies in Latin America.
ACKNOWLEDGMENTS
The authors would like to thank a CCS staff for
MOS device fabrication and ITI/Brazil for mask
manufacturing. This work is supported by FAPESP and
CNPq of Brazil.
REFERENCES
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optimization and extraction of IC device model
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parameter extraction of complex models and an
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Microeletronics Journal, pp. 149-155, 1999.
[3] S. E. Hansen and M. D. Deal, SUPREM IV.GS 2D
process simulation for Si and GaAs manual,
Integrated Circuits laboratory, Stanford University,
1993.
[4] Zhiping Yu, Datong Chen, Lydia So and Robert W.
Dutton, PISCES-2ET and its applications an
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[5] Jacobus W. Swart, ‘Education on microfabrication
in Latin America and the microeletronics workshop
at UNICAMP’, IEEE Transactions on Education,
vol. 41 pp.253-256, November, 1998.
[6] Shiuh-Wuu Lee, ‘Universality of mobility-gate field
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Operational Amplifier
(CCS/UNICAMP)
Educational Chip
(UNIMAR)
Test Devices
(DSIF-FEEC- UNICAMP)
Step Motor Control
(EEL)
Power MOSFETs
(ITI)
SAW device and Operational
Amplifier (UFPE)
Four Bit Adder (CCS/UNICAMP)
Table 2 – Metal-Gate nMOS Technology
Multi-project Chips.