# The JFET Transistor - Ryerson Department of Physics

Page 1 Junction Field-Effect Transistors
OBJECTIVES
The objective of this lab is to help you assemble and test a circuit that uses a JFET. You will
measure and plot the characteristic curves for a P-Channel JFET, as well as the transfer curve
in order to find the cutoff voltage, determine the gain from the slope of the linear region of the
transfer curve and find the operational point.
INTRODUCTION
Junction Field-Effect Transistors (JFETs) work on an entirely different principle from the
bipolar junction transistors (BJTs) although they may have similar functions. However, the
bias conditions and the characteristics are different. A junction field effect transistor has 3
terminals called “Source”, “Gate” and “Drain” as shown below. Two general types of JFETs
are the 'N' channel and the 'P' channel.
N P JFET P-Channel
The P-Channel field effect transistor (JFET) is made of a bar of P type material called the
SUBSTRATE with an N type material (the gate) diffused into it. When a negative voltage
with respect to the source is applied on the drain, a current of “holes” flows from the source to
the drain through the P CHANNEL.
If then a positive voltage with respect to the source is applied on the gate, an electrostatic field
is created between the gate and the substrate that squeezes the channel and reduces the
current. It is said that the gate and the source are reverse biased. If the positive gate voltage is
high enough the channel will be &quot;pinched off&quot; and the current will become zero.
Similarly in an N-Channel FET the current is formed by the flow of electrons.
P N JFET N-Channel
Page 2 This is why the JFET, a unipolar device is voltage controlled, unlike the bipolar junction
transistor, which is current controlled.
If the gate-source is accidentally forward biased, a large gate current will flow and the FET
will be destroyed. To avoid this, an extremely thin insulating layer of silicon oxide is placed
between the gate and the channel. This new device is then known as an insulated gate FET,
or IGFET or metal oxide semiconductor FET (MOSFET).
JFET P-CHANNEL COMMON SOURCE CHARACTERISTIC CURVES
Figure 1a: Transfer curve for a JFET.
Figure 1b: Typical characteristic curve for a JFET.
Figure 1a: The transfer curve for the JTET is useful for visualizing the gain from the device
and identifying the region of linearity. The gain is proportional to the slope of the transfer
curve. The current value IDSS represents the value when the Gate is shorted to ground, the
maximum current for the device. This value will be part of the data supplied by the
manufacturer. For the transistor you will be testing, a “Motorola” 2N5460 p-channel JFET
IDSS = 5 mAdc. The Gate voltage at which the current reaches zero is called the “cutoff
voltage”, VGS(off). For the same transistor, the data sheet gives VGS(off) = 6 V (for a drainsource voltage of 15 V). The operational point of the transistor should be chosen in the middle
part of the linear region on the transfer curve.
Figure 1b: For a given value of Gate-Source voltage VGS, the current is nearly constant over a
wide range of Drain-Source voltages VDS. The JFET controls the drain current by controlling
the depletion of charge carriers from the P-channel. When the Gate is made more positive, it
depletes the majority carriers from a larger zone around the gate and this reduces the current
flow for a given value of Drain-Source voltage. Therefore, modulating the Gate voltage
modulates the current flow through the device.
Page 3 LIST OF COMPONENTS NEEDED
1. Resistors:
a. R1 = 10 kΩ (used for protection in case the JFET is forward-biased
accidentally)
b. R2 = 100 Ω (serves as a current sensing resistor)
2. JFET P-CHANEL 2N5460 (or equivalent); case type and terminals order are shown
below.
3. 2 variable power sources
4. Three multimeters.
5. One small “breadboard” (also known as “protoboard”): solder-less board used to build
a temporary prototype of an electronic circuit.
Front
Connections on the Back
6. Jumper wires for connecting the individual components on the breadboard. Please
note: you should not try to put more than one wire or component terminal in each
hole!
Page 4 PROCEDURE AND DATA ANALYSIS
1. Measure and record the values of R1 and R2 listed above in the Table 1.
Table 1: Listed and Measured Values for R1 and R2
RESISTOR
LISTED VALUE
R1
R2
10 kΩ
100 Ω
R2 R1 VGS + MEASURED VALUE
100 Ω D G 2N5460 10 kΩ -&shy;‐ VDS + S -&shy;‐ Figure 4: Common source circuit with a P-Channel JFET.
2. Connect the components on the breadboard as shown in Figure 5 below.
VGS j i h g f 10 kΩ 2N5460 G
D
100 Ω e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 d S
c b a VDS Figure 5: Suggested arrangement of the components on the breadboard
Page 5 3. Before connecting the two variable sources, set VGS and VDS at 0V.
4. Connect a voltmeter between the drain and the source, another one to measure VGS
and a third to read the voltage across R2.
5. Slowly increase VDS until it becomes 1.0 V.
6. Measure the voltage across R2 (VR2) and enter it in the table 2.
7. Compute the drain current ID by applying Ohm’s Law to R2. (The current through R2
is the same as ID for the transistor. Repeat for all the other combinations in the table 2.
Table 2: Characteristic Curves Data for 2N5460
VDS (V)
VG = 0V
VR2
ID
VG = 0.5V
VR2
VG = 1.0V
ID
VR2
VG = 1.5V
ID
VR2
ID
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
8. Draw the characteristic curves for your transistor using the data in table 2.
9. Slowly, increase the drain-source voltage to 15 V and increase the gate-source voltage
from zero to the value where the drain current becomes practically zero. This is the
“cutoff voltage.
10. Record all the ID and VGS values in Table 3, and draw the transfer curve for your
transistor
Table 3: Transfer Curve Data for 2N5460
VGS (V)
VR2 (V)
ID (mA)
Page 6 11. Draw the transfer curve and from it find the operational point Q and the transfer
conductance at this point:
gm =
ΔID
ΔVGS
This will help you understand€how the JFET transistor is amplifying a sinusoidal signal
applied to the gate:
ID Q VGS IDQ Id VGSQ VGS(OFF) Vgs Figure 6: Transfer Curve for a P-Channel JFET showing sinusoidal signal amplification