SSRG International Journal of Electrical and Electronics Engineering (SSRG-IJEEE) – volume 1 Issue 6 -August 2014
Analysis of Cascaded H- Bridge Inverter and Minimization of Total Harmonic
Distortion
P.Divya Jyothsna1 S.Harinath2
1
Lecturer in Govt. Polytechnical college, Department of Electrical & Electronics Engineering, India.
2
PG Scholor, Department of Electrical & Electronics Engineering, JNTU college of Engineering, India.
ABSTRACT: This paper projects the different levels of
voltage induction motor drives required high level inverter to
cascaded H-bridge inverters and the minimization of total
produce the waveforms nearer to sinusoidal and to minimize
harmonic distortion by increasing the levels. For triggering of
the ripple content. As the number of levels increases, the
the semiconductor devices used in the inverter level shifting
synthesized output waveform adds more steps, producing a
pulse width modulation technique is used. Individually for
staircase wave which approaches thesinusoidal wave with
each level inverter we have developed the switching circuit
minimum harmonic distortion.The stepped waveform is
and also the inverter. The analysis of three level and five level
synthesized byselecting different voltage levels generated by
cascaded H-bridge inverters is done in MATLAB/SIMULINK
the proper connection of the load to the different capacitive
by applying level shifting PWM technique. The simulation
voltage sources. This connection is performed by the proper
results shows the improvement of output voltage waveform
switching of the power semiconductors. The three and five
and reduction of the total harmonic distortion by increasing
level cascaded H-bridge inverters are analyzed how to
the levels in inverter.
produce the sinusoidal voltage and how the switches are
operates with the level shifting PWM.
Key words: Cascaded H-bridge inverter, Level shifting
Pulse Width Modulation.
I. INTRODUCTION
The Voltage source inverter fed induction motor drives
aremostly used in medium power applications. The voltage
waveforms of two level inverter show that the voltage across
This paper is organized into five sections. Following the
introduction in section I, different levels of inverters are
discussed in section II, the basics of the level shifting PWM in
section III, the simulation of three, five and seven level
inverters with results and comparison between them in section
IV. Finally conclusion from section V.
the motorcontains not only the required fundamental
sinusoidal components, but also pulses of voltage i.e. ripple
II.
CASCADED H-BRIDGE INVERTER
voltage. The output of inverter voltage is applied to the
The cascaded multilevel inverter consists of a series
induction motor then the performance of the motors are
of H-bridge inverter. The general purpose of this
degrades. Because of the ripple voltages the rate of change of
multilevel inverter is to synthesize a desired voltage
voltage with respect to time is more.Also high voltage rating
from several separate dc sources, like batteries, fuel
of the power semiconductors devices is required for inverters
cells, solar cells, and ultra-capacitors. A single-phase
used to run the high voltage motors. The medium and high
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SSRG
G Internationaal Journal of Electrical
E
and Electronics En
ngineering (SS
SRG-IJEEE) – volume 1 Isssue 6 -August 2014
2
struccture of a casscade inverterr with separaate dc sourcess
[1]. Each separatte dc source is connectedd to a single-ngle phase toppology of thee
phasse full-bridge inverter. Sin
hybrrid multilevel inverter is sh
hown in Fig.1; the bottom
m
is onne leg of a sttandard 3-leg inverter withh a dc powerr
sourcceVdc, the toop is a hyb
brid in seriees with eachh
standdard inverter leg that the H-bridge
H
inverter can use a
separrate dc poweer source the top is a hybbrid in seriess
with each standarrd inverter leg
g that the H-brridge inverterr
u a separatee dc power so
ource (Vdc/2). Consideringg
can use
the output
o
voltage V1 of this leg
l is either +(V
+ dc/2)whenn
S1 iss closed or –V
– dc/2 when
n S2 is closedd.This leg iss
connnected in seriees witha full H-bridge
H
inveerter, then thee
outpuut voltage V2
of th
he H-bridge inverter iss
eitheer+(Vdc/2) whhen Sa1 and Sa
S 4 are closedd, 0 when Sa1,
Fig.44 Five level casscaded H-bridgge inverter
III.
SW
WITCHING PATTERN
P
SC
CHEME
I this paper, a level shifteed pulse widtth modulationn
In
technnique is emplloyed.
Sa3 or
o Sa2, Sa4 aree closed, or –(Vdc/2)
–
wheen Sa2 and Sa33
are closed. An example ou
utput waveform that thiss
topology can acchieve as sh
hown in thee Fig. 2.Thee
topology of the proposed a 5-level3-phaase cascadedd
hown in Fig. 3.
3
hybrrid multilevel inverter is sh
A.. Level shifted PWM
A m-level Cascaded
An
C
H-bbridge inverteer using level
shiftted modulatioon requires (m
m–1) triangulaar carriers, all
havinng the sam
me frequenccy and ampplitude. Thee
frequuency modulaation index iss given by
. Levell
shiftted PWM techhnique is classified into thhree types. 1))
In phase
p
disposittion 2)Phase opposition disposition
d
3))
Alterrnate phase opposition
o
disposition.
1 IN PHASE DISPOSITIION
1)
Fig.33 Three level caascaded H-brid
dge inverter
In phhase dispositiion method all
a the carrier waves are inn
phasse with each other
o
as shown in figure beelow
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SSRG
G Internationaal Journal of Electrical
E
and Electronics En
ngineering (SS
SRG-IJEEE) – volume 1 Isssue 6 -August 2014
2
Fig.6 Switching pattern in IPD
2 PHASE OPPOSITION
2)
O
N DISPOSITIO
ON
In phase opposittion dispositio
on (POD) modulation
m
alll
Fig.88 Switching pattern in APOD
D
carriier waveformss above zero reference aree in phase andd
are 180
1 0 out of phhase with those below zeroo as shown inn
figurre below
IV.
MATLAB MODELING
G AND SIMU
ULATION
RESU
ULTS
s
is carried out in followingg
In this simulation
threee cases.
i)
Cascadeed 3-level innverter with level shiftedd
pulse wiidth modulation.
ii)
Cascadeed 5-level innverter with level shiftedd
pulse wiidth modulation.
Casee i:In this casse we will finnd out outpuut voltage andd
Totaal Harmonicss Distortion for 3-level cascaded H-Fig.7Switcching pattern in
n POD
3 ALTERN
3)
NATE PHASE OPPOSITIO
ON
bridgge
inverterr.
The
sim
mulation
diiagram
correesponding waaves forms aree as shown inn figure.
DISPOSIT
TION
I case of altternate phasee disposition modulation,,
In
everyy carrier waaveform is in out of phhase with itss
neighhbor carrier by
b 1800as shown in figure below.
b
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andd
SSRG
G Internationaal Journal of Electrical
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and Electronics En
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SRG-IJEEE) – volume 1 Isssue 6 -August 2014
2
Fig.99 Three-level innverter
Fig.112 THD analyysis of 3-levell inverter withh level shiftedd
PWM
M.
Casee ii: In this caase also we will
w find out output
o
voltagee
Fig.10 switching circuit
and THD for 5-llevel cascadeed H-bridge inverter withh
levell shifted PWM
M.
Fig.11 line voltage of cascaded 3--level inverter
Fig.133 Line voltage of 5-level
5
cascaded H-bridge
H
inverter.
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SSRG
G Internationaal Journal of Electrical
E
and Electronics En
ngineering (SS
SRG-IJEEE) – volume 1 Isssue 6 -August 2014
2
increeases the Total Harmoniccs Distortionn is decreasess
and the
t machine performance
p
is improved.
Refeerences:
Fig.13 THD analysis of 5-level caascaded H-briddge inverter.
Table
LEVELS
V.
%THD
%
3
39.88
3
5
22.78
2
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w
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CONCL
LUSION:
In this paper
p
a threee level andd Five levell
cascaaded H-bridgge inverterwitth level shifteed PWM hass
beenn designed and
a
compared
d their THD
Ds. Form thee
compparison we haave to identify
fy as level of the
t inverter iss
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