ICE Module
ICE Module Carrier Board Design Guide
Page i
ICE Module
Revision
Date
Version
Changes
12 March, 2009
1.01
Changed ICE module model name from ICE-ATOM
to ICE-945GSE
23 September, 2008
Page ii
1.00
Initial release
ICE Module
Copyright
COPYRIGHT NOTICE
The information in this document is subject to change without prior notice in order to
improve reliability, design and function and does not represent a commitment on the
part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, special, incidental, or
consequential damages arising out of the use or inability to use the product or
documentation, even if advised of the possibility of such damages.
This document contains proprietary information protected by copyright. All rights are
reserved. No part of this manual may be reproduced by any mechanical, electronic, or
other means in any form without prior written permission of the manufacturer.
TRADEMARKS
All registered trademarks and product names mentioned herein are used for
identification purposes only and may be trademarks and/or registered trademarks of
their respective owners.
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ICE Module
Table of Contents
1 INTRODUCTION.....................................................................................................1
1.1 INTRODUCTION......................................................................................................2
1.2 ACRONYMS AND ABBREVIATIONS DEFINITION .....................................................2
1.3 REFERENCE DOCUMENTS ......................................................................................4
2 ICE MODULE OVERVIEW ...................................................................................5
2.1 CHAPTER OVERVIEW .............................................................................................6
2.2 ICE SPECIFICATIONS .............................................................................................7
2.2.1 ICE-9152-R10 ...............................................................................................8
2.2.2 ICE-9102-1GZ-R10.....................................................................................10
2.2.3 ICE-9102-1G512-R10.................................................................................12
2.2.4 ICE-945GSE-R10........................................................................................14
2.2.5 ICE-GM45A-R10 ........................................................................................16
2.2.6 ICE-DB-9S-R10 ..........................................................................................17
2.3 PERFORMANCE ....................................................................................................19
3 PIN ASSIGNMENTS..............................................................................................20
3.1 CHAPTER OVERVIEW ...........................................................................................21
3.2 TYPE 1, TYPE 2, TYPE 3, TYPE 4 AND TYPE 5 ......................................................22
3.3 SIGNAL TABLE TERMINOLOGY ............................................................................23
3.4 CONNECTOR PINOUT ROW A AND ROW B............................................................24
3.5 CONNECTOR PINOUT ROWS C AND D ..................................................................26
4 SIGNAL DESCRIPTION AND ROUTING GUIDELINE .................................29
4.1 PEG (PCI EXPRESS GRAPHIC) ............................................................................30
4.1.1 Signal Description ......................................................................................30
4.1.2 PEG Connector...........................................................................................32
4.1.3 SDVO ..........................................................................................................33
4.1.4 PEG_ENABLE# ..........................................................................................34
4.1.5 PCI Express Test Points and Probing ........................................................34
4.1.6 PCI Express Routing Guideline ..................................................................35
4.1.6.1 Impedance Consideration.....................................................................35
4.1.6.2 AC Coupling Capacitors ......................................................................36
4.1.6.3 Routing Notices ...................................................................................37
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4.2 PCI EXPRESS .......................................................................................................38
4.2.1 Signal Description ......................................................................................39
4.2.2 PCI Express Slot X1....................................................................................40
4.2.3 Express Card Connector.............................................................................40
4.2.4 PCIe Mini Card...........................................................................................43
4.2.5 PCI Express Clock Buffer ...........................................................................46
4.2.5.1 PCI Express Routing Guideline ...........................................................46
4.3 PCI......................................................................................................................47
4.3.1 Signal Description ......................................................................................47
4.3.2 PCI Connector ............................................................................................48
4.3.3 PCI IRQ Assignment ...................................................................................48
4.3.4 PCI Clock Buffer.........................................................................................50
4.3.5 PCI Routing Guideline................................................................................50
4.4 SATA (SERIAL ATA INTERFACE).......................................................................51
4.4.1 Signal Description ......................................................................................51
4.4.2 SATA Connector..........................................................................................52
4.4.3 SATA LED#.................................................................................................53
4.4.4 SATA Routing Guideline .............................................................................53
4.5 UNIVERSAL SERIAL BUS (USB) ..........................................................................54
4.5.1 Signal Description ......................................................................................54
4.5.2 USB Keyed Connector Protocol .................................................................55
4.5.3 ESD/EMI .....................................................................................................57
4.5.4 Over Current Protection .............................................................................58
4.5.5 Reference Schematics..................................................................................58
4.5.6 USB Routing Guideline...............................................................................60
4.5.6.1 Impedance ............................................................................................60
4.5.6.2 General Routing and Placement...........................................................60
4.6 LVDS..................................................................................................................61
4.6.1 Signal Description ......................................................................................61
4.6.2 LVDS Cable Consideration.........................................................................62
4.6.3 Backlight and LCD Power Timing Control.................................................62
4.6.4 LVDS Routing Guideline.............................................................................64
4.6.4.1 Impedance ............................................................................................64
4.6.4.2 Implement ............................................................................................64
4.7 AUDIO CODEC INTERFACE(AC’97/HDA) ...........................................................65
4.7.1 Signal Description.......................................................................................65
4.8 REFERENCE CIRCUIT ...........................................................................................65
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4.8.1 Audio Routing Guideline.............................................................................65
4.8.1.1 Analog Power Delivery........................................................................65
4.8.1.2 Digital and Analog Signals Isolation ...................................................66
4.8.1.3 EMI Consideration...............................................................................66
4.9 IDE .....................................................................................................................66
4.9.1 Signal Description ......................................................................................66
4.9.2 IDE Connector ............................................................................................67
4.9.3 CF Connector..............................................................................................68
4.10 TV-OUT ............................................................................................................69
4.10.1 Signal Description ....................................................................................69
4.10.2 TV-Out Routing Guideline ........................................................................69
4.10.2.1 Signal Termination.............................................................................69
4.10.2.2 Video Filter ........................................................................................69
4.10.2.3 ESD Protection...................................................................................70
4.10.2.4 Reference Schematic..........................................................................70
4.11 LAN (LOCAL AREA NETWORK) ........................................................................71
4.11.1 Signal Description.....................................................................................71
4.11.2 Giga LAN Connector.................................................................................72
4.11.3 LAN Link Activity and Speed LED ............................................................72
4.11.4 LAN Routing Guideline .............................................................................73
4.11.4.1 Impedance ..........................................................................................73
4.11.4.2 LAN Ground Plane Separation ..........................................................74
4.12 LPC (LOW PIN COUNT INTERFACE) ..................................................................74
4.12.1 Signal Description ....................................................................................74
4.12.2 Clock and Reset Buffer..............................................................................75
4.12.3 LPC SuperIO for Legacy IO Support........................................................76
4.12.3.1 Keyboard/Mouse................................................................................76
4.12.3.2 RS-232/Floppy/LPT/IR......................................................................77
4.13 VGA .................................................................................................................79
4.13.1 Signal Description ....................................................................................79
4.13.2 VGA Connector.........................................................................................80
4.13.3 VGA DAC Filter........................................................................................80
4.13.4 Routing Guide Line ...................................................................................80
4.13.4.1 HSYNC and VSYNC Signals............................................................80
4.13.4.2 ESD ....................................................................................................80
4.13.4.3 DDC Interface....................................................................................80
4.13.5 VGA Reference Design .............................................................................81
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4.14 MISCELLANEOUS ...............................................................................................82
4.14.1 Signal Description ....................................................................................82
4.14.2 Speaker/FAN Control/RTC Reference .......................................................84
4.14.2.1 Speaker Out........................................................................................84
4.14.2.2 FAN Control.......................................................................................84
4.14.2.3 RTC ....................................................................................................85
5 PCB STACK AND
POWER DELIVER DESIGN ............................................86
5.1 CHAPTER OVERVIEW ...........................................................................................87
5.2 MICROSTRIP OR STRIPLINE ..................................................................................87
5.3 PCB STACKUP EXAMPLE ....................................................................................87
5.3.1 Four-Layer Stack-up...................................................................................88
5.3.2 Six-Layer Stack-up ......................................................................................88
5.4 ATX POWER DELIVERY GUIDELINES ...................................................................90
5.4.1 ATX Power Status (S0,S3,S4,S5,G3)...........................................................91
5.4.2 ATX Power Diagram...................................................................................92
6.3.3 ATX Power On Timing................................................................................92
5.5 AT POWER DELIVERY GUIDELINE ......................................................................93
5.5.1 AT Power Diagram .....................................................................................93
5.5.2 AT Power On Timing ..................................................................................94
6 MECHANICAL DESIGN GUIDELINES ............................................................95
6.1 CHAPTER OVERVIEW ...........................................................................................96
6.2 COM MODULE AND CARRIER BOARD CONNECTOR ............................................96
6.2.1 Module Connector ......................................................................................96
6.2.2 Carrier Board Connector ...........................................................................97
6.3 CONNECTOR FOOTPRINT .....................................................................................98
6.4 COM EXPRESS FORM FACTORS ..........................................................................99
6.5 HEAT SPREAD ....................................................................................................100
6.6 DESIGN NOTES ..................................................................................................103
6.6.1 Component Height — Module Back and Carrier Board Top....................103
6.6.2 Air Follow Issue........................................................................................105
6.6.3 Grounding Issue........................................................................................105
6.7 OTHERS KITS SPECIFICATION ............................................................................105
6.7.1 Heat Sink...................................................................................................105
A ICE MODULE DESIGN SCHEMATIC CHECK LIST ..................................107
B APPLICATION NOTES...................................................................................... 116
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ICE Module
B.1 TERMINOLOGY ................................................................................................. 117
B.2 UPDATING BIOS VERSION ................................................................................ 117
B.2.1 Using AFUWIN......................................................................................... 118
6.7.2 Using DOS Command...............................................................................121
A.1 RTC OVERVIEW ...............................................................................................123
A.1.1 How to Calculate the Battery Life ............................................................123
B REFERENCE CARRIER BOARD SCHEMATIC...........................................124
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ICE Module
List of Figures
Figure 2-1: ICE Module Application ..............................................................................................6
Figure 2-2: ICE-9152-R10 ...............................................................................................................8
Figure 2-3: ICE-9102-1GZ-R10 .....................................................................................................10
Figure 2-4: ICE-9102-1G512-R10 .................................................................................................12
Figure 2-5: ICE-945GSE-R10........................................................................................................14
Figure 2-6: ICE-DB-9S-R10 ..........................................................................................................17
Figure 3-1: COM Express Type 2 Module Diagram ...................................................................21
Figure 4-1: PCI Express x16 Slot Example ................................................................................32
Figure 4-2: Intel Recommend Test Structure for PCI Express Data Eye Measurement ........35
Figure 4-3: PEG Lane Connection Topology Example .............................................................37
Figure 4-4: PEG Layout Trace Example .....................................................................................38
Figure 4-5: PCI Express x1 Slot Example ..................................................................................40
Figure 4-6: Express Card Slot Example...................................................................................41
Figure 4-7: Express Card 54&34 Type (Refer to www.expresscard.org)..............................42
Figure 4-8: Express Card 54 & 34 Plug Way (Refer to www.expresscard.org)....................43
Figure 4-9: Express Card Slot Example .....................................................................................44
Figure 4-10: Mini Card Bottom Side Dimensions (Refer to www.pcisig.com)........................45
Figure 4-11: Mini Card Top Side Dimensions (Refer to www.pcisig.com)..............................45
Figure 4-12: Mini Card Connector (Refer to www.pcisig.com) ................................................46
Figure 4-13: PCI Express Clock Buffer Example.......................................................................46
Figure 4-14: PCI Slot Connection Example................................................................................48
Figure 4-15: PCI Slot Routing Example ...................................................................................49
Figure 4-16: PCI Clock Buffer Example ......................................................................................50
Figure 4-17: SATA 7-pin Connector Example .........................................................................52
Figure 4-18: SATA LED Connection Example.........................................................................53
Figure 4-19: Keyed Connector Protocol (Refer to USB2.0 Spec.) ...........................................55
Figure 4-20: USB Connector........................................................................................................56
Figure 4-21: RailClamp SRV05-4 Low Capacitance TVS Diode Array for ESD ......................57
Figure 4-22: 90 ohm Common Mode Choke at 100MHz for EMI ..............................................57
Figure 4-23: MIC2026 Block Diagram(Please refer the datasheet from MICREL ) .................58
Figure 4-24: USB Reference Design ...........................................................................................59
Figure 4-25: LVDS Power Control ...............................................................................................62
Figure 4-26: Backlight Control Circuit........................................................................................63
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ICE Module
Figure 4-27: LCD Power Sequence Example(Refer to AUO G150XG01).................................63
Figure 4-28: Audio Analog Power Example ...............................................................................66
Figure 4-29: IDE Reference Design.............................................................................................67
Figure 4-30: CF Connector ..........................................................................................................68
Figure 4-31: CompactFlash® Reference Design .......................................................................68
Figure 4-32: TV Out Schematic Reference.................................................................................70
Figure 4-33: Giga Lan Connection Exampel (including Transformer) ....................................72
Figure 4-34: Clock Buffer.............................................................................................................75
Figure 4-35: Windbond W83627EHG Reference Design...........................................................76
Figure 4-36: Keyboard/Mouse Reference Schematic................................................................77
Figure 4-37: RS-232 Reference Schematic ................................................................................77
Figure 4-38: LPT Reference Schematic ......................................................................................78
Figure 4-39: Floppy Reference Schematic.................................................................................78
Figure 4-40: IR Reference Schematic .........................................................................................79
Figure 4-41: VGA Connector D-SUB15 .......................................................................................80
Figure 4-42: VGA Reference Design ...........................................................................................81
Figure 4-43: Speaker Out Reference Schematic .......................................................................84
Figure 4-44: FAN Reference Schematic .....................................................................................84
Figure 4-45: RTC Reference Schematic .....................................................................................85
Figure 5-1: Four Layers Stack .....................................................................................................88
Figure 5-2: Six Layers Stack........................................................................................................89
Figure 5-3: ATX Power Delivery Block Diagram........................................................................92
Figure 5-4: ATX Power On Sequence .........................................................................................92
Figure 5-5: AT Power Delivery Block Diagram ..........................................................................93
Figure 5-6: AT Power On Sequence............................................................................................94
Figure 6-1: Module Connector Picture .......................................................................................97
Figure 6-2: Carrier Board Connector ..........................................................................................97
Figure 6-3: Single Connector Physical Dimensions .................................................................98
Figure 6-4: Dual Connector Footprint and Alignment ..............................................................98
Figure 6-5: Compact, Basic and Extended Form Factor ....................................................... 100
Figure 6-6: Overall Height for Heat-Spreader in Basic and Extended Modules .................. 101
Figure 6-7: Basic Module Heat-Spreader ................................................................................ 102
Figure 6-8: Basic Module Heat-Spreader Footprint ............................................................... 102
Figure 6-9: IEI Heat Spread Module ......................................................................................... 103
Figure 6-10: Component Clearances Underneath Module .................................................... 104
Figure 6-11: IEI Heat Sink Module Dimensions ...................................................................... 105
Figure 6-12: IEI Heat Sink Module Picture .............................................................................. 106
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ICE Module
Figure 6-13: BIOS Main Menu (BIOS Version: MR10) ............................................................ 118
Figure 6-14: AFUWIN – Open BIOS File................................................................................... 118
Figure 6-15: Locate BIOS File................................................................................................... 119
Figure 6-16: Check Program All Block .................................................................................... 119
Figure 6-17: AFUWIN – Flash ................................................................................................... 120
Figure 6-18: BIOS Main Menu – Updated BIOS Version (MR11) ........................................... 120
Figure 6-19: USB Flash Drive and BIOS Updating Files ........................................................ 121
Figure 6-20: BIOS Updating File Directory.............................................................................. 121
Figure 6-21: GO Command ....................................................................................................... 122
Figure 6-22: BIOS Updating Complete (DOS) ......................................................................... 122
Figure 6-23: BIOS Main Menu – Updated BIOS Version (MR11) ........................................... 123
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List of Tables
Table 1-1: Conventions and Terminology....................................................................................2
Table 1-2: Reference Documents..................................................................................................4
Table 2-1: IEI ICE Modules.............................................................................................................7
Table 2-2: ICE-9152-R10 Specifications .......................................................................................8
Table 2-3: ICE-9102-1GZ-R10 Specifications .............................................................................10
Table 2-4: ICE-9102-1G512-R10 Specifications .........................................................................12
Table 2-5: ICE-945GSE-R10 Specifications................................................................................14
Table 2-6: ICE-GM45A-R10 Specification ...................................................................................16
Table 2-7: ICE-DB-9S-R10 Specification ....................................................................................17
Table 3-1 ........................................................................................................................................22
Table 3-2: Conventions and Terminology..................................................................................23
Table 3-3: Module Type 2 Connector Pinout Rows (A and B)..................................................24
Table 3-4: Module Type 2 Connector Pinout Rows (C and D)..................................................26
Table 4-1: PCI Express Signal Descriptions ..............................................................................30
Table 4-2: PEG & S DVO Pin Assignment ..................................................................................33
Table 4-3: Intel® SDVO Support Device List..............................................................................33
Table 4-4: PCI Express Impedance Consideration....................................................................35
Table 4-5: PCI Express Signal Descriptions ..............................................................................39
Table 4-6: Express Card Pin Definition ......................................................................................41
Table 4-7: Mini Card Pin-out .....................................................................................................44
Table 4-8: PCI Signal Description ...............................................................................................47
Table 4-9: PCI Slot Routing Table ...............................................................................................49
Table 4-10: PCI Impedance Consideration.................................................................................51
Table 4-11: Serial ATA Signal Descriptions...............................................................................52
Table 4-12: SATA Impedance Consideration.............................................................................53
Table 4-13: USB Signal Description............................................................................................54
Table 4-14: USB Connector Signal Description ........................................................................56
Table 4-15: LVDS Signals Description........................................................................................61
Table 4-16: LVDS Impedance Consideration .............................................................................64
Table 4-17: Audio Signals Description .......................................................................................65
Table 4-18: IDE signals description ............................................................................................66
Table 4-19: TV-Out Signal Descriptions .....................................................................................69
Table 4-20: Ethernet signals description ...................................................................................71
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Table 4-21: LAN Impedance Consideration ...............................................................................73
Table 4-22: LPC Interface Signal Descriptions..........................................................................75
Table 4-23: VGA signals description ..........................................................................................79
Table 4-24: Miscellaneous pin assignment................................................................................82
Table 5-1: Signal Tables Terminology Descriptions .................................................................91
Table 5-2: Power State Behavior.................................................................................................91
Table 5-3: ATX Power On Sequence Timing..............................................................................93
Table 5-4: AT Power On Sequence Timing ................................................................................94
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ICE Module
Chapter
1
1 Introduction
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ICE Module
1.1 Introduction
This design guide describes the design concept of the IEI COM Express module and
how to teach customers to develop their own COM Express baseboard. IEI COM
Express module is compatible with all baseboards compliant with COM Express
specification.
1.2 Acronyms and Abbreviations Definition
Table 1-1 defines the acronyms, conventions, and terminology that are used
throughout the design guide.
Table 1-1: Conventions and Terminology
Terminology
Description
AC97
Audio Codec 97’
HDA
High Definition Audio
SATA
Serial AT Attachment: serial-interface standard for hard disks
IDE (ATA)
Integrated Drive Electronics (Advanced Technology Attachment)
SDVO
Serial Digital Video Out is a proprietary technology introduced by Intel®
to add additional video signaling interfaces to a system
EMI
Electromagnetic Interference
ESD
Electrostatic Discharge
PCIe x1, x2, x4, x16
x1 refers to one PCI Express Lane of basic bandwidth; x2 to two PCI
Express Lanes; etc.. Also referred to as x1, x2, x4, x16 link.
PCI Express (PCIe)
Peripheral Component Interface Express – next-generation high speed
Serialized I/O bus
ExpressCard
A PCMCIA standard built on the latest USB 2.0 and PCI Express buses
GBE
Gigabit Ethernet
CRT
Cathode Ray Tube
DDR
Double Data Rate SDRAM memory technology
DVI
Digital Visual Interface is the interface specified by the DDWG (Digital
Display working Group) DVI Spec. Rev. 1.0
DDC
Display Data Channel is an I2C bus interface between a display and a
graphics adapter.
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ICE Module
I2C
Inter-IC (a two wire serial bus created by Philips)
LCD
Liquid Crystal Display
LFP
Local Flat Panel
LVDS
Low Voltage Differential Signaling: A high speed, low power data
transmission standard used for display connections to LCD panels.
NTSC
National Television Standards Committee
PAL
Phase Alternate Line
PCI
Peripheral Component Interface
RTC
Real Time Clock
SMBus
System Management Bus.
COM
Computer On Module
STD
Suspend To Disk
STR
Suspend To RAM
ULV
Ultra-Low Voltage
USB
Universal Serial Bus
PCI
N.C.
Not connected
N.A.
Not available
T.B.D.
To be determined
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ICE Module
1.3 Reference Documents
Table 1-2 lists all the reference documents of this design guide.
Table 1-2: Reference Documents
Document
Location
PICMGR COM Express Module™ Base Specification
http://www.picmg.org/
I2C Bus Interface
http://www.semiconductors.philips.com/
PCI Local Bus Specification, Revision 2.3
http://www.pcisig.com/
Serial ATA Specification, Revision 1.0a
http://www.serialata.org/
PC104
http://www.pc104.org/technology/pc104_tech.html
SMBus
http://www.smbus.org/specs/
Universal Serial Bus (USB) Specification, Revision 2.0
http://www.usb.org/home
IrDA
http://www.irda.org/
Ethernet(IEEE 802.3)
http://www.ieee.org/portal/site
RS-232
http://www.eia.org/
Advanced Configuration and Power Management (ACPI)
http://www.teleport.com/~acpi/
Specification 1.0b & 2.0
Advanced Power Management (APM) Specification 1.2
http://www.microsoft.com/hwdev/busbios/amp_12.
htm
PCI Express Base Specification, Revision 2.0
http://www.pcisig.com/specifications
ExpressCard Standard Release 1.0
http://www.expresscard.org/
High Definition Audio Specification, Rev. 1.0
http://www.intel.com/standards/hdaudio/
Extended Display Identification Data Standard Version 1.3
http://www.vesa.org/
(EDID™)
Enhanced Display Data Channel Specification Version 1.1
http://www.vesa.org/
(DDC)
Audio Codec ‘97 Component Specification, Version 2.3
Page 4
http://www.intel.com/design/chipsets/audio/
ICE Module
Chapter
2
2 ICE Module Overview
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ICE Module
2.1 Chapter Overview
ICE modules have various options for users to choose. IEI provides high-end,
mid-range and low-end CPU modules. Using the ICE module can overcome the
problems that may be caused by designing a compatible and stable module. IEI also
provides the service of deigning COM Express baseboard.
Figure 2-1: ICE Module Application
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ICE Module
2.2 ICE Specifications
IEI provides many kinds of ICE modules for customers, including BGA type and socket
type. Table 2-1 lists the IEI ICE modules and the specifications.
Table 2-1: IEI ICE Modules
ICE 910/915 Series
Description
ICE-9152-R10
COM Express Basic Type 2 Module, Socket 479
Intel® Pentium M CPU, VGA/LVDS, LAN, CF, SATA,
USB 2.0 and Audio
COM Express Basic Type 2 Module with Intel®
ICE-9102-1GZ-R10
Celeron® M 1G zero cache CPU, VGA/LVDS, LAN,
CF, SATA, USB 2.0 and Audio
COM Express Basic Type 2 Module with Intel®
ICE-9102-1G512-R10
Celeron® M 1G 512KB cache CPU, VGA/LVDS,
LAN, CF, SATA, USB 2.0 and Audio
ICE 945GSE Series
Description
COM Express Basic Type 2 Module with Intel®
ICE-945GSE-R10
Diamondville-SC Processor at FSB 533MHz, Intel®
945GSE/ICH7M Basic Mobile Platform supports
ICE GM45 Series
Description
COM Express Module with Intel® GM45/Penryn
ICE-GM45A-R10
processor DDR2, GbE, LVDS/CRT/HDTV-out,
SATAII, USB2.0
Carrier Board
Description
ICE-DB-9S-R10
Base Board for COM Express Type 2 modules
Others
Description
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ICE Module
2.2.1 ICE-9152-R10
The ICE-9152 is shown in Figure 2-2 and the specifications are list in Table 2-2.
Figure 2-2: ICE-9152-R10
Table 2-2: ICE-9152-R10 Specifications
Item
CPU
System Memory
System Chipset
BIOS
WatchDog Timer
Expansion Interface
MIO
USB
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Description
Socket 479 Intel® Pentium® M, Celeron® M processor
with a 533/400MHz FSB
One 200-pin 533/400MHz DDR2 SDRAM SO-DIMM
supported (system max. 2GB)
Intel® 915GME + ICH6M
AMI Flash BIOS
255 levels timer interval, from 1 to 255 sec or min
setup by software, jumperless selection, generates
system reset
1 x PCIe x16 signal to Base Board
4 x PCIe x1 signal to Base Board
4 x PCI , 32 bit / 33 MHz PCI bus Singal to Base Base
Board
2 x SATA (Signal to Base Board)
1 x IDE channel (Signal to Base Board)
8 x USB 2.0 (Signal to Base Board)
ICE Module
Audio
Ethernet
CRT Display mode
LCD Display mode
Dimensions (L x W)
Power Supply Voltage
Operating
Temperature
Operating Humidity
AC’97 Audio Signal to Base Board (Audio Codec on
Base Board)
One Intel® 82541PI GbE Chipset (co-layout Intel®
82551ER 10/100Mbps Ethernet chipset)
Signal to Base Board
VGA Integrated in Intel 915GME Signal (Signal to Base
Board)
18/24-bit Dual channel LVDS Signal (to Base Board)
125 mm x 95 mm
ATX / AT supported
0 ~ 60˚ C (32 ~ 140˚ F)
0% ~ 90% relative humidity, non-condensing
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ICE Module
2.2.2 ICE-9102-1GZ-R10
The ICE-9102-1GZ is shown in Figure 2-3 and the specifications are listed in Table
2-3.
Figure 2-3: ICE-9102-1GZ-R10
Table 2-3: ICE-9102-1GZ-R10 Specifications
Item
CPU
System Memory
System Chipset
BIOS
WatchDog Timer
Expansion Interface
MIO
USB
Audio
Ethernet
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Description
On board Intel® Celeron® M 1GHz zero cache
processor
One 200-pin 400MHz DDR2 SDRAM SO-DIMM
supported (system max. 2GB)
Intel® 910GMLE + ICH6-M
AMI Flash BIOS
Software programmable supports 1 ~255 sec. System
reset
2 x SATA (Signal to Base Board)
1 x IDE channel (Signal to Base Board)
4 x PCIe x1 Signal to Base Board
4 x PCI , 32 bit / 33 MHz PCI bus Signal to Base Board
8 x USB 2.0 (Signal to Base Board)
AC’97 Audio Signal to Base Board (Audio Codec on
Base Board)
One Intel® 82541PI GbE Chipset (co-layout Intel®
82551ER 10/100Mbps Ethernet chipset)
ICE Module
CRT Display mode
LCD Display mode
Dimensions (L x W)
Power Supply Voltage
Operating
Temperature
Operating Humidity
Singal to Base Board
VGA Integrated in Intel 910GMLE Signal (Signal to
Base Board)
18/24-bit Dual channel LVDS Signal (Signal to Base
Board)
125 mm x 95 mm
ATX / AT supported
0 ~ 60˚ C (32 ~ 140˚ F)
0% ~ 90% relative humidity, non-condensing
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ICE Module
2.2.3 ICE-9102-1G512-R10
The ICE-9152-1G512 is shown in Figure 2-4 and the specifications are listed in Table
2-4.
Figure 2-4: ICE-9102-1G512-R10
Table 2-4: ICE-9102-1G512-R10 Specifications
Item
CPU
System Memory
System Chipset
BIOS
WatchDog Timer
Expansion Interface
MIO
USB
Audio
Page 12
Description
On board Intel® Celeron® M 1GHz 512KB cache
processor
One 200-pin 400MHz DDR2 SDRAM SO-DIMM
supported (system max. 2GB)
Intel® 910GMLE + ICH6-M
AMI Flash BIOS
Software programmable supports 1 ~255 sec. System
reset
2 x SATA (Signal to Base Board)
1 x IDE channel (Signal to Base Board)
4 x PCIe x1 Signal to Base Board
4 x PCI , 32 bit / 33 MHz PCI bus Signal to Base Board
8 x USB 2.0 (Signal to Base Board)
AC’97 Audio Signal to Base Board (Audio Codec on
ICE Module
Ethernet
CRT Display mode
LCD Display mode
Dimensions (L x W)
Power Supply Voltage
Operating
Temperature
Operating Humidity
Base Board)
One Intel® 82541PI GbE Chipset (co-layout Intel®
82551ER 10/100Mbps Ethernet chipset)
Signal to Base Board
VGA Integrated in Intel 910GMLE Signal (Signal to
Base Board)
18/24-bit Dual channel LVDS Signal (Signal to Base
Board)
125 mm x 95 mm
ATX / AT supported
0 ~ 60˚ C (32 ~ 140˚ F)
0% ~ 90% relative humidity, non-condensing
Page 13
ICE Module
2.2.4 ICE-945GSE-R10
The ICE-945GSE is shown in Figure 2-5 and the specifications are listed in Table 2-5.
Figure 2-5: ICE-945GSE-R10
Table 2-5: ICE-945GSE-R10 Specifications
Item
CPU
System Memory
System Chipset
BIOS
WatchDog Timer
Audio
MIO
USB
Ethernet
Display
Page 14
Description
Intel Diamondville-SC support at FSB 533Mhz
1x DDR2 SO-DIMM 400/533MHz support up to 2GB
Intel 945GSE + ICH7M
AMI BIOS
Sofware Programmable support 1~255 sec. System
reset
HD Audio Signal to Base Board (Audio Codec on Base
Board)
2 x SATA II (Signal to Base Board)
1 x IDE channel (Signal to Base Board)
8 USB ports, USB 2.0 (Signal to Base Board)
1 x Intel® 82541PI GbE Chipset (co-layout Intel®
82551ER 10/100Mbps Ethernet chipset) (Signal to
Base Board)
Analog CRT(VGA) Integrated in Intel® 945GSE (Signal
ICE Module
Dimensions (L x W)
Power Supply Voltage
Operating
Temperature
Operating Humidity
to Base Board)
18-bits Dual Channel LVDS Signal (Signal to Base
Board)
HDTV-out (Signal to Base Board)
1 x SDVO Interface (Only SDVO Port_B)
125 mm x 95 mm
AT/ATX support
0 ~ 60° C (32 ~ 140° F)
0% ~ 90% relative humidity, non-condensing system
Page 15
ICE Module
2.2.5 ICE-GM45A-R10
The ICE-GM45A is shown in Error! Reference source not found. and the specifications
are listed in Table 2-6.
Table 2-6: ICE-GM45A-R10 Specification
Item
CPU
System Memory
System Chipset
BIOS
WatchDog Timer
Audio
MIO
Description
Socket P Intel® mobile Core™ 2 Duo(Penryn), Intel®
Celeron® M
2 x 200-pins 1066/800MHz DDR2 SDRAM SO-DIMM
Supported
Intel® GM45 + Intel® ICH9M
AMI BIOS
Software programmable supports 1 ~255 sec. System
reset
HD Audio Signal to Base Board (Audio Codec on Base
Board)
4 x SATA II (Signal to Base Board)
1 x IDE channel (Signal to Base Board)
1 x PCIe x16 signal to Base Board
Expansion
4 x PCIe x1 signal to Base Board
4 x PCI, 32 bit / 33 MHz PCI bus to Base Board
USB
Ethernet
Display
Dimensions (L x W)
Power Supply Voltage
Operating
Temperature
Operating Humidity
Page 16
8 x USB 2.0 (Signal to Base Board)
1 x Intel 82574L GbE chipset (Signal to Base Board)
Analog CRT(VGA) Integrated in Intel® GM45 (Signal to
Base Board)
18/24-bits Dual-Channel LVDS (Signal to Base Board)
HDTV-out (Signal to Base Board)
125 mm x 95 mm
ATX/AT supported
0 ~ 60° C (32 ~ 140° F)
0% ~ 90% relative humidity, non-condensing system
ICE Module
2.2.6 ICE-DB-9S-R10
The ICE-DB-9S is a full function carrier board for customers to apply or test the COM
Express module. The carrier board can be used for any combination, including
software and hardware. Using the carrier board to develop and test the ICE module
also can achieve a quicker time to market. The ICE-DB-9S is shown in Figure 2-6 and
the specifications are listed in Table 2-7.
Figure 2-6: ICE-DB-9S-R10
Table 2-7: ICE-DB-9S-R10 Specification
Item
CPU module interface
Audio
MIO
Description
Supports COM Express Compact/Basic/Extended
modules using connector pin out Type 2
Realtek ALC888 7.1 channels HD audio codec
Front Audio by pin-header(Line in, Line out, Mic in)
SPDIF by pin-header
CD-IN by pin-header
1 x PCIe by 16 Slot
4 x PCIe by 1 Slot
3 x PCI Slot
1 x PCIe Mini card Slot
1 x Express Card Slot
1 x Mini PCI Card Slot
Page 17
ICE Module
Ethernet
Display
Dimensions (L x W)
Power Supply Voltage
Operating
Temperature
Operating Humidity
Page 18
1 x ISA
1 x IDE
2/4 x SATA/SATA II
1 x CF type II Slot
6 x USB 2.0
1 x LPT
1 x FDD
5 x RS-232
1 x RS-232/422/485
2 x USB 2.0 to PCIe Mini card Slot & Express Card Slot
1 x RJ-45 GbE connector
VGA DB15 connector
1 x 18/24 bit dual channel LVDS Connector
1 x Inverter connector
1 x TV-out interface
304.8 mm x 190.5 mm ( 12" x 7.5" )
ATX / AT support
0 ~ 60° C (32 ~ 140° F)
0% ~ 90% relative humidity, non-condensing system
ICE Module
2.3 Performance
Page 19
ICE Module
Chapter
3
3 Pin Assignments
Page 20
ICE Module
3.1 Chapter Overview
This chapter describes pin assignments and I/O characteristics for COM Express
modules. The carrier board uses two 220-pin 0.5 mm fine pitch board-to-board
connectors. There are five different pin-out types currently defined by the COM
Express Specification. The preferred choice of the embedded computer industry is the
Type 2 pin-out and therefore the leading manufacturers have chosen to produce COM
Express Type 2 modules. This pin-out offers the best balance between older
technology such as PCI and Parallel ATA while providing the latest technologies
including PCI Express, Serial ATA and PCI Express graphics.
Figure 3-1: COM Express Type 2 Module Diagram
Page 21
ICE Module
3.2 Type 1, Type 2, Type 3, Type 4 and Type 5
The differences among the Module Types are summarized in Table 3-1.
ƒ
Module Type 1 supports a single connector with two rows of pins
(220 pins total).
ƒ
Module Types 2-5 support two connectors with four rows of pins
(440 pins total).
Connector placement and most mounting holes have transparency between Form
Factors.
Table 3-1
Module Type
Rows
PCIe Lanes (max)
PCI
IDE
LAN (Max)
1
AB
6
X
X
1
2 (Default)
AB, CD
22
V
V
1
3
AB, CD
22
X
V
3
4
AB, CD
32
V
X
1
5
AB, CD
32
X
X
3
Page 22
ICE Module
3.3 Signal Table Terminology
The following section describes the signals found on COM Express Type 2 connectors.
Most of the signals listed in the following sections also apply to other COM Express
module types. The pinout for connector rows A and B remains the same regardless of
the module type but the pinout for connector rows D and C are dependent on the
module type. Refer to the COM Express specification for information about the
different pin-outs of the module types other than Type 2.
Table 3-2 below describes the terminology used in this section for the Signal
Description tables. The “#” symbol at the end of the signal name indicates that the
active or asserted state occurs when the signal is at a low voltage level. When “#” is
not present, the signal is asserted when at a high voltage level.
Table 3-2: Conventions and Terminology
Term
Description
I/O
Bi-directional signal
I
Input signal
O
Output signal
I/F
Interface
GND
Ground
PWR
Power
OD
Open drain output
PD
Pull down
PU
Pull up
+V12
+12V ±5% Volts Normal Power
+V5SB
+5V ±5% Standby Power
+3.3VSB
+3.3V ±5% Standby Power
+V3.3
+3.3V ±5% Volts Normal Power
+V5
+5V ±5% Volts Normal Power
#
Active-Low Signals
‘+’ and ‘-‘
Differential Pairs
PM
Power Management
GBE
Giga Bits Ethernet
Page 23
ICE Module
3.4 Connector Pinout Row A and Row B
Table 3-3: Module Type 2 Connector Pinout Rows (A and B)
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
Signal
GND
GBE0_MDI3GBE0_MDI3+
GBE0_LINK100#
GBE0_LINK1000#
GBE0_MDI2GBE0_MDI2+
GBE0_LINK#
GBE0_MDI1GBE0_MDI1+
GND
GBE0_MDI0GBE0_MDI0+
GBE0_CTREF
SUS_S3#
SATA0_TX+
SATA0_TXSUS_S4#
SATA0_RX+
SATA0_RXGND
SATA2_TX+
SATA2_TXSUS_S5#
SATA2_RX+
SATA2_RXBATLOW#
ATA_ACT#
AC_SYNC
AC_RST#
GND
AC_BITCLK
AC_SDOUT
BIOS_DISABLE#
THRMTRIP#
USB6USB6+
USB_6_7_OC#
USB4USB4+
GND
USB2USB2+
USB_2_3_OC#
USB0USB0+
VCC_RTC
EXCD0_PERST#
EXCD0_CPPE#
LPC_SERIRQ
Page 24
I/F
GND
GBE
GBE
GBE
GBE
GBE
GBE
GBE
GBE
GBE
GND
GBE
GBE
GBE
PM
SATA
SATA
PM
SATA
SATA
GND
SATA
SATA
PM
SATA
SATA
PM
SATA
HDA
HDA
GND
HDA
HAD
PM
USB
USB
USB
USB
USB
GND
USB
USB
USB
USB
USB
PWR
PCIE
PCIE
LPC
I/O
I/O
I/O
O 3.3V
O 3.3V
I/O
I/O
O 3.3V
I/O
I/O
I/O
I/O
O
O
O
O
I
I
O
O
O
I
I
I
O 3.3V
O 3.3V
O 3.3V
O 3.3V
O 3.3V
O
I/O
I/O
I 3.3V
I/O
I/O
I/O
I/O
I 3.3V
I/O
I/O
-I/O
3.3V
Pin
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
Signal
GND
GBE0_ACT#
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ0#
LPC_DRQ1#
LPC_CLK
GND
PWRBTN#
SMB_CK
SMB_DAT
SMB_ALERT#
SATA1_TX+
SATA1_TXSUS_STAT#
SATA1_RX+
SATA1_RXGND
SATA3_TX+
SATA3_TXPWR_OK
SATA3_RX+
SATA3_RXWDT
AC_SDIN2
AC_SDIN1
AC_SDIN0
GND
SPKR
I2C_CK
I2C_DAT
THRM#
USB7USB7+
USB_4_5_OC#
USB5USB5+
GND
USB3USB3+
USB_0_1_OC#
USB1USB1+
EXCD1_PERST#
EXCD1_CPPE#
SYS_RESET#
CB_RESET#
I/F
GND
GBE
LPC
LPC
LPC
LPC
LPC
LPC
LPC
LPC
GND
PM
SMB
SMB
SMB
SATA
SATA
PM
SATA
SATA
GND
SATA
SATA
PM
SATA
SATA
HDA
HDA
HDA
GND
I2C
I2C
PM
USB
USB
USB
USB
USB
GND
USB
USB
USB
USB
USB
PCIE
PCIE
PM
PM
I/O
O 3.3V
O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I 3.3V
I 3.3V
O 3.3V
I
I
O
O
O
I
I
O
O
I
I
I
I 3.3V
I 3.3V
I 3.3V
I
I/O
I/O
I 3.3V
I/O
I/O
I/O
I/O
I 3.3V
I/O
I/O
I
O
ICE Module
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
GND
PCIE_TX5+
PCIE_TX5GPI0
PCIE_TX4+
PCIE_TX4GND
PCIE_TX3+
PCIE_TX3GND
PCIE_TX2+
PCIE_TX2GPI1
PCIE_TX1+
PCIE_TX1GND
GPI2
PCIE_TX0+
PCIE_TX0GND
LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2LVDS_VDD_EN
LVDS_A3+
LVDS_A3GND
LVDS_A_CK+
LVDS_A_CKLVDS_I2C_CK
LVDS_I2C_DAT
GPI3
KBD_RST#
KBD_A20GATE
PCIE0_CK_REF+
PCIE0_CK_REFGND
RSVD
RSVD
GPO0
RSVD
RSVD
GND
+V12
+V12
+V12
GND
+V12
+V12
+V12
+V12
+V12
+V12
GND
PCIE
PCIE
PCIE
PCIE
GND
PCIE
PCIE
GND
PCIE
PCIE
PCIE
PCIE
GND
PCIE
PCIE
GND
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
GND
LVDS
LVDS
LVDS
LVDS
KB/MS
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O 3.3V
O
O
O
O
O 3.3V
IO 3.3V
-
-
-
GND
PWR
PWR
PWR
GND
PWR
PWR
PWR
PWR
PWR
PWR
-
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
B105
B106
GND
PCIE_RX5+
PCIE_RX5GPO1
PCIE_RX4+
PCIE_RX4GPO2
PCIE_RX3+
PCIE_RX3GND
PCIE_RX2+
PCIE_RX2GPO3
PCIE_RX1+
PCIE_RX1WAKE0#
WAKE1#
PCIE_RX0+
PCIE_RX0GND
LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2LVDS_B3+
LVDS_B3LVDS_BKLT_EN
GND
LVDS_B_CK+
LVDS_B_CKLVDS_BKLT_CTRL
5VSB
5VSB
5VSB
5VSB
RSVD
VGA_RED
GND
VGA_GRN
VGA_BLU
VGA_HSYNC
VGA_VSYNC
VGA_I2C_CK
VGA_I2C_DAT
TV_DAC_A
TV_DAC_B
TV_DAC_C
GND
+V12
+V12
+V12
+V12
+V12
+V12
GND
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
GND
PCIE
PCIE
PCIE
PCIE
PCIE
PM
PCIE
PCIE
GND
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
GND
LVDS
LVDS
LVDS
PWR
PWR
PWR
PWR
VGA
GND
VGA
VGA
VGA
VGA
VGA
VGA
TV
TV
TV
GND
PWR
PWR
PWR
PWR
PWR
PWR
Page 25
I
I
I
I
-I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O 3.3V
O
O
O 3.3V
-
-
ICE Module
A107
A108
A109
A110
+V12
+V12
+V12
GND
PWR
PWR
PWR
GND
-
B107
B108
B109
B110
+V12
+V12
+V12
GND
PWR
PWR
PWR
GND
-
Signal
GND
IDE_D5
IDE_D10
IDE_D11
IDE_D12
IDE_D4
IDE_D0
IDE_REQ
IDE_IOW#
IDE_ACK#
GND
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_CS1#
IDE_CS3#
IDE_RESET#
PCI_GNT3#
PCI_REQ3#
GND
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_C/BE0#
PCI_AD9
PCI_AD11
PCI_AD13
PCI_AD15
GND
PCI_PAR
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_AD16
PCI_AD18
PCI_AD20
PCI_AD22
GND
PCI_AD24
PCI_AD26
PCI_AD28
PCI_AD30
I/F
GND
IDE
IDE
IDE
IDE
IDE
IDE
IDE
IDE
IDE
GND
IDE
IDE
IDE
IDE
IDE
IDE
IDE
PCI
PCI
GND
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
GND
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
GND
PCI
PCI
PCI
PCI
I/O
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
I 3.3V
O 3.3V
O 3.3V
I 3.3V
O 3.3V
O 3.3V
O 3.3V
O 3.3V
O 3.3V
IO 3.3V
O 3.3V
I 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
3.5 Connector Pinout Rows C and D
Table 3-4: Module Type 2 Connector Pinout Rows (C and D)
Pin
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
Signal
GND
IDE_D7
IDE_D6
IDE_D3
IDE_D15
IDE_D8
IDE_D9
IDE_D2
IDE_D13
IDE_D1
GND
IDE_D14
IDE_IORDY
IDE_IOR#
PCI_PME#
PCI_GNT2#
PCI_REQ2#
PCI_GNT1#
PCI_REQ1#
PCI_GNT0#
GND
PCI_REQ0#
PCI_RESET#
PCI_AD0
PCI_AD2
PCI_AD4
PCI_AD6
PCI_AD8
PCI_AD10
PCI_AD12
GND
PCI_AD14
PCI_C/BE1#
PCI_PERR#
PCI_LOCK#
PCI_DEVSEL#
PCI_IRDY#
PCI_C/BE2#
PCI_AD17
PCI_AD19
GND
PCI_AD21
PCI_AD23
PCI_C/BE3#
PCI_AD25
Page 26
I/F
GND
IDE
IDE
IDE
IDE
IDE
IDE
IDE
IDE
IDE
GND
IDE
IDE
IDE
PCI
PCI
PCI
PCI
PCI
PCI
GND
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
GND
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
GND
PCI
PCI
PCI
PCI
I/O
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
I 3.3V
O 3.3V
IO 3.3V
O 3.3V
I 3.3V
O 3.3V
I 3.3V
O 3.3V
I 3.3V
O 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
IO 3.3V
Pin
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
ICE Module
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
C98
C99
C100
C101
PCI_AD27
PCI_AD29
PCI_AD31
PCI_IRQA#
PCI_IRQB#
GND
PEG_RX0+
PEG_RX0TYPE0#
PEG_RX1+
PEG_RX1TYPE1#
PEG_RX2+
PEG_RX2GND
PEG_RX3+
PEG_RX3RSVD
RSVD
PEG_RX4+
PEG_RX4FAN_PWMOUT
PEG_RX5+
PEG_RX5GND
PEG_RX6+
PEG_RX6SDVO_DATA
PEG_RX7+
PEG_RX7GND
FAN_TACHOIN
PEG_RX8+
PEG_RX8GND
PEG_RX9+
PEG_RX9RSVD
GND
PEG_RX10+
PEG_RX10GND
PEG_RX11+
PEG_RX11GND
PEG_RX12+
PEG_RX12GND
PEG_RX13+
PEG_RX13GND
RSVD
PEG_RX14+
PEG_RX14GND
PEG_RX15+
PCI
PCI
PCI
PCI
PCI
GND
PEG
PEG
IO 3.3V
IO 3.3V
IO 3.3V
I 3.3V
I 3.3V
I
I
PEG
PEG
I
I
PEG
PEG
GND
PEG
PEG
PEG
PEG
PEG
PEG
GND
PEG
PEG
I
I
I
I
I
I
O
I
I
I
I
PEG
PEG
GND
PEG
PEG
GND
PEG
PEG
I
I
I
I
I
I
I
GND
PEG
PEG
GND
PEG
PEG
GND
PEG
PEG
GND
PEG
PEG
GND
PEG
PEG
GND
PEG
I
I
I
I
I
I
I
I
I
I
I
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D101
PCI_IRQC#
PCI_IRQD#
PCI_CLKRUN#
PCI_M66EN
PCI_CLK
GND
PEG_TX0+
PEG_TX0PEG_LANE_RV#
PEG_TX1+
PEG_TX1TYPE2#
PEG_TX2+
PEG_TX2GND
PEG_TX3+
PEG_TX3RSVD
RSVD
PEG_TX4+
PEG_TX4GND
PEG_TX5+
PEG_TX5GND
PEG_TX6+
PEG_TX6SVDO_CLK
PEG_TX7+
PEG_TX7GND
IDE_CBLID#
PEG_TX8+
PEG_TX8GND
PEG_TX9+
PEG_TX9RSVD
GND
PEG_TX10+
PEG_TX10GND
PEG_TX11+
PEG_TX11GND
PEG_TX12+
PEG_TX12GND
PEG_TX13+
PEG_TX13GND
PEG_ENABLE#
PEG_TX14+
PEG_TX14GND
PEG_TX15+
PCI
PCI
PCI
PCI
PCI
GND
PEG
PEG
I 3.3V
I 3.3V
I/O 3.3V
I 3.3V
OI 3.3V
O
O
PEG
PEG
O
O
PEG
PEG
GND
PEG
PEG
PEG
PEG
GND
PEG
PEG
GND
PEG
PEG
O
O
O
O
O
O
O
O
O
O
PEG
PEG
GND
IDE
PEG
PEG
GND
PEG
PEG
O
O
I 3.3V
O
O
O
O
GND
PEG
PEG
GND
PEG
PEG
GND
PEG
PEG
GND
PEG
PEG
GND
O
O
O
O
O
O
O
O
-
PEG
PEG
GND
PEG
O
O
O
Page 27
ICE Module
C102
C103
C104
C105
C106
C107
C108
C109
C110
PEG_RX15GND
+V12
+V12
+V12
+V12
+V12
+V12
GND
Page 28
PEG
GND
PWR
PWR
PWR
PWR
PWR
PWR
GND
I
-
D102
D103
D104
D105
D106
D107
D108
D109
D110
PEG_TX15GND
+V12
+V12
+V12
+V12
+V12
+V12
GND
PEG
GND
PWR
PWR
PWR
PWR
PWR
PWR
GND
O
-
ICE Module
Chapter
4
4 Signal Description and
Routing Guideline
Page 29
ICE Module
4.1 PEG (PCI Express Graphic)
The PEG Port can utilize COM Express PCIe lanes 16-32 and is suitable to drive a x16
link for an external high-performance PCI Express Graphics card, if implemented on
the COM Express module. It supports a theoretical bandwidth of up to 4 GB/s – twice
the peak bandwidth achievable with AGP 8x. Each lane of the PEG Port consists of a
receiver and transmit differential signal pair designated 'PEG_RX0' (+ and -) to
'PEG_RX15' (+ and -) and correspondingly from 'PEG_TX0' (+ and -) to 'PEG_TX15'
(+ and -). The corresponding signals can be found on the Module connector rows C
and D. The pins of the PEG Port are shared with other functionality like SDVO or DVO
depends of the used chipset. SDVO and PEG are defined on COM Express
specification as “may be used”. Please be sure, your functionality will be supported by
your module vendor.
4.1.1 Signal Description
Table 4-1: PCI Express Signal Descriptions
Pin
Signal
C52
C53
D52
D53
C55
C56
D55
D56
C58
C59
D58
D59
C61
C62
D61
D62
C65
C66
D65
D66
C68
C69
D68
D69
C71
C72
D71
D72
C74
C75
D74
PEG_RX0+
PEG_RX0PEG_TX0+
PEG_TX0PEG_RX1+
PEG_RX1PEG_TX1+
PEG_TX1PEG_RX2+
PEG_RX2PEG_TX2+
PEG_TX2PEG_RX3+
PEG_RX3PEG_TX3+
PEG_TX3PEG_RX4+
PEG_RX4PEG_TX4+
PEG_TX4PEG_RX5+
PEG_RX5PEG_TX5+
PEG_TX5PEG_RX6+
PEG_RX6PEG_TX6+
PEG_TX6PEG_RX7+
PEG_RX7PEG_TX7+
Page 30
I/O
Description
I
PEG Port 0. Receive Input differential pair.
O
PEG Port 0. Transmit Output differential pair.
I
PEG Port 1. Receive Input differential pair.
O
PEG Port 1. Transmit Output differential pair.
I
PEG Port 2. Receive Input differential pair.
O
PEG Port 2. Transmit Output differential pair.
I
PEG Port 3. Receive Input differential pair.
O
PEG Port 3. Transmit Output differential pair.
I
PEG Port 4. Receive Input differential pair.
O
PEG Port 4. Transmit Output differential pair.
I
PEG Port 5. Receive Input differential pair.
O
PEG Port 5. Transmit Output differential pair.
I
PEG Port 6. Receive Input differential pair.
O
PEG Port 6. Transmit Output differential pair.
I
PEG Port 7. Receive Input differential pair.
O
PEG Port 7. Transmit Output differential pair.
ICE Module
D75
C78
C79
D78
D79
C81
C82
D81
D82
C85
C86
D85
D86
C88
C89
D88
D89
C91
C92
D91
D92
C94
C95
D94
D95
C98
C99
D98
D99
C101
C102
D101
D102
A88
A98
D73
C73
PEG_TX7PEG_RX8+
PEG_RX8PEG_TX8+
PEG_TX8PEG_RX9+
PEG_RX9PEG_TX9+
PEG_TX9PEG_RX10+
PEG_RX10PEG_TX10+
PEG_TX10PEG_RX11+
PEG_RX11PEG_TX11+
PEG_TX11PEG_RX12+
PEG_RX12PEG_TX12+
PEG_TX12PEG_RX13+
PEG_RX13PEG_TX13+
PEG_TX13PEG_RX14+
PEG_RX14PEG_TX14+
PEG_TX14PEG_RX15+
PEG_RX15PEG_TX15+
PEG_TX15PCIE_CLK_REF
+
PCIE_CLK_REFSDVO_I2C_CLK
D54
SDVO_I2C_DAT
A
PEG_LANE_RV#
D97
PEG_ENABLE#
I
PEG Port 8,. Receive Input differential pair.
O
PEG Port 8. Transmit Output differential pair.
I
PEG Port 9,. Receive Input differential pair.
O
PEG Port 9. Transmit Output differential pair.
I
PEG Port 10.. Receive Input differential pair.
O
PEG Port 10.Transmit Output differential pair.
I
PEG Port 11. Receive Input differential pair.
O
PEG Port 11. Transmit Output differential pair.
I
PEG Port 12. Receive Input differential pair.
O
PEG Port 12. Transmit Output differential pair.
I
PEG Port 13,. Receive Input differential pair.
O
PEG Port 13. Transmit Output differential pair.
I
PEG Port 14.. Receive Input differential pair.
O
PEG Port 14. Transmit Output differential pair.
I
PEG Port 15. Receive Input differential pair.
O
PEG Port 15. Transmit Output differential pair.
O
PCIe Reference Clock for all COM Express
PCIe lanes, and for PEG lanes
O 2.5V
CMOS
I/O 2.5V
OD CMOS
I 3.3V
CMOS
I 3.3V
CMOS
I2C based control signal (clock) for SDVO
device.
I2C based control signal (data) for SDVO device
PCI Express Graphics lane reversal input strap.
Pull low on the carrier board to reverse lane
order.
PEG enable function. Strap to enable PCI
Express x16 external graphics interface. Pull low
to disable internal graphics and enable the x16
interface.
PS: IEI Bios auto detect the SDVO or
PCIEX16, please reserve for future use
Page 31
ICE Module
4.1.2 PEG Connector
Figure 4-1 illustrates the pinout definition for the standard PCI Express x16
connectors.
+V3.3 +V12
+V12
+V3.3_DUAL
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
3,4,5,10,11,17,20 SMB_CK
3,4,5,10,11,17,20 SMB_DAT
3,5,10,16 PCIE_WAKE_UP#
3
3
B12
B13
B14
B15
B16
B17
B18
PEG_TX0+
PEG_TX0-
3 SDVO_I2C_CK
3
3
PEG_TX1+
PEG_TX1-
3
3
PEG_TX2+
PEG_TX2-
3
3
PEG_TX3+
PEG_TX3-
3
3
PEG_TX4+
PEG_TX4-
3
3
PEG_TX5+
PEG_TX5-
3
3
PEG_TX6+
PEG_TX6-
3
3
PEG_TX7+
PEG_TX7-
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
3 SDVO_I2C_DAT
TP43
3
3
PEG_TX8+
PEG_TX8-
3
3
PEG_TX9+
PEG_TX9-
3
3
PEG_TX10+
PEG_TX10-
3
3
PEG_TX11+
PEG_TX11-
3
3
PEG_TX12+
PEG_TX12-
3
3
PEG_TX13+
PEG_TX13-
3
3
PEG_TX14+
PEG_TX14-
3
3
PEG_TX15+
PEG_TX15-
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
+12V03
+12V04
RSVD05
GND35
SMBCLK
SMBDATA
GND36
3_3V03
JTAG1
3_3VAUX
WAKE#
PRSNT1#
+12V01
+12V02
GND01
JTAG2
JTAG3
JTAG4
JTAG5
3_3V01
3_3V02
PWRGD
RSVD06
GND37
HSOP0
HSON0
GND38
PRSNT2#01
GND39
GND02
REFCLK+
REFCLKGND03
HSIP0
HSIN0
GND04
HSOP1
HSON1
GND40
GND41
HSOP2
HSON2
GND42
GND43
HSOP3
HSON3
GND44
RSVD07
PRSNT2#02
GND45
RSVD01
GND05
HSIP1
HSIN1
GND06
GND07
HSIP2
HSIN2
GND08
GND09
HSIP3
HSIN3
GND10
RSVD02
HSOP4
HSON4
GND46
GND47
HSOP5
HSON5
GND48
GND49
HSOP6
HSON6
GND50
GND51
HSOP7
HSON7
GND52
PRSNT2#03
GND53
RSVD03
GND11
HSIP4
HSIN4
GND12
GND13
HSIP5
HSIN5
GND14
GND15
HSIP6
HSIN6
GND16
GND17
HSIP7
HSIN7
GND18
HSOP8
HSON8
GND54
GND55
HSOP9
HSON9
GND56
GND57
HSOP10
HSON10
GND58
GND59
HSOP11
HSON11
GND60
GND61
HSOP12
HSON12
GND62
GND63
HSOP13
HSON13
GND64
GND65
HSOP14
HSON14
GND66
GND67
HSOP15
HSON15
GND68
PRSNT2#04
RSVD08
NC1 NC2
NC1
PCIE_X16
RSVD04
GND19
HSIP8
HSIN8
GND20
GND21
HSIP9
HSIN9
GND22
GND23
HSIP10
HSIN10
GND24
GND25
HSIP11
HSIN11
GND26
GND27
HSIP12
HSIN12
GND28
GND29
HSIP13
HSIN13
GND30
GND31
HSIP14
HSIN14
GND32
GND33
HSIP15
HSIN15
GND34
Figure 4-1: PCI Express x16 Slot Example
Page 32
+V3.3
PCIEX16_1
NC2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
CB_RESET# 3,5,10,11,14,20
CLK100M_PCIEx16_SLOT+ 4
CLK100M_PCIEx16_SLOT- 4
0_4 2
0_4 2
1 R171
1 R223
0_4 2
0_4 2
1 R224
1 R225
0_4 2
0_4 2
1 R226
1 R227
0_4 2
0_4 2
1 R228
1 R376
0_4 2
0_4 2
1 R377
1 R378
0_4 2
0_4 2
1 R379
1 R380
0_4 2
0_4 2
1 R381
1 R382
0_4 2
0_4 2
1 R383
1 R384
0_4 2
0_4 2
1 R385
1 R386
0_4 2
0_4 2
1 R387
1 R388
0_4 2
0_4 2
1 R389
1 R390
0_4 2
0_4 2
1 R391
1 R392
0_4 2
0_4 2
1 R393
1 R394
0_4 2
0_4 2
1 R395
1 R396
0_4 2
0_4 2
1 R397
1 R399
0_4 2
0_4 2
1 R400
1 R401
PEG_RX0+
PEG_RX0-
3
3
PEG_RX1+
PEG_RX1-
3
3
PEG_RX2+
PEG_RX2-
3
3
PEG_RX3+
PEG_RX3-
3
3
PEG_RX4+
PEG_RX4-
3
3
PEG_RX5+
PEG_RX5-
3
3
PEG_RX6+
PEG_RX6-
3
3
PEG_RX7+
PEG_RX7-
3
3
PEG_RX8+
PEG_RX8-
3
3
PEG_RX9+
PEG_RX9-
3
3
PEG_RX10+
PEG_RX10-
3
3
PEG_RX11+
PEG_RX11-
3
3
PEG_RX12+
PEG_RX12-
3
3
PEG_RX13+
PEG_RX13-
3
3
PEG_RX14+
PEG_RX14-
3
3
PEG_RX15+
PEG_RX15-
3
3
1
TP61
1
1
TP62
TP63
1
1
TP68
TP71
1
1
TP72
TP73
1
1
TP74
TP75
1
1
TP76
TP77
1
1
TP78
TP79
1
1
TP81
TP82
1
1
TP83
TP84
1
1
TP85
TP86
1
TP87
ICE Module
4.1.3 SDVO
The Serial Digital Video Out (SDVO) display ports are multiplexed over a subset of the
External Graphics Interface using PCI Express. Users can choose a manufacturer
approved by Intel® to convert the SDVO port to TV, LVDS, DVI or CRT connection. IEI
also provides cables and SDVO card for customer to use. Due to the fact that SDVO is
an Intel® defined interface, the number of supported SDVO devices is limited to
devices that are supported by the Intel® Graphics Video BIOS and Graphics Driver
software.
The COM Express Module graphics controller configures the PEG lines for SDVO
operation
if
it
detects
that
COM
Express
signals
SDVO_I2C_CLK
and
SDVO_I2C_DATA are pulled high to 2.5V, and if the PEG_ENABLE# line is left
floating. IEI BIOS auto detects the SDVO or PCIEX16, please reserve for future use.
Table 4-2: PEG & S DVO Pin Assignment
Pin
Signal
SDVO
C52
C53
C55
C56
C58
C59
C68
C69
D52
D53
D55
D56
D58
D59
D61
D62
D65
D66
D68
D69
D71
D72
D74
D75
PEG_RX0+
PEG_RX0PEG_RX1+
PEG_RX1PEG_RX2+
PEG_RX2PEG_RX5+
PEG_RX5PEG_TX0+
PEG_TX0PEG_TX1+
PEG_TX1PEG_TX2+
PEG_TX2PEG_TX3+
PEG_TX3PEG_TX4+
PEG_TX4PEG_TX5+
PEG_TX5PEG_TX6+
PEG_TX6PEG_TX7+
PEG_TX7-
SDVO_TVCLKIN+
SDVO_TVCLKINSDVOB_INT+
SDVOB_INTSDVO_FLDSTALL+
SDVO_FLDSTALLSDVOB_INT+
SDVOB_INTSDVOB_RED+
SDVOB_REDSDVOB_GREEN+
SDVOB_GREENSDVOB_BLUE+
SDVOB_BLUESDVOB_CLK+
SDVOB_CLKSDVOC_RED+
SDVOC_REDSDVOC_GREEN+
SDVOC_GREENSDVOC_BLUE+
SDVOC_BLUESDVOC_CLK+
SDVOC_CLK-
Description
SDVO TVOUT Synchronization Clock
differential pair.
SDVOB Input Interrupt differential pair.
SDVO Field Stall differential pair.
SDVOC Input Interrupt differential pair.
SDVO Channel B Red differential pair.
SDVO Channel B Green differential pair.
SDVO Channel B Blue differential pair.
SDVO Channel B Clock differential pair.
SDVO Channel C Red differential pair.
SDVO Channel C Green differential pair.
SDVO Channel C Blue differential pair.
SDVO Channel C Clock differential pair.
Table 4-3: Intel® SDVO Support Device List
Device
Vander
Application
Link
Page 33
ICE Module
CH7021A
Chrontel
SDTV / HDTV Transmitter
http://www.chrontel.com
CH7308A
Chrontel
LVDS Transmitter
http://www.chrontel.com
CH7307C
Chrontel
DVI Transmitter
http://www.chrontel.com
CH7312
Chrontel
DVI Transmitter
http://www.chrontel.com
CX25905
Conexant
DVI-D / TV / CRT Transmitter
http://www.conexant.com
SiL1362/1364
Silicon Image
DVI Transmitter
http://www.siliconimage.com
SiL 1390
Silicon Image
HDMI Transmitter
http://www.siliconimage.com
4.1.4 PEG_ENABLE#
PEG_ENABLE# is defined on the COM Express connector as a method to configure
the COM Express PCIe lanes 16 through 32 on the C-D connector as a PCI Express
Graphics port, for use with an external graphics device. The usual effect of pulling
PEG_ENABLE# low is to disable the on-Module graphics engine. For some Modules,
it is possible to configure the Module such that the internal graphics engine remains
active, even when the external PEG interface is being used for a Carrier Board
graphics device. This is Module dependent. Check with your vendor. ICE Modules
implement the auto-detect function. So, please reserve this pin for future use.
4.1.5 PCI Express Test Points and Probing
IEI follows the suggestion provided by Intel® to preserve 0-Ω on the baseboard.
Additional test structures were not included in the simulation sweeps that this
guideline is based on. The inclusion of test points and probing structures has the
ability to impact the loss and jitter budgets of a PCI Express interconnect. This is not to
say that they cannot be tolerated. In general, test points and probe structures should
not introduce stubs on the differential pairs or cause significant deviation from the
recommendations given throughout this chapter. Existing vias, pads or pins should be
used wherever possible to accommodate such structures. Careful consideration must
be taken whenever additional probing structures are used.
The PCI Express based specification requires the data eyes to be measured into a
50-Ω resistor terminated to ground. To facilitate the measurement, an additional test
structure may be required on a test board. This test structure should not be included in
a production board because it will affect the overall signal quality and resulting
margins. The three-pad test structure consists of the footprints of two resistors,
perpendicular to each other forming a “L” shape. The resistor package/footprint should
Page 34
ICE Module
be as small as possible, preferably 0402. To enable the test mode, a 50 Ω ±1%
resistor stuffing option is needed to break the path. This will force the transmitter port
to enter the compliance mode and begin transmitting the compliance packet.
Otherwise, use a 0-Ω resistor to continue the trace route to the Rx port. This will allow
normal operation of the device.
Figure 4-2: Intel Recommend Test Structure for PCI Express Data Eye Measurement
4.1.6 PCI Express Routing Guideline
4.1.6.1 Impedance Consideration
The PCI Express impedance considerations are listed in Table 4-4.
Table 4-4: PCI Express Impedance Consideration
Parameters
Transfer Rate / PCIe Lane
Maximum signal line length (coupled traces)
Maximum signal length allowance on the
COM Express module "
Signal length allowance on the COM
Express carrier board "
Differential Impedance
Single-ended Impedance
Trace width (W)
Spacing between differential pairs (intra-pair)
(S)
Spacing between RX and TX pairs
(inter-pair) (s)
Spacing between differential pairs and
Routing
2.5 Gbits/sec
TX and RX path: 21.0 inches
TX and RX path: 5.15 inches
TX and RX path: 15.85 inches @
0.28dB/GHz/inch to PCIe device 9.00 inches
@ 0.28dB/GHz/inch to PCIe slot
100 Ohms +/-20%
55 Ohms +/-15%
5 mils (microstrip routing) (*)
4 mils (microstrip routing) (*)
Min. 20mils
Min. 50mils
Page 35
ICE Module
high-speed periodic signals
Spacing between differential pairs and
low-speed non periodic signals
Length matching between differential pairs
(intra-pair)
Length matching between RX and TX pairs
(inter-pair)
Length matching between reference clock
differential pairs REFCLK+ and REFCLK(intra-pair)
Length matching between reference clock
pairs (inter-pair)
Reference plain
Spacing from edge of plane
Via Usage
AC coupling capacitors
Min. 20mils
Max. 5mils
No strict electrical requirements. Keep
difference within a 3.0 inch delta to minimize
latency.
Max. 5mils
No electrical requirements.
GND referenced preferred
Min. 40mils
Max. 2 vias per TX trace Max. 4 vias per RX
trace
The AC coupling capacitors for the TX lines
are incorporated on the COM Express
module. The AC coupling capacitors for RX
signal lines have to be implemented on the
customer COM Express" carrier board.
Capacitor type: X7R
4.1.6.2 AC Coupling Capacitors
TX AC coupling capacitor is already embedded in the ICE modules. Users only need
to add the RX AC coupling capacitor on the baseboard. The PCI Express specification
requires that each lane of a PCI Express link be AC coupled between the driver and
receiver. The specification allows for the AC coupling capacitors to be located either
on or off the die. However, it is anticipated that in most cases the AC coupling will be
separated from the die and in the form of discrete capacitors on the motherboard itself.
While the 0603 size capacitors are acceptable, size 0402 capacitors are strongly
encouraged. — The smaller package size reduces the series inductance. — The
smaller package size reduces the overall board area needed to place the capacitors.
Page 36
ICE Module
PEG SLOT or SDVO Device
TX+
TX-
ICE Module
AC Coupling Cap
RX+
RX-
Figure 4-3: PEG Lane Connection Topology Example
4.1.6.3 Routing Notices
ƒ
Each signal and its complement in a differential pair should be length
matched whenever possible on a segment-by-segment basis at the point
of discontinuity. Examples of segments might include breakout areas,
routes to connect vias, routes to connect an AC coupling capacitor, routes
to connect a connector, and so forth.
ƒ
When trace length matching occurs, it should be made as close as
possible to the point where the length variation occurs, as shown in Figure
4-4. For example, length matching in a chipset breakout area or connector
pin field should occur within the first 125 mils (3.175 mm) of the structure
that causes the length mismatch.
ƒ
When serpentining is needed to match lengths, the trace spacing should
not become greater than two times the original spacing. The length of the
increased spacing should not be greater than three times the trace width.
See Figure 4-4. In determining the overall length of a given signal in a
differential pair, use pad or pin edge-to-edge distances rather than the
total etch present, unless the amount of trace routing inside each pad is
identical. The amount of etch within a given pad is electrically part of the
pad itself. In other words, only the etch outside of the pad edge is relevant
to the overall length of a differential pair.
Page 37
ICE Module
Preferred Routing
Alternative Routing
Bad Routing
Preferred Routing
Preferred Routing
Figure 4-4: PEG Layout Trace Example
4.2 PCI Express
PCI Express provides a scalable, high-speed, serial I/O point-to-point bus connection.
A PCI Express lane consists of dual simplex channels, each implemented as a
low-voltage differentially driven transmit pair and receive pair. They are used for
simultaneous transmission in each direction. The bandwidth of a PCI Express link can
be scaled by adding signal pairs to form multiple lanes between two devices. The PCI
Express specification defines x1, x4, x8, x16, and x32 link widths. Each single lane
has a raw data transfer rate of 2.5Gbps @ 1.25GHz.
Page 38
ICE Module
The PCI Express interface of the COM Express Type 2 module consists of up to 6
lanes, each with a receive and transmit differential signal pair designated from
PCIE_RX0 (+ and -) to PCIE_RX5 (+ and -) and correspondingly from PCIE_TX0 (+
and -) to PCIE_TX5 (+ and -). According to the PCI Express specification, these six
lanes can be configured as several PCI Express x1 links or to a combined x4 link plus
two x1 links. These configuration possibilities are based on the COM Express
module's chipset capabilities.
4.2.1 Signal Description
Table 4-5: PCI Express Signal Descriptions
Pin
Signal
B68
B69
A68
A69
B64
B65
A64
A65
B61
B62
A61
A62
B58
B59
A58
A59
B55
B56
A55
A56
B52
B53
A52
A53
A88
A98
B66
A49
PCIE_RX0+
PCIE_RX0PCIE_TX0+
PCIE_TX0PCIE_RX1+
PCIE_RX1PCIE_TX1+
PCIE_TX1PCIE_RX2+
PCIE_RX2PCIE_TX2+
PCIE_TX2PCIE_RX3+
PCIE_RX3PCIE_TX3+
PCIE_TX3PCIE_RX4+
PCIE_RX4PCIE_TX4+
PCIE_TX4PCIE_RX5+
PCIE_RX5PCIE_TX5+
PCIE_TX5PCIE_CLK_REF+
PCIE_CLK_REFWAKE0#
EXCD0_CPPE#
B48
EXCD1_CPPE#
A48
EXCD0_PERST#
B47
EXCD1_PERST#
I/O
Description
I
PCIe Port 0. Receive Input differential pair.
O
PCIe Port 0. Transmit Output differential pair.
I
PCIe Port 1. Receive Input differential pair.
O
PCIe Port 1. Transmit Output differential pair.
I
PCIe Port 2,. Receive Input differential pair.
O
PCIe Port 2. Transmit Output differential pair.
I
PCIe Port 3.. Receive Input differential pair.
O
PCIe Port 3. Transmit Output differential pair.
I
PCIe Port 4. Receive Input differential pair.
O
PCIe Port 4. Transmit Output differential pair.
I
PCIe Port 5. Receive Input differential pair.
O
PCIe Port 5. Transmit Output differential pair.
O
PCIe Reference Clock for all COM Express
PCIe lanes, and for PEG lanes
PCIe Wake Event: Sideband wake-up signal.
ExpressCard capable card request, slot 1.
I PCIE
I 3.3V
CMOS
I 3.3V
CMOS
O 3.3V
CMOS
O 3.3V
CMOS
ExpressCard capable card request, slot 2.
ExpressCard reset, slot 1.
ExpressCard reset, slot 2.
Page 39
ICE Module
4.2.2 PCI Express Slot X1
Table 4-5 illustrates the pinout definition for the standard x1, x4, x8 and x16 PCI
Express connectors. The dashed lines in the diagram depict where each different
connector type ends. An example of an x1 PCIe slot is shown in Figure 4-5 below.
+V3.3
+V12
+V12
+V3.3_DUAL
3,4,6,10,11,17,20 SMB_CK
3,4,6,10,11,17,20 SMB_DAT
PCIE_WAKE_UP#
3
3
PCIE_TX1+
PCIE_TX1-
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
PCIE1
+12V03
+12V04
RSVD01
GND05
SMBCLK
SMBDATA
GND06
3_3V03
JTAG1
3_3VAUX
WAKE#
PRSNT1#
+12V01
+12V02
GND01
JTAG2
JTAG3
JTAG4
JTAG5
3_3V01
3_3V02
PWRGD
RSVD02
GND02
GND07
REFCLK+
HSOP0
REFCLKHSON0
GND03
GND08
HSIP0
PRSNT2#
HSIN0
GND09 NC1 NC2
GND04
NC1 NC2
PCIE_X1
+V3.3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
CB_RESET# 3,6,10,11,14,20
CLK100M_PCIEx1_SLOT2+ 4
CLK100M_PCIEx1_SLOT2- 4
0_4 2
0_4 2
1 R124
1 R125
1
1
PCIE_RX1+
PCIE_RX1-
3
3
TP90
TP91
Figure 4-5: PCI Express x1 Slot Example
4.2.3
Express Card Connector
Hot-swappable Express Cards come in a small form factor and are designed primarily
for mobile computing. The card’s electrical interface is thru USB 2.0 or a single x1
PCIe link. Express Cards are the successor to Card Bus Cards (which are PCI-based).
Card Bus cards, in turn, are the successors to PCMCIA cards. All three formats are
defined by the PCMCIA Consortium.
ExpressCard is a small, modular add-in card designed to replace common PCMCIA
and PC Cards. It takes advantage of the scalable, high-bandwidth serial PCI Express
and USB 2.0 interfaces to provide much higher data rates. COM Express modules
offer support for up to two ExpressCard slots. More information about the
ExpressCard Standard can be found at http://www.expresscard.org.
In addition to the signals of a PCI Express x1 link and a USB 2.0 link, the ExpressCard
interface requires the following control signals provided by the COM Express module.
The corresponding signals can be found on the module connector rows A and B.
Page 40
ICE Module
R350
+V3.3
C26
3,6,10,11,14,20 CB_RESET#
+V3.3
+V3.3
10K_4 1
10K_4 1
+V3.3_ExpressCard
+V3.3_ExpressCard
+V3.3
+V3.3_DUAL
+V1.5
10U_8_X_6V3
1
2
3
4
5
6
7
8
9
10
2 R73
2 R74
PERST#
TPS2231
U3
SY SRST#
SHDN#
STBY #
3.3VIN1
3.3VIN2
3.3VOUT1
3.3VOUT2
PERST#
NC
GND
OC#
RCLKEN
AUXIN
AUXOUT
1.5VIN2
1.5VIN1
1.5VOUT2
1.5VOUT1
CPPE#
CPUSB#
470_6
R360
1
1
TP41
TP42
C
LEDRED_8_2
C27
0.1U_4_Y _16V
+V3.3SB_ExpressCard
+V1.5_ExpressCard
+V1.5_ExpressCard
CPPE#
CPUSB#
TPS2231
+V1.5
Q1
GS1117-SOT223
<Output Current Capability >
O
V_IN
V_OUT 4
V_OUT1
C
LEDRED_8_2
LED7
A
+V3.3SB_ExpressCard
470_6
20
19
18
17
16
15
14
13
12
11
LED6
A
+V3.3_ExpressCard
E_Card_CON1
R75
124 1%-RS
C30
10U_8_X_6V3
3
3
PCIE_RX2+
PCIE_RX2-
4 CLK100M_PCIEx1_SLOT3+
4 CLK100M_PCIEx1_SLOT3R76
24.9 1%-RS
+V3.3_ExpressCard
+V3.3_ExpressCard
+V1.5_ExpressCard
+V3.3SB_ExpressCard
PERST#
PCIE_WAKE_UP#
+V1.5_ExpressCard
EC9
P15
P14
P13
P12
P11
P10
P7
P6
P5
+V3.3_ExpressCard
C35
0.1U_4_Y _16V
P19
P18
P17
P16
P9
P8
3,4,6,10,11,17,20 SMB_DAT
3,4,6,10,11,17,20 SMB_CK
C37
@150U_TNC_SMD_6.3V 0.1U_4_Y _16V
EC10
CPPE#
+V3.3SB_ExpressCard
C36
10U_8_X_6V3
@150U_TNC_SMD_6.3V
CPUSB#
L2
3
USB6+
3
USB6-
3
4
2
1
P4
P3
P2
P1
GND4
PETp0
PETn0
GND3
PERp0
PERn0
GND2
REFCLK+
REFCLKCPPE#
CLKREQ#
H2
H1
G
C28
C29
10U_8_X_6V3 0.1UF
P26
P25
P24
P23
P22
P21
P20
PCIE_TX2+
PCIE_TX2-
H2
3
3
GND
I
H1
VCC1.5/1A
+3.3V2
+3.3V1
PERST#
+3.3VAUX
WAKE#
+1.5V
SMB_DATA
SMB_CLK
RESERVED3
RESERVED2
RESERVED1
CPUSB#
USB_D+
USB_DGND1
COMCHOKE_8_USB
C38
0.1U_4_Y _16V
Express Card connector
Figure 4-6: Express Card Slot Example
Table 4-6: Express Card Pin Definition
Pin
Signal
I/O
1
2
3
4
5
6
7
8
9
10
GND
USB_DUSB_D+
CPUSB#
RSVD
RSVD
SMBCLK
SMBDATA
+1.5V
+1.5V
I/O 3.3V
I/O 3.3V
P 1.5V
P 1.5V
11
WAKE#
I 3.3V
12
13
14
15
16
17
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
P 3.3V
I 3.3V
P 3.3V
P 3.3V
I 3.3V
I 3.3V
18
REFCLK-
I PCIe
19
20
21
22
REFCLK+
GND
PERn0
PERp0
I PCIe
P
I/O PCIe
I/O PCIe
P
I/O USB
I/O USB
I 3.3V
Description
Ground
USB Serial Data Interface differential pair, negative signal
USB Serial Data Interface differential pair, positive signal
USB Interface presence detected
Reserved
Reserved
System Management Bus Clock
System Management Bus Data
Secondary voltage source, 1.5V
Secondary voltage source, 1.5V
Request that the host interface return to full operation and
respond to PCIe
Auxiliary voltage source, 3.3V
PCI Express Reset
Primary voltage source, 3.3V
Primary voltage source, 3.3V
Request that REFCLK be enabled
PCI Express interface presence detect
PCI Express reference clock differential pair, negative
signal
PCI Express reference clock differential pair, positive signal
Ground
PCI Express Receiver differential pair negative signal
PCI Express Receiver differential pair positive signal
Page 41
ICE Module
23
24
25
26
GND
PETn0
PETp0
GND
P
I/O PCIe
I/O PCIe
P
Ground
PCI Express Transmitter differential pair negative signal
PCI Express Transmitter differential pair positive signal
Ground
The PCMCIA Consortium defines two form factors for Express Cards:
ƒ
Express Card/34 and Express Card/54 use a socket-style interconnect.
ƒ
There are two mechanical Form Factors with Express Card/34, which
are useable in either socket. Each has the same electrical interface.
ƒ
Interface support for a PCIe x1 lane and USB 2.0 on the socket is
required.
ƒ
Socket interface requirements for Carrier Boards include:
ƒ
PCIe x1 Lane and USB 2.0
ƒ
WAKE# and the SM Bus are optional at the socket and COM Express
Module level.
Figure 4-7: Express Card 54&34 Type (Refer to www.expresscard.org)
Page 42
ICE Module
Figure 4-8: Express Card 54 & 34 Plug Way (Refer to www.expresscard.org)
4.2.4 PCIe Mini Card
The PCI Express Mini Card add-in card is a small size unique form factor optimized for
mobile computing platforms equipped with communication applications such as
Wireless LAN. A small footprint connector can be implemented on the carrier board
providing the ability to insert different removable PCI Express Mini Cards. Using this
approach gives the flexibility to mount an upgradeable, standardized PCI Express Mini
Card device to the carrier board without additional expenditure of a redesign. In
addition to a PCI Express x1 link and a USB 2.0 link, the PCI Express Mini Card
interface utilizes the following control and reset signals, which are provided by the
COM Express module connector rows A and B.
Page 43
ICE Module
1
1
TP96 3
TP97 3
PCIE_RX3+
PCIE_RX3-
4 CLK33M_MINICARD
3,6,10,11,14,20 CB_RESET#
PCIE_TX3+
PCIE_TX30_4 2
0_4 2
1 R122
1 R123
0_4 2
0_4 2
1 R70
1 R72
4 CLK100M_PCIEx1_SLOT4+
4 CLK100M_PCIEx1_SLOT4TP40
3,6,10,16 PCIE_WAKE_UP#
1
PCIE_WAKE_UP#
15
13
11
9
7
5
3
1
GND2
REFCLK+
REFCLKGND1
CLKREQ#
RESERVED_2
RESERVED_1
WAKE#
53
CN1(LATCH)1
+V3.3
54
RESERVED_10
RESERVED_9
RESERVED_8
RESERVED_7
RESERVED_6
RESERVED_5
RESERVED_4
RESERVED_3
GND9
PETp0
PETn0
GND7
GND6
PERp0
PERn0
GND4
UIM_C4
UIM_C8
G1
3
3
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
G2
CN1
3.3V_2
GND11
1.5V_3
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND10
USB_D+
USB_DGND8
SMB_DATA
SMB_CLK
1.5V_2
GND5
3.3VAUX1
PERST#
W_DISABLE#
GND3
UIM_VPP
UIM_RESET
UIM_CLK
UIM_DATA
UIM_PWR
1.5V_1
GND0
3.3V_1
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
1
1
+V1.5
TP38
TP39
L1
4
SMB_DAT
SMB_CK
1
COMCHOKE_8_USB
3
USB7+
2
USB7-
3
3
+V1.5
CB_RESET#
R71
+V3.3_DUAL
8.2K_4
+V1.5
+V3.3
MINICARD_DISABLE# 13
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
3,11,13,14,20
3,11,13,14,20
3,11,13,14,20
3,11,13,14,20
3,11,13,14,20
+V3.3
MINI PCIE CON_9MM_0.8
MINI PCIE LATCH_DIP
Figure 4-9: Express Card Slot Example
The following sections illustrate signal pin-outs for the system connector. Table 4-7
lists the pin-out for the system connector.
Table 4-7: Mini Card Pin-out
Pin #
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
Page 44
Signal
Reserved*
Reserved*
Reserved*
Reserved*
Reserved*
Reserved*
Reserved*
Reserved*
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
Reserved
Reserved
GND
REFCLK+
REFCLKGND
CLKREQ#
Pin #
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
Mechanical Key
16
14
12
10
8
Signal
+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
Reserved***
GND
Reserved**
Reserved**
Reserved**
Reserved**
Reserved**
ICE Module
5
3
1
Reserved****
Reserved****
WAKE#
6
4
2
1.5V
GND
3.3V
* Reserved for future second PCI Express Lane (if needed)
** Reserved for future Subscriber Identity Module (SIM) interface (if needed)
*** Reserved for future wireless disable signal (if needed)
**** Reserved for future wireless coexistence control interface (if needed)
Figure 4-10: Mini Card Bottom Side Dimensions (Refer to www.pcisig.com)
Figure 4-11: Mini Card Top Side Dimensions (Refer to www.pcisig.com)
Page 45
ICE Module
Figure 4-12: Mini Card Connector (Refer to www.pcisig.com)
4.2.5 PCI Express Clock Buffer
COM Express only provides a set of 100 MHz Clock for PCI Express Device. When
there are more than one PCI Express modules used on the baseboard, the Clock
Buffer must be used. Please refer to the schematic diagram (Figure 4-13) suggested
by IEI.
+V3.3_CLK_A
+V3.3_CLK
+V3.3_CLK
U1
CLK_DIV#
3 CLK100M_PCIE_REF+
3 CLK100M_PCIE_REF5 CLK100M_PCIEx1_SLOT1+
5 CLK100M_PCIEx1_SLOT15 CLK100M_PCIEx1_SLOT2+
5 CLK100M_PCIEx1_SLOT25 CLK100M_PCIEx1_SLOT3+
5 CLK100M_PCIEx1_SLOT35 CLK100M_PCIEx1_SLOT4+
5 CLK100M_PCIEx1_SLOT4-
CLK_OE_0
CLK_OE_3
R16
R18
2
2
1 33_4
1 33_4
R20
R21
2
2
1 33_4
1 33_4
R22
R23
2
2
1 33_4
1 33_4
R25
R27
2
2
1 33_4
1 33_4
CLK_OE_1
CLK_OE_2
CLK_PLL
3,5,6,10,11,17,20 SMB_CK
3,5,6,10,11,17,20 SMB_DAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SRC_DIV#
VDD01
GND01
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
GND02
VDD02
DIF_1
DIF_1#
OE_1
OE_2
DIF_2
DIF_2#
GND03
VDD03
DIF_3
DIF_3#
BY PASS#/PLL
SCLK
SDATA
VDDA
GNDA
IREF
LOCK
OE_7
OE_4
DIF_7
DIF_7#
OE_INV
VDD04
DIF_6
DIF_6#
OE_6
OE_5
DIF_5
DIF_5#
GND04
VDD05
DIF_4
DIF_4#
HIGH_BW#
SRC_SOP#
PD#
GND05
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK_IREF
CLK_LOCK
CLK_OE_7
CLK_OE_4
1
1
ICS9DB801
Figure 4-13: PCI Express Clock Buffer Example
4.2.5.1 PCI Express Routing Guideline
Please refer to Section 4.1.6
Page 46
R10
475
TP32
TP33
R114
R115
CLK_OE_6
CLK_OE_5
R112
R113
2
2
1 33_4
1 33_4
2
2
1 33_4
1 33_4
33_4 1
33_4 1
CLK_HBW#
CLK_SRC_SOP#
CLK_PD#
2 R24
2 R26
CLK100M_PCIEx1_SLOT6+ 10
CLK100M_PCIEx1_SLOT6- 10
CLK100M_PCIEx1_SLOT5+ 10
CLK100M_PCIEx1_SLOT5- 10
CLK100M_PCIEx16_SLOT+ 6
CLK100M_PCIEx16_SLOT- 6
ICE Module
4.3 PCI
The COM Express provides a PCI Bus interface that is compliant with the PCI Local
Bus Specification, Revision 2.2. The implementation is optimized for high-performance
data streaming when the COM Express is acting as either the target or the initiator on
the PCI bus. For more information on the PCI Bus interface, refer to the PCI Local Bus
Specification, Revision 2.2.
4.3.1 Signal Description
Table 4-8 shows COM Express PCI bus signal, including pin number, signals, I/0,
power plane, terminal resistors, damping resistors and descriptions.
Table 4-8: PCI Signal Description
Pin
Signal
I/O
Description
Note1
Note1
C36
D36
C37
D35
D34
D32
C34
PCI_AD[0..31]
PCI_C/BE[0..3]#
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_PERR#
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
Note1
Note1
C23
C35
D33
PCI_REQ[0..3]#
PCI_GNT[0..3]#
PCI_RESET#
PCI_LOCK#
PCI_SERR#
I 3.3V
O 3.3V
O 3.3V
I/O 3.3V
I/O 3.3V
C15
PCI_PME#
I 3.3VSB
D48
PCI_CLKRUN#
I/O 3.3V
Note1
D50
D49
PCI_IRQ[A..D]#
PCI_CLK
PCI_M66EN
I 3.3V
O 3.3V
I 3.3V
PCI bus multiplexed address and data lines
PCI bus byte enable lines , active low
PCI bus Device Select, active low.
PCI bus Frame control line, active low.
PCI bus Initiator Ready control line, active low.
PCI bus Target Ready control line, active low.
PCI bus STOP control line, active low.
PCI bus parity
Parity Error: An external PCI device drives PERR# to
low, when it receives data that has a parity error.
PCI bus master request input line, active low.
PCI bus master grant output lines, active low.
PCI Reset output, active low.
PCI Lock control line, active low.
System Error: SERR# may be pulsed active by any
PCI device that detects a system error condition.
PCI Power Management Event: PCI peripherals drive
PME# to low to wake up the system from low-power
states S1–S5.
Bidirectional pin used to support PCI clock run
protocol for mobile systems.
PCI interrupt request lines.
PCI 33MHz clock output.
Module input signal that indicates whether an carrier
board PCI device is capable of 66MHz operation. It is
pulled to ground by carrier board device or by slot
card, if one of the devices are NOT capable of
66MHz operation.
Please refer to Table 3-3: Module Type 2 Connector Pinout Rows (A and B) or
Table 3-4: Module Type 2 Connector Pinout Rows (C and D).
Page 47
ICE Module
4.3.2 PCI Connector
The PCI slot connection is shown in Figure 4-14.
3,8,9 PCI_AD[0..31]
+V3.3
+V5
+V5
-V12
2
1
5.6K_4
3,8 PCI_INT#B
3
PCI_INT#D
C51
0.1U_4_Y _16V
C50
0.1U_4_Y _16V
4 CLK33M_SLOT1
3
PCI_REQ#1
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
3,8,9 PCI_C/BE#3
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
3,8,9 PCI_C/BE#2
3,8,9 PCI_IRDY #
3,8 PCI_DEVSEL#
3
PCI_LOCK#
3,8 PCI_PERR#
3,8
PCI_SERR#
3,8,9 PCI_C/BE#1
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
+V5
8.2K_4
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PCI1
-12V
TCK
GND11
TDO
+5V07
+5V08
INTB#
INTD#
PRSNT1#01
RSVD03
PRSNT1#02
GND12
GND13
RSVD04
GND14
CLK
GND15
REQ#
+5V09
AD31
AD29
GND16
AD27
AD25
+3.3V07
C/BE3#
AD23
GND17
AD21
AD19
+3.3V08
AD17
C/BE2#
GND18
IRDY #
+3.3V09
DEVSEL#
GND19
LOCK#
PERR#
+3.3V10
SERR#
+3.3V11
C/BE1#
AD14
GND20
AD12
AD10
GND21
TRST#
+12V
TMS
TDI
+5V01
INTA#
INTC#
+5V02
RSVD
+5V03
RSVD02
GND01
GND02
3.3VAUX
RST#
+5V04
GNT#
GND03
PME#
AD30
+3.3V01
AD28
AD26
GND04
AD24
IDSEL
+3.3V02
AD22
AD20
GND05
AD18
AD16
+3.3V03
FRAME#
GND06
TRDY #
GND07
STOP#
+3.3V04
SMBCLK
SMDATA
GND08
PAR
AD15
+3.3V05
AD13
AD11
GND09
AD9
AD8
AD7
+3.3V12
AD5
AD3
GND22
AD1
+5V10
ACK64#
+5V11
+5V12
X1
C/BE0#
+3.3V06
AD6
AD4
GND10
AD2
AD0
+5V05
REQ64#
+5V
+5V06
X1
X2
R85
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
X2
R77
+V12
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
+V3.3
+V3.3_DUAL
PCI_INT#A
PCI_INT#C
PCI_RST#
PCI_PME#
PCI_AD30
3,8
3
3,8,9,13
PCI_GNT#1
3
PCI_PME#
3,8
PCI_AD28
PCI_AD26
PCI_AD24
R79
PCI_AD22
PCI_AD20
1
PCI_AD20
2
100_4_1%
PCI_AD18
PCI_AD16
PCI_FRAME# 3,8,9
10K_4
10K_4
PCI_AD15
PCI_TRDY #
3,8
PCI_STOP#
3,8
R81
R83
+V3.3
PCI_PAR
3,8
PCI_C/BE#0
3,8,9
PCI_AD13
PCI_AD11
PCI_AD9
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
+V5
R86
8.2K_4
PCISLOT120_2.54
Figure 4-14: PCI Slot Connection Example
4.3.3 PCI IRQ Assignment
Most of this PCI devices only utilize the interrupt signal 'INTA#'. To distribute the
interrupt source of the devices over the interrupt signals 'INTB#', 'INTC#' and 'INTD#',
an interrupt cross routing has to be implemented on the COM Express carrier board
design. Figure 5-14 and Table 5-16 illustrate the PCI bus interrupt routing for the PCI
bus slots 1-4. The PCI REQ and GNT lines with the same index must be considered
Page 48
ICE Module
as a pair. It is not permitted to combine REQ and GNT lines with a different index. A
PCI REQ/GNT pair can only be used once for a single PCI bus-master device.
Table 4-9: PCI Slot Routing Table
IDSEL
Slot1
PCI_AD[20]
Slot2
PCI_AD[21]
Slot3
PCI_AD[22]
Slot4
PCI_AD[23]
INTA#
INTB#
INTC#
INTD#
PCI_IRQ[A]#
PCI_IRQ[B]#
PCI_IRQ[C]#
PCI_IRQ[D]#
PCI_IRQ[B]#
PCI_IRQ[C]#
PCI_IRQ[D]#
PCI_IRQ[A]#
PCI_IRQ[C]#
PCI_IRQ[D]#
PCI_IRQ[A]#
PCI_IRQ[B]#
PCI_IRQ[D]#
PCI_IRQ[A]#
PCI_IRQ[B]#
PCI_IRQ[C]#
Figure 4-15: PCI Slot Routing Example
Page 49
ICE Module
4.3.4 PCI Clock Buffer
The COM Express Specification only supports a single PCI clock signal called
'PCI_CLK' to be used on the carrier board. If there are multiple devices or slots
implemented on the carrier board, a zero delay clock buffer is required to expand the
number of PCI clocks so that each device or each bus slot will be provided with a
separate clock signal.
PCI Clock Buffer
@33_41
3 CLK33M_PCI
8 CLK33M_MINIPCI
7 CLK33M_SLOT3
9 CLK33M_80PORT
20 CLK33M_BIOS2
11 CLK33M_TPM
+V3.3
C15
10U_8_X_6V3
2 R34
U2
V1.01 Modify
FB3
FB30_8_3A
C16
10U_8_X_6V3
R37
R40
2
2
1
2
3
4
5
6
7
8
1 33_4
1 33_4
+V3.3_CLKBUFFER
R44
R47
R51
2
2
1 33_4
1 33_4
CLKBUFFER_S2
2
REF
CLKOUT
CLKA1 CLKA4
CLKA2 CLKA3
VDD
VDD
GND
GND
CLKB1 CLKB4
CLKB2 CLKB3
S2
S1
16
15
14
13
12
11
10
9
33_4 1
33_4 1
2 R38
2 R41
+V3.3_CLKBUFFER
33_4 1
33_4 1
CLKBUFFER_S1
2 R45
2 R48
CLK33M_SLOT1 7
CLK33M_SLOT2 7
CLK33M_SIO2 14
CLK33M_MINICARD 5
CY 2309NZSXC-1H
1 33_4
CLK33M_SLOT1
C10
1
2 10P_4_N_50V
CLK33M_SLOT2
C11
1
2 10P_4_N_50V
CLK33M_SLOT3
C13
1
2 10P_4_N_50V
CLK33M_SIO2
C241 1
2 10P_4_N_50V
CLK33M_BIOS2
C265 1
2 10P_4_N_50V
CLK33M_TPM
C266 1
2 10P_4_N_50V
CLK33M_MINICARD C267 1
2 10P_4_N_50V
CLK33M_80PORT
C14
1
2 10P_4_N_50V
CLK33M_MINIPCI
C12
1
2 10P_4_N_50V
+V3.3_CLKBUFFER
C17
C18
0.1U_4_Y _16V 0.1U_4_Y _16V
+V3.3_CLK
10K_4 1
@10K_4 1
2 R62
2 R63
CLKBUFFER_S1
+V3.3_CLK
10K_4 1
@10K_4 1
2 R65
2 R67
CLKBUFFER_S2
Figure 4-16: PCI Clock Buffer Example
4.3.5 PCI Routing Guideline
Particular attention must be paid to the PCI clock routing. The PCI Local Bus
specification requires a maximum propagation delay for the clock signals of 10ns
within a propagation skew of 2ns @ 33MHz between the several clock signals. The
COM Express Specification allows 1.6ns ± 0.1ns @ 33MHz propagation delay for the
PCI clock signal beginning from the module pin to the destination pin of the PCI device.
The propagation delay is dependent on the trace geometries, PCB stack-up and the
PCB dielectric constant. Calculating using a typical propagation delay value of
180ps/inch for an internal layer clock trace of the carrier board, a maximum trace
length of 8.88 inches is allowed.
The clock trace from the COM Express module to a PCI bus slot should be 2.5 inches
shorter because PCI cards are specified to have 2.5 inches of clock trace length on
the card itself. PCI clock signals should be routed as a single ended trace with a trace
impedance of 55Ω. To reduce EMI, a single ground referenced internal layer is
recommended. The clock traces should be separated as far as possible from other
Page 50
ICE Module
signal traces. Refer to section 8.1 'PCI Trace Routing Guidelines' and the 'PCI Local
Bus Specification Revision 2.3' to get more information about this subject.
Table 4-10: PCI Impedance Consideration
Parameters
Routing
Transfer Rate @ 33MHz
Signal length used on COM Express module
(including the COM Express" carrier board
connector) "
Maximum data and control signal length
allowance for the COM Express carrier board. "
Maximum clock signal length allowance for the
COM Express carrier board. "
Single-ended Impedance
Trace width (W)
Spacing between signals (inter-signal) (S)
Length matching between single ended signals
Length matching between clock signals
Spacing from edge of plane
Reference plain
Via Usage
132 MB/sec
Decoupling capacitors for each PCI slot.
3.0 inches
10 inches
8.88 inches
55 Ohms +/-15%
5mils (microstrip routing) (*)
7mils (microstrip routing) (*)
Max. 200mils
Max. 200mils
Min. 40mils
GND referenced preferred
Try to minimize number of vias
Min. 1x22μF, 2x 100nF @ VCC 5V Min.
2x22μF, 4x 100nF @ VCC 3.3V Min.
1x22μF, 2x 100nF @ +12V (if used) Min.
1x22μF, 2x 100nF @ -12V (if used)
4.4 SATA (Serial ATA Interface)
Serial ATA is a serial interface for connecting storage devices (mainly hard disks) and
was defined to replace the old parallel ATA interface. SATA uses a point-to-point serial
connection between the system and the storage device. The first generation of
standard SATA provides a maximum effective data transfer rate of 150 MB/s per port.
With the second generation SATA II, an effective transfer rate of up to 300 MB/s per
port is possible. Serial ATA is completely software transparent to the IDE interface
while providing a lower pin count and higher performance.
4.4.1 Signal Description
All COM Express modules provide up to 4 Serial ATA channels, each with a receive
and transmit differential signal pair designated from 'SATA0_RX' (+ and -) to
'SATA3_RX' (+ and -) and correspondingly from 'SATA0_TX' (+ and -) to 'SATA3_TX'
(+ and -). The appropriate signals can be found on the COM Express module
connector row A and row B.
Page 51
ICE Module
Table 4-11: Serial ATA Signal Descriptions
Pin
Signal
I/O
Description
A19
A20
A16
A17
B19
B20
B16
B17
A25
A26
A22
A23
B25
B26
B22
B23
A28
SATA0_RX+
SATA0_RXSATA0_TX+
SATA0_TXSATA1_RX+
SATA1_RXSATA1_TX+
SATA1_TXSATA2_RX+
SATA2_RXSATA2_TX+
SATA2_TXSATA3_RX+
SATA3_RXSATA3_TX+
SATA3_TXSATA_ACT#
I SATA
Serial ATA channel 0 Receive input differential pair.
O SATA
Serial ATA channel 0 Transmit output differential pair.
I SATA
Serial ATA channel 1 Receive input differential pair.
O SATA
Serial ATA channel 1 Transmit output differential pair.
I SATA
Serial ATA channel 2 Receive input differential pair.
O SATA
Serial ATA channel 2 Transmit output differential pair.
I SATA
Serial ATA channel 3 Receive input differential pair.
O SATA
Serial ATA channel 3 Transmit output differential pair.
O 3.3V
CMOS OC
Serial ATA activity LED. Open collector output pin driven
during SATA command activity.
4.4.2 SATA Connector
Each ICE module provides four SATA port at maximum. Users can use these SATA
ports for their applications. Figure 4-17 shows the standard SATA port connection.
S_ATA1
SATA_1X7_1
8 GND1
8 A+
A9
GND2
9
BB+
GND3
S_ATA3
SATA_1X7_1
8 GND1
8 A+
A9
GND2
9
BB+
GND3
1
2
3
4
5
6
7
S_ATA2
SATA_1X7_1
SATA0_TX+
SATA0_TXSATA0_RXSATA0_RX+
SATA0_TX+ 3
SATA0_TX- 3
SATA0_RX- 3
SATA0_RX+ 3
8 GND1
8 A+
A9
GND2
9
BB+
GND3
S_ATA4
SATA_1X7_1
1
2
3
4
5
6
7
SATA1_TX+
SATA1_TXSATA1_RXSATA1_RX+
SATA1_TX+ 3
SATA1_TX- 3
SATA1_RX- 3
SATA1_RX+ 3
8 GND1
8 A+
A9
GND2
9
BB+
GND3
Figure 4-17: SATA 7-pin Connector Example
Page 52
1
2
3
4
5
6
7
1
2
3
4
5
6
7
SATA2_TX+
SATA2_TXSATA2_RXSATA2_RX+
SATA3_TX+
SATA3_TXSATA3_RXSATA3_RX+
SATA2_TX+ 3
SATA2_TX- 3
SATA2_RX- 3
SATA2_RX+ 3
SATA3_TX+ 3
SATA3_TX- 3
SATA3_RX- 3
SATA3_RX+ 3
ICE Module
4.4.3 SATA LED#
The SATA LED can be used with the HDD LED. Please refer to the following
schematic diagram.
+V3.3
R322
4.7K
R323
4.7K
D17
HDD_LED#
11,21 HDD_LED#
3,21 ATA_ACT#
K1
K2
1
LED1
3
C
C
A
R324
470_6_5% +V5
LEDRED_8_2
2
BAW56LT1_SOT23
Figure 4-18: SATA LED Connection Example
4.4.4 SATA Routing Guideline
Table 4-12: SATA Impedance Consideration
Parameters
Transfer Rate
Maximum signal line length (coupled traces)
Signal length used on COM Express module
(including the COM Express" carrier board
connector) "
Signal length available for the COM Express
carrier board "
Differential Impedance
Single-ended Impedance
Trace width (W)
Spacing between differential pairs (intra-pair)
(S)
Spacing between RX and TX pairs
(inter-pair) (s)
Spacing between differential pairs and
high-speed periodic signals
Spacing between differential pairs and
low-speed non periodic signals
Length matching between differential pairs
(intra-pair)
Length matching between RX and TX pairs
(inter-pair)
Spacing from edge of plane
Via Usage
AC Coupling capacitors
Routing
3.0 Gbits/sec
7.0 inches on PCB (COM Express module
and carrier board. The length of the SATA
cable is specified between 0 and 40 inches) "
2.5 inches
4.5 inches
100 Ohms +/-20%
55 Ohms +/-15%
5mils (microstrip routing) (*)
7mils (microstrip routing) (*)
Min. 20mils
Min. 50mils
Min. 20mils
Max. 5mils
No strict electrical requirements. Keep
difference within a 3.0 inch delta to minimize
latency. Do not serpentine to meet trace
length guidelines for the RX and TX path.
Min. 40mils
Try to minimize number of vias
The AC coupling capacitors for the TX and
RX lines are incorporated on the COM
Express module. "
Page 53
ICE Module
4.5 Universal Serial Bus (USB)
The Universal Serial Bus (USB) provides a bi-directional, isochronous, hot-attachable
Plug and Play serial interface for adding external peripheral devices such as game
controllers, communication devices and input devices on a single bus. A COM
Express Module must provide a minimum of four USB ports and can support up to
eight USB ports.
USB stands for Universal Serial Bus, an industry-standard specification for attaching
peripherals to a computer. It delivers high performance, the ability to plug in and
unplug devices while the computer is running, great expandability, and a wide variety
of solutions.
The USB physical topology consists of connecting the downstream hub port to the
upstream port of another hub or to a device. The USB can operate at three speeds.
High-speed (480 Mb/s) and full-speed (12 Mb/s) require the use of a shielded cable
with two power conductors and twisted pair signal conductors. Low-speed (1.5 Mb/s)
recommends, but does not require the use of a cable with twisted pair signal
conductors. The connectors are designed to be hot plugged. The USB Icon on the
plugs provides tactile feedback making it easy to obtain proper orientation.
4.5.1 Signal Description
Table 4-13 shows COM Express USB signals, including pin number, signals, I/0,
power plane, terminal resistors, damping resistors and descriptions.
Table 4-13: USB Signal Description
Pin
Signal
I/O
Description
A46
A45
USB0+
USB0-
I/O
USB Differential Data Port 0.
B46
B45
USB1+
USB1-
I/O
USB Differential Data Port 1.
A43
A42
USB2+
USB2-
I/O
USB Differential Data Port 2.
B43
B42
USB3+
USB3-
I/O
USB Differential Data Port 3.
A40
A39
USB4+
USB4-
I/O
USB Differential Data Port 4.
B40
B39
USB5+
USB5-
I/O
USB Differential Data Port 5.
A37
A36
USB6+
USB6-
I/O
USB Differential Data Port 6.
Page 54
ICE Module
B37
B36
USB7+
USB7-
I/O
USB Differential Data Port 7.
B44
USB_0_1_OC#
I 3.3V CMOS
A44
USB_2_3_OC#
I 3.3V CMOS
B38
USB_4_5_OC#
I 3.3V CMOS
USB over-current sense, USB ports 0 and 1. A pull-up for this
line shall be present on the module. An open drain driver from
a USB current monitor on the Carrier Board may drive this
line low. Do not pull this line high on the Carrier Board.
USB over-current sense, USB ports 2 and3. A pull-up for this
line shall be present on the module. An open drain driver from
a USB current monitor on the Carrier Board may drive this
line low. Do not pull this line high on the Carrier Board.
USB over-current sense, USB ports 4 and 5. A pull-up for this
line shall be present on the module. An open drain driver from
a USB current monitor on the Carrier Board may drive this
line low. Do not pull this line high on the Carrier Board.
4.5.2 USB Keyed Connector Protocol
To minimize end user termination problems, USB uses a “keyed connector” protocol.
The physical difference in the Series “A” and “B” connectors insures proper end user
connectivity. The “A” connector is the principle means of connecting USB devices
directly to a host or to the downstream port of a hub. All USB devices must have the
standard Series “A” connector specified in this chapter. The “B” connector allows
device vendors to provide a standard detachable cable. This facilitates end user cable
replacement.
Figure 4-19: Keyed Connector Protocol (Refer to USB2.0 Spec.)
Page 55
ICE Module
The following list explains how the plugs and receptacles can be mated:
ƒ
Series “A” receptacle mates with a Series “A” plug. Electrically, Series “A”
receptacles function as outputs from host systems and/or hubs.
ƒ
Series “A” plug mates with a Series “A” receptacle. The Series “A” plug
always is oriented towards the host system.
ƒ
Series “B” receptacle mates with a Series “B” plug (male). Electrically,
Series “B” receptacles function as inputs to hubs or devices.
ƒ
Series “B” plug mates with a Series “B” receptacle. The Series “B” plug is
always oriented towards the USB hub or device.
USB connector usually used connector of Type A.
Figure 4-20: USB Connector
Table 4-14: USB Connector Signal Description
Pin
Signal
I/O
Description
1
VCC
P
+5V Power supply
2
DATA-
I/O
USB Data, negative differential signal.
3
DATA+
I/O
USB Data, positive differential signal.
4
GND
P
Ground
Page 56
ICE Module
4.5.3 ESD/EMI
To improve the EMI behavior of the USB interface, a design should include common
mode chokes, which have to be placed as close as possible to the USB connector
signal pins. Common mode chokes can provide required noise attenuation but they
also distort the signal quality of full-speed and high-speed signaling. Therefore,
common mode chokes should be chosen carefully to meet the requirements of the
EMI noise filtering while retaining the integrity of the USB signals on the carrier board
design.
To protect the USB host interface of the module from over-voltage caused by
electrostatic discharge (ESD) and electrical fast transients (EFT), low capacitance
steering diodes and transient voltage suppression diodes have to be implemented on
the carrier board design.
USB0-_R 1
IO_GND
D10
USB1-_R
6
5 +V5_USB01
2
USB0+_R 3
USB1+_R
4
PACDN006
Figure 4-21: RailClamp SRV05-4 Low Capacitance TVS Diode Array for ESD
USB1-_R
USB1+_R
COMCHOKE_8_USB
1
2
4
3
USB1-
3
USB1+
3
L17
Figure 4-22: 90 ohm Common Mode Choke at 100MHz for EMI
Page 57
ICE Module
4.5.4 Over Current Protection
Over-current protection for USB ports can be implemented by using power distribution
switches on the carrier board that monitor the USB port power lines. Power distribution
switches usually have a soft-start circuitry that minimizes inrush current in applications
where highly capacitive loads are employed. Transient faults are internally filtered.
Additionally, they offer a fault status output that is asserted during over-current and
thermal shutdown conditions. These outputs should be connected to the
corresponding COM Express modules USB over-current sense signals. IEI uses
MIC2026 for carrier board.
Figure 4-23: MIC2026 Block Diagram(Please refer the datasheet from MICREL )
4.5.5 Reference Schematics
The following notes apply to Figure 4-24 below.
LAN_USB and CN26 incorporate two USB Type A receptacles, LAN_USB in addition
includes an RJ-45 (LANKom LJ -G40BU1-10-F).
The reference design uses an over-current detection and protection device. The Micrel
MIC2026 is dual channel power distribution switch. Power to the USB Port is filtered
using a ferrite (30 Ω @100MHz, 600mA) to minimize emissions. The ferrite should be
placed adjacent to the USB Port connector pins. The OC# signal is asserted until the
over-current or over-temperature condition is resolved.
Page 58
ICE Module
USB0+/- through USB4+/- from the COM Express Module are routed through a
common mode choke to reduce radiated cable emissions. The part shown is a AXIS
POWER BCCUB-T4P-2012-900T; this device has a common mode impedance of
approximately 90 Ω at 100MHz. The common-mode choke should be placed close to
the USB connector.
ESD protection diodes D10、D11 and D12 provide over-voltage protection caused by
ESD and electrical fast transients. Low capacitance diodes and transient voltage
suppression diodes should be placed near the USB connector. The example design
uses a RailClamp SRV05-4 low capacitance TVS Diode Array from Semtech
(http://www.semtech.com).
R249
@0_4
2
1
OUTB
FLGB
GND
FLGA
ENA
IN
OUTA
5
6
7
8
FB6
1
ENB
C286+
+V5_USB0
GCB1608K-300
3
USB0-
3
USB0+
GCB1608K-300
1
GND
FLGA
IN
ENA
OUTA
6
7
8
C288
+
150U_TNC_SMD_6V3
+V5_USB2
3
USB2-
3
USB2+
COMCHOKE_8_USB
2
1
3
4
C289
+
150U_TNC_SMD_6V3
+V5_USB2
USB2-_R
USB2+_R
L18
GCB1608K-300
FB33
U33
H3
U1
U2
U6
U3
U7
U4
U8
H4 H6
2
1
+V5_USB3
OUTB
FLGB
GND
FLGA
ENA
IN
OUTA
MIC2026
R375
0_4
6
7
8
C290
+
150U_TNC_SMD_6V3
USB0-_R 1
USB1-
3
USB1+
3
IO_GND
D10
+V5_USB4
3
USB4-
3
USB4+
GCB1608K-300
FB37
C291
+
150U_TNC_SMD_6V3
6
USB1-_R
5 +V5_USB01
2
USB0+_R 3
4
USB1+_R
6
USB3-_R
PACDN006
L17
IO_GND
+V5_USB3
USB3-_R
USB3+_R
COMCHOKE_8_USB
1
2
4
3
USB2-_R 1
USB3-
3
USB3+
3
IO_GND
D11
5 +V5_USB23
2
USB2+_R 3
4
USB3+_R
6
USB5-_R
PACDN006
IO_GND
USB1
1
ENB
3
COMCHOKE_8_USB
2
1
3
4
+V5_USB4
USB4-_R
USB4+_R
1
3
5
7
V1.01 Modify
2
4
6
8
L19
USB5+_R
USB5-_R
+V5_USB5
4
1
L21
USB4-_R 1
3
2
COMCHOKE_8_USB
USB5+
3
USB5-
3
IO_GND
D12
5 +V5_USB45
2
USB4+_R 3
4
PACDN006
HEADER_2X4_2.54
2
3
4
IO_GND
GCB1608K-300
FB36
1
3 USB_4_5_OC#
5
COMCHOKE_8_USB
1
2
L20
IO_GND
+V5_USB5
GCB1608K-300
2
4
+V5_USB1
USB1-_R
USB1+_R
IO_GND
2
MIC2026
FB8
1
FLGB
5
6
7
8
VCC1VCC2
D1D2D1+
D2+
GND1GND2
CN26
2
2
1
2
3
4
LJ-G40BU1-10
2
3
5
+V5_USB0
USB0-_R
USB0+_R
4
IO_GND
1
3 USB_2_3_OC#
OUTB
3
+V5_USB1
150U_TNC_SMD_6V3
ENB
COMCHOKE_8_USB
2
1
LAN_USB1B
L16
FB7
U32
4
USB for ESD Protect
150U_TNC_SMD_6V3
C287+
MIC2026
USB Port0~6
2
3
1
4
3 USB_0_1_OC#
USB Power control
U31
H5
U5
+V5_DUAL
+V5_USB01C181 0.1U_4_Y _16V
+V5_USB01C182 0.1U_4_Y _16V
+V5_USB23C183 0.1U_4_Y _16V
+V5_USB23C184 0.1U_4_Y _16V
+V5_USB45C185 0.1U_4_Y _16V
+V5_USB45C186 0.1U_4_Y _16V
Figure 4-24: USB Reference Design
Page 59
USB5+_R
ICE Module
4.5.6 USB Routing Guideline
4.5.6.1 Impedance
Parameters
Routing
Transfer rate / Port
480 Mbit/s
Maximum signal line length (coupled traces)
Max. 17.0 inches
Signal length used on COM Express module (including the COM
Express" connector) "
Signal length allowance for the COM Express carrier board "
3.0 inches
14.0 inches
Differential Impedance
90 Ohms +/-15%
Single-ended Impedance
45 Ohms +/-10%
Spacing between pairs-to-pairs (inter-pair) (s)
Min. 20mils
Spacing between differential pairs and high-speed periodic
signals
Spacing between differential pairs and low-speed non periodic
signals
Reference plain
Min. 50mils
Spacing from edge of plane
Min. 40mils
Via Usage
Try to minimize number of
vias
Min. 20mils
GND referenced preferred
4.5.6.2 General Routing and Placement
ƒ
USB 2.0 signals should be ground referenced.
ƒ
Route USB 2.0 signals using a minimum of vias and corners. This reduces
reflections and impedance changes.
ƒ
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of
making a single 90° turn. This reduces reflections on the signal by minimizing
impedance discontinuities.
ƒ
Do not route USB 2.0 traces under crystals, oscillators, clock synthesizers,
magnetic devices or ICs that use and/or duplicate clocks.
ƒ
Avoid stubs on high-speed USB signals, as stubs will cause signal reflections
and affect signal quality. If a stub is unavoidable in the design, the total of all
the stubs on a particular line should not be greater than 200 mils.
ƒ
Route all traces over continuous planes, with no interruptions. Avoid crossing
over anti-etch if possible. Crossing over anti-etch (plane splits) increases
inductance and radiation levels by forcing a greater loop area. Likewise, avoid
changing layers with USB 2.0 traces as much as practical. It is preferable to
change layers to avoid crossing a plane split. USB 2.0 traces as much as
practical. It is preferable to change layers to avoid crossing a plane split.
Page 60
ICE Module
ƒ
Separate signal traces into similar categories, and route similar signal traces
together (such as routing differential pairs together).
ƒ
Keep USB 2.0 signals clear of the core logic set. High current transients are
produced during internal state transitions and can be very difficult to filter out.
4.6 LVDS
4.6.1 Signal Description
Table 4-15 shows COM Express LVDS and LCD signals, including pin number,
signals, I/O and descriptions.
Table 4-15: LVDS Signals Description
Pin
Signal
I/O
Description
A71
A72
A73
A74
A75
A76
A78
A79
A81
A82
B71
B72
B73
B74
B75
B76
B77
B78
B81
B82
A77
LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2LVDS_A3+
LVDS_A3LVDS_A_CK+
LVDS_A_CKLVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2LVDS_B3+
LVDS_B3LVDS_B_CK+
LVDS_B_CKLVDS_VDD_EN
O
LVDS channel A differential signal pair 0
O
LVDS channel A differential signal pair 1
O
LVDS channel A differential signal pair 2
O
LVDS channel A differential signal pair 3
O
LVDS channel A differential clock pair
O
LVDS channel B differential signal pair 0
O
LVDS channel B differential signal pair 1
O
LVDS channel B differential signal pair 2
O
LVDS channel B differential signal pair 3
O
LVDS channel B differential clock pair
LVDS flat panel power enable.
B79
LVDS_BKLT_EN
B83
LVDS_BKLT_CTRL
A83
LVDS_I2C_CK
A84
LVDS_I2C_DAT
O 3.3V
CMOS
O 3.3V
CMOS
O 3.3V
CMOS
O 3.3V
CMOS
I/O 3.3V
OD CMOS
LVDS flat panel backlight enable high active signal
LVDS flat panel backlight brightness control
DDC I2C clock signal used for flat panel detection
and control.
DDC I2C data signal used for flat panel detection
and control.
Page 61
ICE Module
4.6.2 LVDS Cable Consideration
Balanced cables (twisted pair) are usually better than unbalanced cables (ribbon cable)
for noise reduction and signal quality. Balanced cables tend to generate less EMI due
to field canceling effects and also tend to pick up electromagnetic radiation as
common-mode noise, which is rejected by the receiver. Twisted pair cables provide a
low-cost solution with good balance and flexibility. They are capable of medium to long
runs depending upon the application skew budget. A variety of shielding options are
available.
Ribbon cables are a cost effective and easy solution. Even though they are not well
suited for high-speed differential signaling they do work fine for very short runs. Most
cables will work effectively for cable distances of <0.5m.
4.6.3 Backlight and LCD Power Timing Control
Figure 4-25 is a reference design of backlight and LCD power timing control. In Figure
4-26, VIN is LCD power and lamp is LCD backlight power. Figure 4-27 shows the LCD
power sequence, and design must conform to it’s power sequence.
+V3.3
C109
10U_8_X_6V3
J_VLVDS1
C110
10U_8_X_6V3
J_VLVDS1
+V12
2-3
5V
2
R145
C269
1000P_4_X_50V
1
2
R417
100K_4
S
1
R151
2
100K_4
Figure 4-25: LVDS Power Control
Page 62
C273
2.2U_6_Y _10V
2
G S
HEADER_1X3_2
7
8
Q3
2N7002_SOT23
G
3 LVDS_VDD_EN
1
+V3.3_LCD_PANEL
3 +V5
Q2A
FDS6975_SOP8 D
D
2
1M_4
2
1 +V3.3
1
3.3V(Default)
1
1-2
1
J_VLVDS1(1-2)
MINIJUMPER_1X2_2
+V5
C270
0.1U_4_Y _16V
C271
0.1U_4_Y _16V
2
LVDS
C272
10U_1210_Y_25V
ICE Module
C114
C115
0.1U_4_Y_16V
R148
47K_4
6
5
2
4
B
1K_4 B
LVDS_BRIGHTNESS
Q4
2N3904_SOT23
Q5
2N3904_SOT23
R152
100K_4
C116
1
2
3
4
5
INVERTER1
LCD_Adj
GND1
12V
GND2
BL_EN
WAFER_1X5_2
10U_1210_Y _25V
E
R150
E
LVDS_BKLT_EN
LVDS_BKLT_CRTL
LVDS_ENABKL
R149
1K_4
C
Q2B
FDS6975_SOP8
R146
1K_4
+V12_LCD_BKL
R147
39_4_1%
1
3
FB4
FB11_12_600MA
2
+V5
1
+V12
1
+V12_LCD_BKL
2
10UF_1210_16V
C
2
1
+V12_LCD_BKL
LVDS_BRIGHTNESS
R153
R154
@4.7K_4
+V5
@4.7K_4
Figure 4-26: Backlight Control Circuit
Figure 4-27: LCD Power Sequence Example(Refer to AUO G150XG01)
Page 63
ICE Module
4.6.4 LVDS Routing Guideline
4.6.4.1 Impedance
Table 4-16: LVDS Impedance Consideration
Parameters
Transfer Rate
Maximum signal line length to the LVDS connector (coupled
traces)
Signal length used on COM Express module (including the
COM Express" carrier board connector) "
Signal length to the LVDS connector available for the COM
Express carrier board "
Routing
5.38 Gbits/sec
8.75 inches
2.0 inches
6.75 inches
Differential Impedance
100 Ohms +/-20%
Single-ended Impedance
55 Ohms +/-15%
Spacing between pair to pairs (inter-pair) (s)
Min. 20mils
Spacing between differential pairs and high-speed periodic
signals
Spacing between differential pairs and low-speed non
periodic signals
Min. 20mils
Min. 20mils
Length matching between differential pairs (intra-pair)
+/- 20mils
Length matching between clock and data pairs (inter-pair)
+/- 20mils
Length matching between data pairs (inter-pair)
+/- 40mils
Spacing from edge of plane
+/- 40mils
4.6.4.2 Implement
Many carrier board designs do not need the full range of LVDS performance offered
by COM Express modules. It depends on the flat panel configuration of the COM
Express module, as well as the carrier board design, as to how many LVDS signal
pairs are supported. While the dual channel 24-bit LVDS configuration needs all 10
LVDS signal pairs, a single channel 18-bit LVDS configuration only requires 4 LVDS
signal pairs. In this case all unused LVDS signal pairs should be left open on the
carrier board. If the LVDS display interface of the COM Express module is not
implemented, all signals associated with this interface should be left open.
Page 64
ICE Module
4.7 Audio Codec Interface(AC’97/HDA)
All COM Express module types support Audio Codec '97 (AC'97) and/or High
Definition Audio (HDA) Digital Interface (AC-link) specifically designed for
implementing audio and modem I/O functionality. The corresponding signals can be
found on the COM Express module connector rows A and B.
4.7.1 Signal Description
Table 4-17 shows COM Express audio bus signal, including pin number, signals, I/0,
power plane, terminal resistors, damping resistors and descriptions.
Table 4-17: Audio Signals Description
Pin
Signal
I/O
Description
A30
AC_RST#
O 3.3VSB CMOS
CODEC Reset.
A29
AC_SYNC
O 3.3V CMOS
A32
A33
B30
B29
B28
AC_BITCLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
AC_SDIN2
O 3.3V CMOS
O 3.3V CMOS
I 3.3VSB CMOS
48kHz fixed-rate, sample-synchronization signal to
the CODEC(s).
12.228 MHz Serial Bit Clock for CODEC.
Serial TDM data output to the CODEC.
Serial TDM data inputs from up to 3 CODECs
4.8 Reference Circuit
Please refer to the schematic diagram of the baseboard. IEI baseboard is embedded
with the Realtek ALC888 audio controller. For the detailed specifications of the
Realtek ALC888, please go to http://www.realtek.com/ .
4.8.1 Audio Routing Guideline
4.8.1.1 Analog Power Delivery
Clean analog power delivery to the audio codec and other audio components utilizing
the 5-V analog supply is critical. Excessive system noise on this supply will degrade
the entire audio sub-system. Except the GND signal, users can use independent LDO
to generate clean audio analog power.
Page 65
ICE Module
Q9
1
+V5_AUDIO
VIN
VOUT
GND
FB9
2
3
2
GS78L05N_TO92_3
TO92_123
C188
0.1U_4_Y _16V
FB_80_6_600MA
1
+V12
EC12
100U_SMD6_3_EC_25V
Figure 4-28: Audio Analog Power Example
4.8.1.2 Digital and Analog Signals Isolation
Analog audio signals and other digital signals should be routed as far as possible from
each other. All audio circuits require careful PCB layout and grounding to avoid picking
up digital noise on audio-signal lines.
4.8.1.3 EMI Consideration
Any signals entering or leaving the analog area must cross the ground split in the area
where the analog ground is attached to the main motherboard ground. That is, no
signal should cross the split/gap between the ground planes, which would cause a
ground loop, thereby greatly increasing EMI emissions and degrading the analog and
digital signal quality.
4.9 IDE
Type 2 and 4 COM Express modules provide a single channel IDE interface
supporting two standard IDE hard drives or ATAPI devices with a maximum transfer
rate of ATA100 (Ultra-DMA-100 with 100MB/s transfer rate). The corresponding
signals can be found on the module connector rows C and D.
4.9.1 Signal Description
Table 4-18 shows COM Express PCI IDE signals, including pin number, signals, I/0,
power plane, terminal resistors, damping resistors and descriptions.
Table 4-18: IDE signals description
Pin
D13
D14
D15
D9
C14
D8
Signal
I/O
Description
IDE_D[0..15]
IDE_A[0:2]
I/O 3.3V
O 3.3V
Bidirectional data to / from IDE device.
Address lines to IDE device.
IDE_IOW#
IDE_IOR#
IDE_REQ
O 3.3V
O 3.3V
I 3.3V
I/O write line to IDE device.
I/O read line to IDE device.
IDE device DMA request. It is asserted by the IDE device
to request a data transfer.
Page 66
ICE Module
D10
D16
D17
C13
IDE_ACK#
IDE_CS1#
IDE_CS3#
IDE_IORDY
O 3.3V
O 3.3V
O 3.3V
I 3.3V
D18
D12
D77
IDE_RESET#
IDE_IRQ
IDE_CBLID#
O 3.3V
I 3.3V
I 3.3V
IDE device DMA acknowledge.
IDE device chip select for 1F0h to 1FFh range.
IDE device chip select for 3F0h to 3FFh range.
IDE device I/O ready input. Pulled low by the IDE device to
extend the cycle.
Reset output to IDE device, active low.
Interrupt request from IDE device.
Input from off-module hardware indicating the type of IDE
cable being used. High indicates a 40-pin cable used for
legacy IDE modes. Low indicates that an 80-pin cable with
interleaved grounds is used. Such a cable is required for
Ultra-DMA 66, 100 modes.
4.9.2 IDE Connector
To interface standard 3.5-inch parallel ATA drives, a standard 2.54mm, two row,
40-pin connector in combination with a ribbon conductor cable is used. For slower
drive speeds up to ATA33, a normal 40-pin, 1.0mm-pitch conductor cable is sufficient.
Higher transfer rates like ATA66 and ATA100 require 80-pin conductor cables, where
the extra 40 conductors are tied to ground to isolate the adjacent signals for better
signal integrity. The signal 'IDE_CBLID#' of the COM Express carrier board indicates
which conductor cable is used. It ties to ground if a 80-pin conductor cable is
connected. This allows the module's BIOS to determine the maximum transfer rate
that can be driven and set up the proper drive parameters for the IDE controller.
IDE Connector
3 IDE_RESET#
PIDE1
33_4
2
IDE_D7
IDE_D6
IDE_D5
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0
2
+V3.3
R130
4.7K_4
1
R129
8.2K_4
3
3
3
3
3
3
3
3
3
20,21
IDE_REQ
IDE_IOW#
IDE_IOR#
IDE_IORDY
IDE_ACK#
IDE_IRQ
IDE_A1
IDE_A0
IDE_CS#1
HDD_LED#
R134
R137
1
1
2 33_4
2 33_4
IDE_SDA1
IDE_SDA0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
20
IDE_D[15..0] 3
2
4
6
8
10
12
14
16
18
22
24
26
28
30
32
34
36
38
40
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
R132
470_4
R135 1
IDE_SDA2
R138 1
2 0_4
2 33_4
IDE_CBLID#
IDE_A2
IDE_CS#3
2
R128
1
R140
10K_4
1
BOXHEADER_2X20_2.54
Figure 4-29: IDE Reference Design
Page 67
3
3
3
ICE Module
Notes: When using a 44- pin IDE connector, pins 41 and 42 must be connected to VCC
and pins 43 and 44 must be connected to ground. All other pins are equivalent to a
40-pin IDE connector. Additionally, decoupling capacitors should be connected to the
VCC pins.
4.9.3 CF Connector
CompactFlash (CF) cards with DMA capability require that the two signals 'IDE_REQ'
and 'IDE_ACK#' are routed to the CF card socket on the COM Express carrier board.
If this is not done then some DMA capable CF cards may not work because they are
not designed for non DMA mode. For more information about this subject refer to the
datasheet of the CF card or contact your CF card manufacturer. If two CF cards are
used in master/slave mode on the same IDE channel, the signal 'CSEL#' of the CF
card socket that drives the slave CF card must be tied to ground. In master mode the
'CSEL#' signal must be left open. Figure 4-31 shows a circuitry implementing a CF
card socket that is DMA capable.
Figure 4-30: CF Connector
CF Connector
IDE_D3
IDE_D4
IDE_D5
IDE_D6
IDE_D7
IDE_CS#1
+V5
IDE_SDA2
IDE_SDA1
IDE_SDA0
IDE_D0
IDE_D1
IDE_D2
R142
100_4_1%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CF1 515253
515253
26
GND1
CD1 27
D3
D11 28
D4
D12 29
D5
D13 30
D6
D14 31
D7
D15 32
CE
CE2 33
A10
VS1 34
OE
IOR 35
A9
IOW 36
A8
WE 37
A7
IRQ 38
VCC1
VCC2 39
A6
CSEL 40
A5
VS2 41
A4
RESET 42
A3
WAIT 43
A2
INPACK 44
A1
REG 45
A0
BVD2 46
D0
BVD1 47
D1
D8 48
D2
D9 49
IOCS16
D10 50
CD2545556
GND2
545556
CFIIB-SMD
R131
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
R133
R136
R1391
IDE_CBLID#
IDE_D8
IDE_D9
IDE_D10
Figure 4-31: CompactFlash® Reference Design
Page 68
100_4_1%
IDE_CS#3
3
IDE_IOR#
IDE_IOW#
10K_4
3
3
IDE_IRQ
3
10K_4
+V5
+V5
+V5
JCF1
SHORT : MASTER
OPEN : SLAVE
233_4 IDE_RESET#
IDE_IORDY 3
IDE_REQ
3
IDE_ACK#
3
HDD_LED# 20,21
1
2
JCF1
1
2
HEADER 2
R141
1K_4
ICE Module
4.10 TV-Out
The TV-Out display interface of the COM Express Module consists of three individual
digital-to-analog converter (DAC) channels, which can be used in different
combinations to support S-Video (Y/C), Composite Video or Component Video
(YPbPr). The corresponding signals can be found on the COM Express module
connector row B.
4.10.1 Signal Description
Table 4-19: TV-Out Signal Descriptions
Pin
Signal
I/O
Description
B97
TV_DAC_A
O Analog
B98
TV_DAC_B
O Analog
B99
TV_DAC_C
O Analog
TVDAC Channel A Output supports the following:
Composite video: CVBS
Component video: Chrominance (Pb) analog signal
S-Video: not used
TVDAC Channel B Output supports the following:
Composite video: not used
Component video: Luminance (Y) analog signal.
S-Video: Luminance analog signal.
TVDAC Channel C Output supports the following:
Composite video: not used
Component: Chrominance (Pr) analog signal.
S-Video: Chrominance analog signal.
4.10.2 TV-Out Routing Guideline
4.10.2.1 Signal Termination
Each of the TV-DAC channels should have a 150 Ω ±1% pull-down termination
resistor connected from the TV-DAC output of the COM Express module to the carrier
board ground. This termination resistor should be placed as close as possible to the
TV-Out connector on the carrier board. A second 150 Ω ±1% termination resistor
exists on the COM Express module itself.
4.10.2.2 Video Filter
There should be a PI-filter placed on each TV-DAC channel output to reduce
high-frequency noise and EMI. The PI-filter consists of two 10pF capacitors with a
120Ω @ 30Mhz ferrite bead between them. It is recommended to place the PI-filters
and the termination resistors as close as possible to the TV-Out connector on the
carrier board. The PI-filters should be separated from each other by at least 50mils or
more in order to minimize crosstalk between the TV-DAC channels.
Page 69
ICE Module
4.10.2.3 ESD Protection
ESD clamp diodes are required for each TV-DAC channel. These low capacitance
clamp diodes should be placed as near as possible to the TV-Out connector on the
COM Express carrier board between +5V supply voltage and ground.
4.10.2.4 Reference Schematic
At least 30 mils of spacing should be used for the routing between each TV-DAC
channel to prevent crosstalk between the TV-DAC signals. The maximum trace length
distance of the TV-DAC signals between the COM Express connector and the 150Ω
±1% termination resistor should be within 12 inches. This distance should be routed
with a 50 Ω trace impedance.
A
K
+V3.3
D6
C
BAV99LT1G_SOT23
1
A
R168
150_4_1%
C128
3.3P_4_N_50V
TV_ABLUE_CVBS
TV1
C129
3.3P_4_N_50V
2
+V3.3
K
FB150_6_200MA
1
L9
TV_DAC_A
2
3
D7
C
BAV99LT1G_SOT23
L10
TV_DAC_B
FB150_6_200MA
TV_AGREEN_Y
C131
3.3P_4_N_50V
2
C130
3.3P_4_N_50V
1
1
A
K
R169
150_4_1%
D8
1
FB150_6_200MA
C132
3.3P_4_N_50V
2
R170
150_4_1%
1
L11
TV_DAC_C
C133
3.3P_4_N_50V
Figure 4-32: TV Out Schematic Reference
Page 70
2
C
BAV99LT1G_SOT23
3
GND
Y
GND
C
GND
CVBS
HEADER_2X3_2.54
+V3.3
2
3
1
2
3
TV_ARED_C
4
5
TV_ABLUE_CVBS6
TV_AGREEN_Y
TV_ARED_C
ICE Module
4.11 LAN (Local Area Network)
All COM Express modules provide at least one LAN port with the minimum capability
of 10/100BaseTx Ethernet and optional 10/100/1000BaseT Gigabit Ethernet compliant
to the IEEE 802.3ab specification.
The LAN interface of the COM Express module consists of 4 pairs of low voltage
differential pair signals designated from 'GBE0_MDI0' (+ and -) to 'GBE0_MDI3' (+ and
-) plus additional control signals for link activity indicators. These signals can be used
to connect a 10/100/1000BaseT RJ-45 connector with integrated or external isolation
magnetics to the carrier board. The corresponding LAN differential pair and control
signals can be found on the modules connector rows A and B.
4.11.1 Signal Description
Table 4-20 shows COM Express Ethernet signals, including pin number, signals, I/O,
power plane, terminal resistors, damping resistors and descriptions.
Table 4-20: Ethernet signals description
Pin
Signal
A13
A12
A10
A9
A7
A6
A3
A2
GBE0_MDI0+
GBE0_MDI0GBE0_MDI1+
GBE0_MDI1GBE0_MDI2+
GBE0_MDI2GBE0_MDI3+
GBE0_MDI3-
A14
GBE0_CTREF
A8
GBE0_LINK#
A4
GBE0_LINK100#
A5
GBE0_LINK1000
#
B2
GBE0_ACT#
I/O
Description
Media Dependent Interface (MDI) differential pair 0. The
MDI can operate in 1000, 100, and 10Mbit/sec modes.
Media Dependent Interface (MDI) differential pair 1. The
MDI can operate in 1000, 100, and 10Mbit/sec modes.
Media Dependent Interface (MDI) differential pair 2. The
MDI can operate in 1000, 100, and 10Mbit/sec modes.
Media Dependent Interface (MDI) differential pair 3. The
MDI can operate in 1000, 100, and 10Mbit/sec modes.
Reference voltage for carrier board Ethernet channel 0
magnetics center tap. The reference voltage is
determined by the requirements of the module's PHY
and may be as low as 0V and as high as 3.3V.
I/O
I/O
I/O
I/O
REF
O 3.3V
CMOS
O 3.3V
CMOS
O 3.3V
CMOS
O 3.3V
CMOS
OD
OD
OD
OD
Ethernet controller 0 link indicator, active low.
Ethernet controller 0 100Mbit/sec link indicator, active
low.
Ethernet controller 0 1000Mbit/sec link indicator, active
low.
Ethernet controller 0 activity indicator, active low.
Page 71
ICE Module
4.11.2 Giga LAN Connector
IEI uses the RJ-45 connector including the transformer.
8
6
4
2
+V3.3_DUAL
7
5
3
1
RN28
330_8P4R04
LAN_USB1A
P2
P3
3 GBE0_MDI0+
3 GBE0_MDI0-
P4
P5
3 GBE0_MDI1+
3 GBE0_MDI1-
P6
P7
3 GBE0_MDI2+
3 GBE0_MDI2-
P8
P9
3 GBE0_MDI3+
3 GBE0_MDI3R233
+V1.8_LAN
0_4
P1
P10
MD0+
MD0MD1+
MD1MD2+
MD2MD3+
MD3CT1
GND
LJ-G40BU1-10
Y ELLOW
LEFT-P
LEFT-N
RIGHT-P
RIGHT-N
GREEN
FG1
FG2
PG3
FG4
FG5
FG6
FG7
FG8
P14
P13
P12
P11
R229
220_4
R230
R231
0_4
220_4
R232
0_4
GBE0_ACT#
GBE0_LINK#
3
3
GBE0_LINK1000# 3
GBE0_LINK100# 3
15
16
9
10
11
12
13
14
C187
0.1U_4_Y _16V
IO_GND
Figure 4-33: Giga Lan Connection Exampel (including Transformer)
4.11.3 LAN Link Activity and Speed LED
The COM Express module has four 3.3V open drain outputs to directly drive activity,
speed indication and link status LEDs. The 3.3V standby voltage should be used as
LED supply voltage so that the link activity can be viewed during system standby state.
Since LEDs are likely to be integrated into a RJ-45 connector with integrated
magnetics module, the LED traces need to be routed away from potential sources of
EMI noise.
Page 72
ICE Module
4.11.4 LAN Routing Guideline
4.11.4.1 Impedance
Table 4-21: LAN Impedance Consideration
Parameters
Transfer Rate
Maximum signal line length (coupled traces)
Signal length used on COM Express module
(including the carrier board connector) "
Signal length allowance for the COM Express
carrier board "
Maximum signal length between isolation
magnetics module and RJ-45 connector on the
carrier board
Differential Impedance
Single-ended Impedance
Spacing between RX and TX pairs (inter-pair) (s)
Spacing between differential pairs and high-speed
periodic signals
Spacing between differential pairs and low-speed
non periodic signals
Length matching between differential pairs
(intra-pair)
Length matching between RX and TX pairs
(inter-pair)
Spacing between digital ground and analog ground
plane (between the magnetics module and RJ-45
connector)
Spacing from edge of plane
Via Usage
Routing
1.0 Gbits/sec
8.0 inches specified by COM Express "
3.0 inches specified by COM Express "
5.0 inches to the magnetics module
1.0 inch
95 Ohms +/-20%
55 Ohms +/-15%
Min. 50mils
Min. 300mils
Min. 100mils
Max. 5mils
Max. 30mils
Min. 60mils
Min. 40mils
Max. of 2 vias on TX path Max. of 2
vias on RX path
Page 73
ICE Module
4.11.4.2 LAN Ground Plane Separation
Isolated separation between the analog ground plane and digital ground plane is
recommended. If this is not implemented properly then bad ground plane partitioning
could cause serious EMI emissions and degrade analog performance due to bouncing
noise. The plane area underneath the magnetic module should be left void. The void
area is to keep transformer induced noise away from the power and system ground
planes. The isolated ground, also called chassis ground, connects directly to the fully
shielded RJ-45 connector. For better isolation it is also important to maintain a gap
between chassis ground and system ground that is wider than 60mils. For ESD
protection a 3kV high voltage capability capacitor is recommended to connect to this
chassis ground for ESD protection. Additionally, a ferrite bead can be placed parallel
to the capacitor.
4.12 LPC (Low Pin Count Interface)
The Low Pin Count Interface was defined by the Intel Corporation to facilitate the
industries transition toward legacy free systems. It allows the integration of
low-bandwidth legacy I/O components within the system, which are typically provided
by a Super I/O controller. Furthermore, it can be used to interface Firmware Hubs,
Trusted Platform Module (TPM) devices and Embedded Controller solutions. Data
transfer on the LPC bus is implemented over a 4 bit serialized data interface, which
uses a 33MHz LPC bus clock. For more information about LPC bus refer to the 'Intel
Low Pin Count Interface Specification Revision 1.1'.
4.12.1 Signal Description
Since COM Express is designed to be a legacy free standard for embedded modules,
it does not support legacy functionality such as PS/2 keyboard/mouse, serial and
parallel ports. Instead it provides an LPC interface that can be used to add peripheral
devices to the carrier board design. The reduced pin count of the LPC interface makes
it easy to implement such devices. All corresponding signals can be found on the
modules connector rows A and B.
Page 74
ICE Module
Table 4-22: LPC Interface Signal Descriptions
Pin
Signal
I/O
Description
A50
LPC_SERIRQ
LPC serialized IRQ.
B3
LPC_FRAME#
B4
B5
B6
B7
B8
B9
B10
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ0#
LPC_DRQ1#
LPC_CLK
I/O 3.3V
CMOS
O 3.3V
CMOS
I/O 3.3V
CMOS
LPC frame indicates start of a new cycle or termination
of a broken cycle.
LPC multiplexed command, address and data.
I 3.3V
CMOS
O 3.3V
CMOS
LPC encoded DMA/Bus master request.
LPC clock output 33MHz.
4.12.2 Clock and Reset Buffer
The ICE module already integrates reset buffer, therefore, the baseboard does not
need reset buffer. For clock buffer, please refer to or integrate with the PCI clock
buffer.
@33_41
2 R34
U2
CLK33M_PCI
CLK33M_MINIPCI
CLK33M_SLOT3
CLK33M_80PORT
CLK33M_BIOS2
CLK33M_TPM
+V3.3
C15
10U_8_X_6V3
R37
R40
2
2
+V3.3_CLKBUFFER
R44
R47
2
2
R51
1 33_4
1 33_4
CLKBUFFER_S2
2
REF
CLKOUT
CLKA1 CLKA4
CLKA2 CLKA3
VDD
VDD
GND
GND
CLKB1 CLKB4
CLKB2 CLKB3
S2
S1
16
15
14
13
12
11
10
9
33_4 1
33_4 1
2 R38
2 R41
CLK33M_SLOT1
CLK33M_SLOT2
+V3.3_CLKBUFFER
33_4 1
33_4 1
CLKBUFFER_S1
2 R45
2 R48
CLK33M_SIO2
CLK33M_MINICARD
CY 2309NZSXC-1H
1 33_4
+V3.3_CLKBUFFER
FB3
FB30_8_3A
C16
10U_8_X_6V3
1
2
3
4
5
6
7
8
1 33_4
1 33_4
C17
C18
0.1U_4_Y _16V 0.1U_4_Y _16V
+V3.3_CLK
10K_4 1
@10K_4 1
2 R62
2 R63
CLKBUFFER_S1
+V3.3_CLK
10K_4 1
@10K_4 1
2 R65
2 R67
CLKBUFFER_S2
CLK33M_SLOT1
C10
1
2 10P_4_N_50V
CLK33M_SLOT2
C11
1
2 10P_4_N_50V
CLK33M_SLOT3
C13
1
2 10P_4_N_50V
CLK33M_SIO2
C241 1
2 10P_4_N_50V
CLK33M_BIOS2
C265 1
2 10P_4_N_50V
CLK33M_TPM
C266 1
2 10P_4_N_50V
CLK33M_MINICARD C267 1
2 10P_4_N_50V
CLK33M_80PORT
C14
1
2 10P_4_N_50V
CLK33M_MINIPCI
C12
1
2 10P_4_N_50V
Figure 4-34: Clock Buffer
Page 75
ICE Module
4.12.3 LPC SuperIO for Legacy IO Support
Some COM Express modules utilize BIOS that contains built-in support for an external
Winbond W83627HG LPC Super I/O controller that can be implemented on the carrier
board (http://www.winbond-usa.com). The base address for this Super I/O should be
0x2E to be sure that the legacy devices can be initialized by the BIOS. The
implementation of this device on the COM Express carrier board will provide legacy
interfaces such as PS/2 keyboard/mouse, floppy port, two serial ports (COM1 and
COM2) and one parallel port (LPT1). The other functions of this Super I/O controller
are not supported.
16
16
16
16
16
16
16
16
3
IR CONNECTOR
+V5
IR1
IR_5X1_2.54
1
2
3
4
5
UART_RX2
UART_TX2
UART_CTS#2
UART_DSR#2
UART_RTS#2
UART_DTR#2
UART_RX2
UART_TX2
UART_DCD#2
UART_RI#2
WAKE_UP#
CASEOPEN#
SUS_LED
R176
R177
4.7K_4
1K_4_1%
SIO_DOUT3
SIO_DOUT2
SIO_DOUT1
SIO_DOUT0
SIO_DIN3
SIO_DIN2
SIO_DIN1
SIO_DIN0
WDTO : 6F02
DIO in : 6F08
DIO out : 6F09
UART_TX1
UART_RX1
UART_DTR#1
UART_RTS#1
UART_DSR#1
UART_CTS#1
15
15
15
15
15
15
+V3.3
LPT_STB#
LPT_AFD#
LPT_ERR#
LPT_INIT#
LPT_SLIN#
LPT_PD[7..0]
15
LPT_ACK#
LPT_BUSY
LPT_PE
LPT_SLCT
15
15
15
15
+V3.3
C135
0.1U_4_X_10V
C136
C137
1
CLK48M_SIO1
3 CLK33M_LPC
3,11 LPC_DRQ#0
3,11,14 SERIRQ
3,5,11,14,20 LPC_AD3
3,5,11,14,20 LPC_AD2
3,5,11,14,20 LPC_AD1
3,5,11,14,20 LPC_AD0
+V3.3
3,5,11,14,20 LPC_FRAME#
3,5,6,7,8,10,14 PCI_RST#
0.1U_4_X_10V 0.1U_4_X_10V
2
R179 2
LPT_PD[7..0]
15
15
15
15
15
LPT_PD0
LPT_PD1
LPT_PD2
LPT_PD3
LPT_PD4
LPT_PD5
LPT_PD6
LPT_PD7
W83627EHG_PQFP128
1
3
2
MINICARD_DISABLE# 5
KB_DAT#
15
KB_CLK#
15
KB_RST#
3
KB_A20GATE 3
2
VDD OUT
EN GND
C134
0.1U_4_Y_16V OSC48MHZ_SMD
2
1
Y1
21
UART_RI#1
15
UART_DCD#1 15
1
+V3.3
15 FDD_RWC#
15 FDD_INDEX#
15
FDD_MOA#
15
FDD_DSA#
15
FDD_DIR#
15 FDD_STEP#
15
FDD_WD#
15
FDD_WE#
+V3.3
15 FDD_TRACK0#
15
FDD_WP#
15 FDD_RDATA#
15 FDD_HEAD#
15 FDD_DSKCHG#
1 33_4
21
3
15
15
2 @0_4
SIO_SMI-
R178
10K_4
3
21,23
3
PANSWIN
PM_PWRBTN#
MS_DAT#
MS_CLK#
+V3.3_DUAL
2
+V3.3_DUAL
SIO_WDT#
+VBAT
+V3.3_DUAL
+VBAT
PM_SLP_S3#
PS_ON#
PWROK_SIO
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
W83627EHG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
+V5
D-
R175 1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
C138
1
FAN_PWM1
FAN_PWM2
1
20
20
GP37
KDAT/GP26
KCLK/GP27
3VSB
KBRST
GA20M
SO/AUXFANIN1
RIA/GP60
DCDA/GP61
VSS_2
SOUTA/GP62/PENKBC
SINA/GP63
DTRA/GP64/PENROM
RTSA/GP65/HEFRAS
DSRA/GP66
CTSA/GP67
VCC3_3
STB
AFD
ERR
INIT
SLIN
PD0
PD1
PD2
PD3
0.1U_4_X_10V
2
FAN_IO1
FAN_IO2
IOAVCC
CPUTIN
SY STIN
VID5
VID4
VID3
VID2
VID1
VID0
AUXFANIN0
CPUFANIN0
SY SFANIN
AVCC3
CPUFANOUT0
SY SFANOUT
AGND
BEEP/SI
GP21/CPUFANIN1/MSI
GP20/CPUFANOUT1/MSO
GP17/GPSA2
GP16/GPSB2
GP15/GPY 1
GP14/GPY 2
GP13/GPX2
GP12/GPX1
GP11/GPSB1
GP10/GPSA1
2
20
20
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
DRVDEN0
GP23/SCK
INDEX
MOA
HM_SMI / OVT
DSA
AUXFANOUT0
DIR
STEP
WD
WE
VCC3_1
TRAK0
WP
RDATA
HEAD
DSKCHG
IOCLK
GP22/SCE
VSS_1
PCICLK
LDRQ
SERIRQ
LAD3
LAD2
LAD1
LAD0
VCC3_2
LFRAME
LRESET
SLCT
PE
BUSY
ACK
PD7
PD6
PD5
PD4
D+
VTIN1
AUXTIN
VREF
CPUVCORE
VIN0
VIN1
VIN2
VIN3
VIN4
RSTOUT0
RSTOUT1
GP30
GP31
SCL/GP32/RSTOUT2
SDA/GP33/RSTOUT3
GP34/RSTOUT4
GP35
PME
RIB/GP40
DCDB/GP41
SOUTB/IRTX
SINB/IRRX
DTRB/GP44
RTSB/GP45
DSRB/GP46
CTSB/GP47
GP50/WDTO/EN_VRM10
CASEOPEN
RSMRST/GP51
VBAT
SUSB/GP52
PSON/GP53
PWROK/GP54
GP55/SUSLED
GP36
PSIN/GP56
PSOUT/GP57
MDAT/GP24
MCLK
U13
4
4.7K 1
10M_4
10K_4
HM_VREF
VTIN3
C260
0.1U_4_Y _16V
R180
R173
R174
+5VIN
+3.3VIN
VIN2
VIN1
+12VIN
C139
0.1U_4_X_10V
Figure 4-35: Windbond W83627EHG Reference Design
4.12.3.1 Keyboard/Mouse
The following figures display reference circuitries for the legacy I/O interfaces such as
PS/2 keyboard/mouse, RS-232 serial port, parallel port and floppy port connected to
the Winbond W83627HG Super I/O controller. The PS/2 connector has to be powered
Page 76
ICE Module
up by the +5V standby voltage to support keyboard and mouse wake up functionality
from low power system states (S1 and S3).
F1
2
+V5_DUAL
FB5
+V5_KB_R
1
FB19_6_500MA
FUSE_12_1.1A_6V
13
1
KB_DAT#
2
13
KB_CLK#
13
MS_DAT#
3
U15
DI
GND
DO
VCC
CLKI CLKO
KBDAT
1
4
KBCLK
1
6
MSDAT
1
6
5
+V5_DUAL
KBMF01SC6
U16
1
2
13
3
MS_CLK#
DI
GND
DO
VCC
CLKI CLKO
5
MSCLK
L12 19
L13 19
CN6A
2
L_KDAT
2
L_KCLK
2
L_MDAT
2
L_MCLK
L14 19
+V5_DUAL
4
KB/MS
+V5_KB_RR
L15 19
1
KBMF01SC6
1
2
3
4
5
6
7
8
9
10
11
12
Dual Mini Din
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
CN6B
B7
B8
13
14
15
16
17
Dual Mini Din
IO_GND
Figure 4-36: Keyboard/Mouse Reference Schematic
4.12.3.2 RS-232/Floppy/LPT/IR
The Winbond W83627provides some other legacy I/O. Please refer to the schematic
diagrams suggested by Winbond.
U17
0.1U_4_Y _16V
C147
C146
0.1U_4_Y_16V
12
14
13
EN
SHDN#
C1+
C1V+
TOUT1
TOUT2
TOUT3
TOUT4
VCC
GND
C2+
C2V-
ADM213LEEA_SSOP28
232_DCD#1
232_DSR#1
232_RX1
232_CTS#1
232_RI1
2
3
1
28
232_TX1
232_RTS#1
232_DTR#1
11
10
VCC5
COM1
11
232_RI1
16
15 0.1U_4_Y _16V
C148
16
17
C149
0.1U_4_Y _16V
232_DCD#1
232_DSR#1
232_RX1
232_RTS#1
232_TX1
232_CTS#1
232_DTR#1
232_RI1
R204
R205
R206
R207
R208
R209
R210
R211
0_6
0_6
0_6
0_6
0_6
0_6
0_6
0_6
1
6
2
7
3
8
4
9
5
2
4
6
8
24
25
+V5
TIN1
TIN2
TIN3
TIN4
9
4
27
23
18
CN7
180P_8P4C_N_50V
IO_GND
COM1
10
CN8
180P_8P4C_N_50V
1
3
5
7
13
UART_TX1
13 UART_RTS#1
13 UART_DTR#1
RIN1
RIN2
RIN3
RIN4
RIN5
2
4
6
8
7
6
20
21
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
1
3
5
7
8
5
26
22
19
13 UART_DCD#1
13 UART_DSR#1
13
UART_RX1
13 UART_CTS#1
13
UART_RI#1
DB9
IO_GND
IO_GND
Figure 4-37: RS-232 Reference Schematic
Page 77
ICE Module
+V5
A
LPT
LPT_PD7
LPT_PD6
LPT_PD5
LPT_PD4
LPT_PD3
LPT_PD2
LPT_PD1
LPT_PD0
13
LPT_STB#
13
13
13
LPT_SLIN#
LPT_INIT#
LPT_AFD#
13
LPT_ERR#
14
13
11
9
7
6
5
4
3
2
1
28
27
VCC
20
Select
PError
BUSY
ACK
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PSTROBE
1
8
10
12
15
LPT_SLCT
LPT_PE
LPT_BUSY
LPT_ACK#
2
13
13
13
13
LPT_STB#_R
LPT_AFD#
LPT_PDD0
LPT_ERR#
LPT_PDD1
LPT_INIT#
LPT_PDD2
LPT_SLIN#
LPT_PDD3
PD_7
PD_6
PD_5
PD_4
PD_3
PD_2
PD_1
PD_0
STROBE
LPT_PDD7
LPT_PDD6
LPT_PDD5
LPT_PDD4
LPT_PDD3
LPT_PDD2
LPT_PDD1
LPT_PDD0
LPT_STB#_R
16
17
18
19
21
23
24
25
26
LPT_PD[7..0]
SelectIn
INIT
AUTOFD
C150
0.1U_4_Y_16V
LPT_PDD4
LPT_PDD5
LPT_PDD6
LPT_PDD7
LPT_PD[7..0]
LPT_ACK#
13
LPT_BUSY
GND
22
LPT_PE
FAULT
LPT_SLCT
PACSZ128402_QSOP28
IO_GND
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
LPT1
262728
U18
C1
C2
Q8
BAT54A_SOT23_3
IO_GND
DB25
Figure 4-38: LPT Reference Schematic
FLOPPY(only Device A)
R199
1K_4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
FDD1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
BOXHEADER_2X17_2.54_BLACK
Figure 4-39: Floppy Reference Schematic
Page 78
+V5
R200
1K_4
R201
1K_4
R202
1K_4
R203
1K_4
FDD_RWC#
13
FDD_INDEX# 13
FDD_MOA#
13
FDD_DSA#
13
FDD_DIR#
13
FDD_STEP# 13
FDD_WD#
13
FDD_WE#
13
FDD_TRACK0# 13
FDD_WP#
13
FDD_RDATA# 13
FDD_HEAD# 13
FDD_DSKCHG# 13
ICE Module
IR CONNECTOR
+V5
UART_RX2
UART_TX2
IR1
IR_5X1_2.54
1
2
3
4
5
C260
0.1U_4_Y _16V
Figure 4-40: IR Reference Schematic
4.13 VGA
COM Express provides analog display signals. There are three signals -- red, green,
and blue -- that send color information to a VGA monitor. These three signals each
drive an electron gun that emits electrons which paint one primary color at a point on
the monitor screen. Analog levels between 0 (completely dark) and 0.7 V (maximum
brightness) on these control lines tell the monitor what intensities of these three
primary colors to combine to make the color of a dot (or pixel) on the monitor’s screen.
4.13.1 Signal Description
Table 4-23 shows COM Express VGA signals, including pin number, signals, I/0,
power plane, terminal resistors, damping resistors and descriptions.
Table 4-23: VGA signals description
Pin
D-SUB15
Signal
I/O
Description
B89
1
VGA_RED
O Analog
B91
2
VGA_GRN
O Analog
B92
3
VGA_BLU
O Analog
B93
13
VGA_HSYNC
B94
14
VGA_VSYNC
B95
15
VGA_I2C_CK
O 3.3V
CMOS
O 3.3V
CMOS
I/O 3.3V
CMOS
Red component of analog DAC monitor
output, designed to drive a 37.5Ω equivalent
load.
Green component of analog DAC monitor
output, designed to drive a 37.5Ω equivalent
load.
Blue component of analog DAC monitor
output, designed to drive a 37.5Ω equivalent
load.
Horizontal sync output to VGA monitor.
B96
VGA_I2C_DAT
I/O 3.3V
CMOS
Vertical sync output to VGA monitor.
DDC clock line (I2C port dedicated to
identify VGA monitor capabilities). DDC data
line.
DDC clock line (I2C port dedicated to
identify VGA monitor capabilities). DDC data
Page 79
ICE Module
5-8,10
9
GND
DDC_POWER
4,11
NC
line.
Analog and Digital GND
5V DDC supply voltage for monitor
EEPROM
Not Connected
4.13.2 VGA Connector
Figure 4-41: VGA Connector D-SUB15
4.13.3 VGA DAC Filter
A video filter is required for each CRT DAC output. This video filter is to be placed in
close proximity to the VGA connector. The separation between each of the three video
filters for the RGB channels should be maximized if possible to minimize crosstalk.
4.13.4 Routing Guide Line
4.13.4.1 HSYNC and VSYNC Signals
The horizontal and vertical sync signals 'VGA_HSYNC' and 'VGA_VSYNC' provided
by the COM Express module are 3.3V tolerant outputs. Since VGA monitors may drive
the monitor sync signals with 5V tolerance, it is necessary to implement high
impedance unidirectional buffers. These buffers prevent potential electrical over-stress
of the module and avoid that VGA monitors may attempt to drive the monitor sync
signals back to the module
4.13.4.2 ESD
For optimal ESD protection, additional low capacitance clamp diodes should be
implemented on the monitor sync signal and DAC. Please see the reference
schematic.
4.13.4.3 DDC Interface
COM Express provides a dedicated I2C bus for the VGA interface. It corresponds to
the VESA defined DDC interface that is used to read out the CRT monitor specific
Extended Display Identification Data (EDID). The appropriate signals 'VGA_I2C_DAT'
and 'VGA_I2C_CK' of the COM Express module are supposed to be 3.3V tolerant..
Page 80
ICE Module
ICE Module implement the LVDS EDID ROM on board. If Customer want to fix
the resolution or EDID information, please contact IEI for ODM Service.
4.13.5 VGA Reference Design
This reference design shows a circuitry implementing a VGA port.
IO_GND
A
K
+V3.3
D1
+V3.3
IO_GND
C123
10P_4_N_50V
C124
22P_4_N_50V
1
2
G
2
12
CRT_DDCDATA R160
13
CRT_HSY NC
R162
1
2 33_4
14
CRT_VSY NC
R164
1
2 33_4
15
CRT_DDCCLK R165
1
2 33_4
1
2 33_4
VGA_I2C_DAT_Z
R161 1
VGA_I2C_DAT
2 0_4
+V3.3
VGA_I2C_DAT
VGA_HSY NC
VGA_VSYNC
VGA_I2C_CK_Z
R166 1
2 0_4
IO_GND
VGA_I2C_CK
+V3.3
IO_GND
K
C
L7
FB47_6_300MA
R157
@2.7K_4
S
IO_GND
11
D4
BAV99LT1G_SOT23
C125
10P_4_N_50V
C
R167
150_4_1%
CRT_B_Y
16
VGA SOCKET
<1ST PART FIELD>
BAV99LT1G_SOT23
L8
FB47_6_300MA
D
@2N7002_SOT23
17
D3
VGA_BLU
Q7
CON7
6
1
7
2
8
3
9
4
10
5
A
K
+V3.3
VGA_I2C_DAT_Z
A
CRT_B
C122
10P_4_N_50V
IO_GND
R159
@2.2K_4
VGA_I2C_CK
K
C121
22P_4_N_50V
S
D5
BAV99LT1G_SOT23
C
C120
10P_4_N_50V
2
A
C
CRT_R
CRT_G
R163
150_4_1%
R158
@2.7K_4
D
+V3.3
@2N7002_SOT23
BAV99LT1G_SOT23
L6
FB47_6_300MA
+V5
VGA
D2
CRT_G_Y
@2.2K_4
Q6
1
R156
VGA_I2C_CK_Z
IO_GND
K
IO_GND
L5
FB47_6_300MA
+V3.3
G
C119
10P_4_N_50V
+V3.3
VGA_GRN
+V3.3
+V5
1
BAV99LT1G_SOT23
L4
FB47_6_300MA
C118
22P_4_N_50V
A
CRT_R_Y
2
C117
10P_4_N_50V
1
R155
150_4_1%
C
L3
FB47_6_300MA
VGA_RED
CRT_VSY NC
CRT_HSY NC
IO_GND
C127
@22P_4_N_50V
C126
@22P_4_N_50V
Figure 4-42: VGA Reference Design
Page 81
ICE Module
4.14 Miscellaneous
This section describes some signals which are not described above, including PI[3:0],
GPO[3:0], Watch Dog Timer, Speaker Out, System Reset, Carrier Board Reset,
Suspend Control, Power Good, Smart Fan Control,I2C Data, Alert#.
4.14.1 Signal Description
Table 4-24: Miscellaneous pin assignment
Pin
Signal
I/O
Description
B12
PWRBTN#
I CMOS
B49
SYS_RESET#
I CMOS
B50
CB_RESET#
O CMOS
PWR_OK
I CMOS
B18
SUS_STAT#
O CMOS
A15
PM_SLP_S3#
O CMOS
A18
PM_SLP_S4#
O CMOS
A24
PM_SLP_S5#
O CMOS
B66
B67
WAKE0#
WAKE1#
I CMOS
I CMOS
A27
B35
BATLOW#
THRM#
I CMOS
I CMOS
A35
THERMTRIP#
O CMOS
C77
C67
B13
B14
FAN_TACHOIN
FAN_PWMOUT
SMB_C
SMB_DAT
I CMOS
O CMOS
I/O 3.3V
OD
CMOS
B33
B34
B15
I2C_CK
I2C_DAT
SMB_ALERT#
I/O 3.3V
CMOS
I 3.3V
CMOS
B32
SPKR
O CMOS
Power button to bring system out of S5 (soft off), active on
rising edge.
Reset button input. Active low input. System is held in
hardware reset while this input is low, and comes out of
reset upon release.
Reset output from module to Carrier Board. Active low.
Issued by module chipset and may result from a low
SYS_RESET# input, a low PWR_OK input, a VCC_12V
power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module
software.
Power OK from main power supply. A high value indicates
that the power
Indicates imminent suspend operation; used to notify LPC
devices.
Indicates system is in Suspend to RAM state. Active low
output.
Indicates system is in Suspend to Disk state. Active low
output.
Indicates system is in Soft Off state. Also known as
"PS_ON" and can be used to control an ATX power supply.
PCI Express wake up signal.
General purpose wake up signal. May be used to
implement wake-up on PS2 keyboard or mouse activity.
Indicates that external battery is low.
Input from off-module temp sensor indicating an over-temp
situation.
Active low output indicating that the CPU has entered
thermal shutdown.
0V~5V Fan Tachometer Input
Fan Speed Control PWM Control
System Management Bus (SMBus) is used by the COM
Express module for memory configuration and clock
synthesizer configuration. It is also used by the external
PCI Express slots and ExpressCard slots.
General purpose I2C bus for common usage on the carrier
board.
The SMBus alert signal used by the SMBus slave to inform
the SMBus master " Optional signal used by the SMBus
slave. that a slave transaction is pending.
Output for audio enunciator - the "speaker" in PC-AT
Page 82
ICE Module
A34
BIOS_DISABLE#
I CMOS
B27
WDT
O CMOS
A86
KBD_RST#
I CMOS
A87
KBD_A20GATE
I CMOS
GPO[0:3]
OI CMOS
GPI[0:3]
I CMOS
TYPE[0:2]#
TBD
systems
Module BIOS disable input. Pull low to disable module
BIOS. Used to allow off-module BIOS implementations.
Output indicating that a watchdog time-out event has
occurred.
Input to module from (optional) external keyboard
controller that can force a reset. Pulled high on the module.
This is a legacy artifact of the PC-AT.
Input to module from (optional) external keyboard
controller that can be used to control the CPU A20 gate
line. The A20GATE restricts the memory access to the
bottom megabyte and is a legacy artifact of the PC-AT.
Pulled low on the module.
General purpose output pins. Upon a hardware reset,
these outputs should be low.
General purpose input pins. Pulled high internally on the
module.
The TYPE pins indicate to the Carrier Board the Pin-out
Type that is implemented on the module. The pins are tied
on the module to either ground (GND) or are no-connects
(NC). For Pin-out Type 1, these pins are don’t care (X).
TYPE2# TYPE1# TYPE0#
X
X
X
Pin-out Type 1
NC
NC
NC Pin-out Type 2
NC
NC
GND Pin-out Type 3 (no IDE)
NC
GND
NC Pin-out Type 4 (no PCI)
NC
GND
GND Pin-out Type 5 (no IDE, no
PCI)
The Carrier Board should implement combinatorial logic
that monitors the module TYPE pins and keeps power off
(e.g deactivates the ATX_ON signal for an ATX power
supply) if an incompatible module pin-out type is detected.
The Carrier Board logic may also implement a fault
indicator such as an LED.
PS: In IEI carrier board, these pins are for future use.
Page 83
ICE Module
4.14.2 Speaker/FAN Control/RTC Reference
4.14.2.1 Speaker Out
+V5
R321
Buzzer
+V5S_BUZZER
33_4
1
2
SP1
SATG1205NP45_DIP12X10_6.5
C
C246
0.1U_4_Y_16V
3,18,21
2
2.7K_4
E
1
R325
SPKR
B
Q14
2N3904_SOT23
Figure 4-43: Speaker Out Reference Schematic
4.14.2.2 FAN Control
+V12
CPU FAN W/FAN Control
C240
2
1
+V12
0.1U_4_Y _16V
C268
+V5
10UF_1210_16V
FAN1
R313
4.7K
1
2
3
4
GND
+12V
SENSE
CONTROL
1N4148
D33
1K_4
FAN_PWM1
FAN_PWM1 1K_4
FAN_IO1
FAN_IO1
13
R315
10K_4
CPUFAN_4_2.54
13
R314
R316
+V12
SYSTEM FAN W/FAN Control
1K_4
R320 G
Q13
FAN2
FDN335N
C244
Q22
2N3906_SOT23_3
1N4148
R317
D34
4.7K
1K_4
2
1
3
2
1
E
B
1K_4
S
FAN_PWM2
R402
+V5
DET
VCC
GND
13
4.7K
C
D
+V12
R374
C245
10UF_1210_16V
0.1U_4_Y _16V
R318
C263
0.1U_4_Y _16V
FAN_IO2
FAN_IO2
13
R319
10K_4
SYSTEM FAN2 W/FAN Control from COM module
+V12
R411
+V12
4.7K
R410 G
Q18
FDN335N
FAN3
E
2
Figure 4-44: FAN Reference Schematic
Page 84
C261
Q23
2N3906_SOT23_3
1N4148
R407
D35
4.7K
1K_4
1
3
2
1
C
D
1K_4
S
3 FAN_PWMOUT
1K_4
DET
VCC
GND
R412
B
+V5
C262
10UF_1210_16V
0.1U_4_Y _16V
R409
C264
0.1U_4_Y _16V
FAN_TACHOIN 3
R408
10K_4
ICE Module
4.14.2.3 RTC
Q10,C234 and R304 are for the no battery solution. Using super CAP to instead of
Battery.
Q10
CLEAR CMOS/Super CAP
A1
C
1
+V3.3_DUAL
1K_4
A2
2
BAT54C
SOT23_AAC
R304
JP9(1-2)
JUMP_1X2_2.54mm
C235
Q11
0.22F Super Cap
A1
C
R305
1K_4
3
BT2
JP9
2
CON3_HDR
BAT54C
SOT23_AAC
BAT1
CR2032-HOLDER
A2
1
R307
1K_4
+VBAT
C237
10U_8_X_6V3
C239
0.1U_4_Y _16V
DCBAT_3V
Figure 4-45: RTC Reference Schematic
Page 85
ICE Module
Chapter
5
5 PCB Stack and
Power Deliver Design
Page 86
ICE Module
5.1 Chapter Overview
A brief description of the Printed Circuit Board (PCB) for COM Express based board is
provided in this section. From a cost- effectiveness point of view, a four-layer board is
the target platform for the motherboard design.
For better quality, a six-layer or
8-layer board is preferred. This chapter also provides the ATX/AT power supply design
recommendation for customer’s reference. IEI ICE module carrier board use 4-layer
PCB stack.
5.2 Microstrip or Stripline
Either edge-coupled microstrip, edge-coupled stripline, or broad-side striplines are
recommended for designs with differential signals. Designs with microstrip lines offer
the advantage that a lower number of layers can be used. Also, with microstrip lines it
may be possible to route from a connector pad to the device pad without any via. This
provides better signal quality on the signal path that connects devices. A limitation of
microstrip lines is that they can only be routed on the two outside layers of the PCB,
thus routing channel density is limited.
Stripline may be either edge-coupled or broad-side coupled lines. Stripline designs
provide additional shielding since they are embedded in the board stack and are
typically sandwiched between ground and power planes. This reduces radiation and
coupling of noise onto the lines. Striplines have the disadvantage that they require the
use of vias to connect to them.
5.3 PCB Stackup Example
It is recommended to use PCB's with at least a 4-layer stackup where the impedance
controlled layer 1 (top layer) is used for differential signals and layer 4 (bottom layer)
for other periodic signals (CMOS/TTL). The dedicated power planes (layer 2 – GND
and layer 3 – VCC) are typically required for high-speed designs. The solid ground
plane is necessary to establish a controlled (known) impedance for the transmission
line interconnects. A narrow spacing between power and ground planes will
additionally create an excellent high frequency bypass capacitance. The following
example shows a four layer PCB stackup using microstrip trace routing. A good rule to
follow for microstrip designs is to keep S < W and S < H (“H” = space between
differential signal layers and the reference plane). The best practice is to use the
closest spacing, “S,” allowed by your PCB vendor and then adjust trace widths, “W,” to
control differential impedance.
Page 87
ICE Module
5.3.1 Four-Layer Stack-up
Figure 5-1 below is an example of a four layer stack-up. Layers L1 and L4 are used for
signal routing. Layers L2 and L3 are used for solid ground and power planes
respectively. Microstrips on Layers 1 and 4 reference ground and power planes on
Layers 2 and 3 respectively. In some cases, it may be advantageous to swap the GND
and PWR planes. This allows Layer 4 to be GND referenced. Layer 4 is clear of parts
and may be the preferred primary routing layer.
Figure 5-1: Four Layers Stack
5.3.2 Six-Layer Stack-up
Figure 5-2 below is an example of a six layer stack-up. Layers L1, L3, L4 and L6 are
used for signal-routing. Layers L2 and L5 are power and ground planes respectively.
Microstrips on Layers 1 and 6 reference solid ground and power planes on Layers 2
and 5 respectively. Inner Layers 3 and 4 are asymmetric striplines that are referenced
to planes on Layers 2 and 5.
Page 88
ICE Module
Figure 5-2: Six Layers Stack
NOTE:
ƒ
All high-speed signals should reference solid ground planes through
the length of their routing and should not cross plane splits. To
guarantee this, both planes surrounding strip-lines should be GND.
ƒ
IEI recommends that high-speed signal routing be done on internal,
strip-line layers.
ƒ
For high-speed signals transitioning between layers next to the
component, the signal pins should be accounted for by the GND
stitching vias that would stitch all the GND plane layers in that area of
the board.
Page 89
ICE Module
High-speed routing on external layers should be minimized in order to
ƒ
avoid EMI. Routing on external layers also introduces different delays
compared to internal layers. This makes it extremely difficult to do
length matching if routing is done on both internal and external layers.
5.4 ATX Power Delivery Guidelines
The COM Express module uses a single main power rail with a nominal value of +12V.
Two additional rails are specified: a +5V standby power rail and a +3V battery input to
power the module Real-time Clock (RTC) circuit in the absence of other power
sources. The +5V standby rail may be left unconnected on the Carrier Board if the
standby functions are not required by the application. Likewise, the +3V battery input
may be left open if the application does not require the RTC to keep time in the
absence of the main and standby sources. There may be module specific concerns
regarding storage of system setup parameters that may be affected by the absence of
the +5V standby and / or the +3V battery.
The rationale for this power-delivery scheme is:
ƒ
Module pins are scarce. It is more pin-efficient to bring power in on a
higher voltage rail.
ƒ
Lithium ion battery packs for mobile systems are most prevalent with a
+14.4V output. This is well suited for the +12V main power rail.
ƒ
Contemporary chipsets have no power requirements for +5V other than to
provide a reference voltage for +5V tolerant inputs. No COM Express
module pins are allocated to accept +5V except for the +5V standby pins.
In the case of an ATX supply, the switched (non standby) +5V line would
not be used for the COM Express module, but it might be used elsewhere
on the Carrier Board.
Page 90
ICE Module
5.4.1 ATX Power Status (S0,S3,S4,S5,G3)
ATX power source will provide 12V , -12V , 5V , -5V , 3.3V , 5VSBY power , if other
voltage is required (3.3VSBY , LAN1.8V…. ) on carried board. The additional
switching regulator or LDO will be necessary. Power states are described by the
following terms:
Table 5-1: Signal Tables Terminology Descriptions
State
Description
Comment
G3
Mechanical Off
AC power to system is removed, by a mechanical switch. System
power consumption is near zero – the only power consumption is
that of the RTC circuits powered by a backup battery.
Soft Off
System is off except for a small subset that is powered by the 5V
suspend rail. There is no system context preserved.
VCC_5V_SBY current consumption is system dependent, and it
may be from tens of milliamps up to several hundred milliamps.
Suspend to Disk
System is off except for a small subset that is powered by the 5V
suspend rail. System context is preserved on a non-volatile disk
media (that is powered off). VCC_5V_SBY current consumption
is system dependent, and it may be from tens of milliamps up to
several hundred milliamps.
S3
Suspend to RAM
System is off except for system subset that includes the RAM.
Suspend power is provided by the 5V suspend rail. System
context is preserved in the RAM. VCC_5V_SBY current
consumption is system dependent, and it may be from several
hundred milliamps up to a maximum of 2A.
S0
On
System is on.
S5
S4
Table 5-2: Power State Behavior
State
SUS_S5#
SUS_S4#
SUS_S3#
G3
N/A
N/A
N/A
S5
Low
Low
Low
S4
High
Low
Low
S3
High
High
Low
S0
High
High
High
Page 91
ICE Module
5.4.2 ATX Power Diagram
Battery(3.3V)
+12V
COM-Express
Module
+5VSB
ATX Power
Source
LD
O
+3.3VSB
+5V
+3.3V
-12V
-5V
Figure 5-3: ATX Power Delivery Block Diagram
6.3.3 ATX Power On Timing
+VBAT(3.3V)
+V5SB
PWR_BTN#
SUS_S3#
PS_ON#
+V12
+V5,+V3.3
ICE Power Rail
CB_RESET#
PCI_RESET#
BIOS Starts
T0
T1
T2
T3 T4 T5 T6
Figure 5-4: ATX Power On Sequence
Page 92
T7
T8
ICE Module
Table 5-3: ATX Power On Sequence Timing
Parameters
T0
T1
T2
T3
T4
T5
T6
T7
T8
min
Max
Description
5.5 AT Power Delivery Guideline
AT power source will provide 12V, 5V power. The additional switching regulator or
LDO will be required to simulate the ATX power (3.3V…). There will be no standby
voltage once AT power source be used.
5.5.1 AT Power Diagram
12V
COMExpress
Module
AT Power
Source
5V
3.3V
Figure 5-5: AT Power Delivery Block Diagram
Page 93
ICE Module
5.5.2 AT Power On Timing
+VBAT(3.3V)
+V12
+V5,+V3.3
SUS_S3#
ICE Power Rail
CB_RESET#
PCI_RESET#
BIOS Starts
T0
T1
T2
T3
T4
T5
T6
Notes: Do not need 5VSB.
Figure 5-6: AT Power On Sequence
Table 5-4: AT Power On Sequence Timing
Parameters
T0
T1
T2
T3
T4
T5
T6
min
Max
Description
NOTE:
Please follow the power requirement provided in Chapter 2 to design the
baseboard requested by the customer.
Page 94
ICE Module
Chapter
6
6 Mechanical Design
Guidelines
Page 95
ICE Module
6.1 Chapter Overview
The interconnection between COM Express modules and the carrier board uses two
220 pin 0.5mm fine pitch board-to-board connectors. Each single 220-pin connector is
split into two connector rows. This results in a total of 440 pins and 4 connector rows.
These connectors should be capable of driving up to 6.25GHz Low Voltage Differential
Signals to match the requirements for PCI Express signaling.
6.2 COM Module and Carrier Board Connector
6.2.1 Module Connector
The module connector for Pin-out Types 2 through 5 shall be a 440-pin receptacle that
is composed of 2 pieces of a 220-pin, 0.5 mm pitch receptacle. The pair of connectors
may be held together by a plastic carrier during assembly to allow handling by
automated assembly equipment. Module Pin-out Type 1 shall use a single 220-pin,
0.5 mm pitch receptacle. The connectors shall be qualified for LVDS operation up to
6.25GHz, to support PCI Express Generation 2 signaling speeds.
AMP / Tyco 3-1318490-6 0.5 mm pitch Free Height 220 pin 4H Receptacle, or
equivalent
AMP / Tyco 8-1318490-6 0.5 mm pitch Free Height 220 pin 4H Receptacle, or
equivalent
Sources for the individual 220-pin receptacle are (same as previous part, but with
anti-wicking solution applied) A source for the combined 440-pin receptacle
(composed of 2 pieces of the 220 pin receptacle held by a carrier) is: AMP / Tyco
3-1827231-6 0.5mm pitch Free Height 440 pin 4H Receptacle or equivalent. Note: the
part number above shown with a leading ‘8’ has an anti-wicking solution applied that
may help in processing with an aggressive flux. The other versions of the parts may
also be made available with this solution by the vendor. The module connector is a
receptacle by virtue of the vendor’s technical definition of a receptacle, and to some
users it looks like a plug.
Page 96
ICE Module
Figure 6-1: Module Connector Picture
6.2.2 Carrier Board Connector
The single 220-pin 0.5mm pitch carrier board connectors are 5H/8H plug in connectors
with a board-to-board stack height of 5.0mm/8.0mm. A potential source for this plug-in
board-to-board connector is:
3-1827253-6 AMP/Tyco HARD TRAY ASSY FH 0.5 BTB CONNECTOR 220POS
PLUG 5H WITH GROUND PLATE (5.0mm stack height)
8-1318491-6 AMP/Tyco HARD TRAY ASSY FH 0.5 BTB CONNECTOR 220POS
PLUG 8H WITH GROUND PLATE (8.0mm stack height)
Figure 6-2: Carrier Board Connector
Page 97
ICE Module
6.3 Connector Footprint
For carrier board designs it is essential that the distance and the alignment of the dual
connector shape on the PCB comply to the dimensions defined by the COM Express
Specification. The alignment between the two single connectors is guaranteed by the
connectors peg holes shown in following drawings. It is very important that the PCB
drill tolerances of these peg holes are within the recommended ranges mentioned
below. Otherwise, the interconnection between module and carrier board may cause
functional problems for the system. Instead of two single connectors, a dual connector
model with a reinforcing bar spacer can be used to ensure the alignment between the
two connectors during assembly. All dimensions of the following drawings are shown
in millimeters or Hirose FX8-100S connector detail spec, please reference the Hirose
website.
Figure 6-3: Single Connector Physical Dimensions
Figure 6-4: Dual Connector Footprint and Alignment
Page 98
ICE Module
The COM Express PnP Initiative strongly recommends to use the following
location
peg hole tolerances instead of those indicated in the footprint drawings from
the
COM Express Specification as shown above:
• 0.8mm +0.075/-0.025mm
• 1.5mm +0.075/-0.025mm
6.4 COM Express Form Factors
The COM Express specification was developed by the PCI Industrial Computer
Manufacturing Group (PICMG) in close collaboration with many leading companies
across the embedded industry in order to find an implementation solution to handle
upcoming new high speed serial I/Os, processors and chipsets. COM Express
specifies two form factors, as well as five different types of connector pinouts. The two
form factors are referred to as Basic and Extended. The Basic module footprint is
125mm x 95mm and focuses on space-constrained, low power systems which
typically do not contain more than one horizontal mounted SO-DIMM. The Extended
footprint is slightly larger at 155mm x 110mm and supports up to two full size, vertically
mounted DIMM modules to accommodate larger memory configurations for
high-performance CPUs, chipsets and multiprocessor systems. The placement of the
shielded 220-pin connectors and the mounting holes are identical between these two
footprints.
Page 99
ICE Module
Figure 6-5: Compact, Basic and Extended Form Factor
6.5 Heat Spread
An important factor for each system integration is the thermal design. The
heatspreader acts as a thermal coupling device to the Module. Usually It is a 3mm
thick aluminum plate. The heatspreader is thermally coupled to the CPU via a thermal
gap filler and on some Modules it may also be thermally coupled to other heat
generating components with the use of additional thermal gap fillers. Although the
heatspreader is the thermal interface where most of the heat generated by the Module
is dissipated, it is not to be considered as a heat sink. It has been designed to be used
as a thermal interface between the Module and the application specific thermal
solution.
The application specific thermal solution may use heat sinks with fans, and/or heat
pipes, which can be attached to the heatspreader. Some thermal solutions may also
require that the heatspreader is attached directly to the systems chassis therefore
using the whole chassis as a heat dissipater. The main mechanical mounting solutions
for systems based on COM Express Modules have proven to be the 'top-mounting'
and 'bottom-mounting' solutions. The decision as to which solution will be used is
determined by the mechanical construction and the cooling solution of the customer's
system. There are two variants of the heatspreader, one for each mounting possibility.
Page 100
ICE Module
One version has threaded standoffs and the other has non-threaded standoffs (bore
hole). The following sections describe these two common mounting possibilities and
the additional components (standoffs, screws, etc...) that are necessary to implement
the respective solution.
Modules should be equipped with a heat-spreader. This heat-spreader by it self does
not constitute the complete thermal solution for a module but provides a common
interface between modules and implementation-specific thermal solutions. The overall
module height from the bottom surface of the module board to the heat-spreader top
surface shall be 13 mm for both the Basic and Extended Modules. The module PCB
and heat-spreader plate thickness are vendor implementation specific, however, a
2-mm PCB with a 3-mm heat-spreader may be used which allows use of readily
available standoffs.
Figure 6-6: Overall Height for Heat-Spreader in Basic and Extended Modules
All dimensions in mm. Tolerances (unless otherwise specified): Z (height) dimensions
should be ± 0.8mm [±0.031”] from top of Carrier Board to top of heat-spreader.
Heat-spreader surface should be flat within 0.2mm [.008"] after assembly. Interface
surface finish should have a maximum roughness average (Ra) of 1.6μm [63μin]. The
critical dimension in Figure 6-8 is the module PCB bottom side to heat-spreader top
side. This dimension shall be 13.00mm ± 0.65mm [±0.026”]. Figure 6-8 shows a cross
section of a module and heat-spreader assembled to a Carrier Board using the 5mm
stack height option. If 8mm Carrier Board connectors are used, the overall assembly
height increases from 18.00mm to 21.00mm.
Page 101
ICE Module
Figure 6-7: Basic Module Heat-Spreader
Figure 6-8: Basic Module Heat-Spreader Footprint
Page 102
ICE Module
All dimensions are in mm. X-Y tolerances shall be ± 0.3mm [±0.012"].
The interior holes at coordinates (40, 40) and (80, 40) are tapped through holes with a
M2.5 thread. The interior holes do not receive standoffs. These holes may be sealed
on the module side by an adhesive backed foil, or they may be blind tapped holes with
a minimum thread depth of 2.5 mm. They are intended to allow additional attachment
points to the heat-spreader from outside the module.
Figure 6-9: IEI Heat Spread Module
6.6 Design Notes
6.6.1 Component Height — Module Back and Carrier Board Top
Parts mounted on the backside of the module (in the space between the bottom
surface of the module PCB and the Carrier Board) shall have a maximum height of 3.8
mm (dimension ‘B’ in Figure 6-11).
With the 5 mm stack option, the clearance
between the Carrier Board and the bottom surface of the module’s PCB is 5 mm
(dimension ‘A’ in Figure 6-11). Using the 5 mm stack option, components placed on
the Carrier Board topside under the module envelope shall be limited to a maximum
height of 1 mm (dimension ‘C’ in Figure 6-11), with the exception of the mating
connectors. Using Carrier Board topside components up to 1mm allows a gap of 0.2
mm between Carrier Board module bottom side components. This may not be
sufficient in some situations. In Carrier Board applications in which vibration or board
flex is a concern, then the Carrier Board component height should be restricted to a
value less than 1mm that yields a clearance that is sufficient for the application. If the
Carrier Board uses the 8 mm stack option (dimension ‘A’ in Figure 6-11), then the
Page 103
ICE Module
Carrier Board topside components within the module envelope shall be limited to a
height of 4 mm (dimension ‘C’ in Figure 6-11), with the exception of the mating
connectors. Using Carrier Board topside components up to 4mm allows a gap of 0.2
mm between Carrier Board topside components and module bottom side components.
This may not be sufficient in some situations. In Carrier Board applications in which
vibration or board flex is a concern, then the Carrier Board component height should
be restricted to a value less than 4 mm that yields a clearance that is sufficient for the
application.
Figure 6-10: Component Clearances Underneath Module
Page 104
ICE Module
6.6.2 Air Follow Issue
The air flow of the IEI COM Express fan module must be considered when installing a
COM Express system. Please refer to Figure 6-11 for air flow consideration.
6.6.3 Grounding Issue
The mounting holes on all ICE COM modules are connected to digital circuit ground
(GND) for improved EMC performance. Using conductive screws and distance
keepers will also connect the heat spreader and attached heat sink to GND. In some
applications the heat sink or heat spreader will be directly screwed with the inner
surface of the chassis. In some cases, however, it may not be desirable to have a
direct connection of circuit ground (GND) and chassis ground through the heat sink
and / or heat spreader. System designers should take this into account when defining
system grounding.
6.7 Others Kits Specification
6.7.1 Heat Sink
IEI provides a standard heat sink specially designed for COM Express module. The
fan in the heat sink can be removed if the fan is not needed.
Figure 6-11: IEI Heat Sink Module Dimensions
Page 105
ICE Module
Figure 6-12: IEI Heat Sink Module Picture
Page 106
ICE Module
Appendix
A
A ICE Module Design
Schematic Check List
Page 107
ICE Module
COM Module
PU/PD Series
-
Pin
C52
C53
Signal
PEG_RX0+
PEG_RX0-
D52
D53
C55
C56
PEG_TX0+
PEG_TX0PEG_RX1+
PEG_RX1-
-
D55
D56
C58
C59
PEG_TX1+
PEG_TX1PEG_RX2+
PEG_RX2-
-
D58
D59
C61
C62
PEG_TX2+
PEG_TX2PEG_RX3+
PEG_RX3-
-
D61
D62
C65
C66
PEG_TX3+
PEG_TX3PEG_RX4+
PEG_RX4-
-
D65
D66
C68
C69
PEG_TX4+
PEG_TX4PEG_RX5+
PEG_RX5-
-
D68
D69
C71
C72
PEG_TX5+
PEG_TX5PEG_RX6+
PEG_RX6-
-
D71
D72
C74
C75
PEG_TX6+
PEG_TX6PEG_RX7+
PEG_RX7-
-
Page 108
-
-
-
-
-
-
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
Notes
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
V
ICE Module
D74
D75
C78
C79
PEG_TX7+
PEG_TX7PEG_RX8+
PEG_RX8-
-
D78
D79
C81
C82
PEG_TX8+
PEG_TX8PEG_RX9+
PEG_RX9-
-
D81
D82
C85
C86
PEG_TX9+
PEG_TX9PEG_RX10+
PEG_RX10-
-
D85
D86
C88
C89
PEG_TX10+
PEG_TX10PEG_RX11+
PEG_RX11-
-
D88
D89
C91
C92
PEG_TX11+
PEG_TX11PEG_RX12+
PEG_RX12-
-
D91
D92
C94
C95
PEG_TX12+
PEG_TX12PEG_RX13+
PEG_RX13-
-
D94
D95
C98
C99
PEG_TX13+
PEG_TX13PEG_RX14+
PEG_RX14-
-
D98
D99
C101
C102
PEG_TX14+
PEG_TX14PEG_RX15+
PEG_RX15-
-
-
-
-
-
-
-
-
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
Page 109
ICE Module
D101
D102
A88
A98
D73
PEG_TX15+
PEG_TX15PCIE_CLK_REF+
PCIE_CLK_REFSDVO_I2C_CLK
-
0.1U Cap
0.1U Cap
33 ohm
-
-
C73
SDVO_I2C_DATA
-
-
B66
WAKE0#
PU
If unused, these signals can be left as NC.
Pin
B68
B69
Signal
PCIE_RX0+
PCIE_RX0-
PU/PD
-
Series
-
A68
A69
B64
B65
PCIE_TX0+
PCIE_TX0PCIE_RX1+
PCIE_RX1-
-
0.1U Cap
0.1U Cap
-
A64
A65
B61
B62
PCIE_TX1+
PCIE_TX1PCIE_RX2+
PCIE_RX2-
-
A61
A62
B58
B59
PCIE_TX2+
PCIE_TX2PCIE_RX3+
PCIE_RX3-
-
A58
A59
B55
B56
PCIE_TX3+
PCIE_TX3PCIE_RX4+
PCIE_RX4-
-
A55
A56
B52
B53
PCIE_TX4+
PCIE_TX4PCIE_RX5+
PCIE_RX5-
-
Page 110
-
-
-
-
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
0.1U Cap
0.1U Cap
-
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Directly connect to PCIe Device or
Buffer IC
Directly connect to SDVO Transmitter.
Using 4.7K to 10K pull up to 2.5V.
Directly connect to SDVO Transmitter.
Using 4.7K to 10K pull up to 2.5V.
Connect to PCIE wake up signal
Notes
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Provide 0.1-μF AC coupling
capacitors (0402 or 0603 package)
and place them
near to TX side (near to destination)
V
ICE Module
A52 PCIE_TX5+
0.1U Cap
A53 PCIE_TX50.1U Cap
A88 PCIE_CLK_REF+
33 ohm
A98 PCIE_CLK_REFIf unused, these signals can be left as NC.
Pin
as per PCI-E Device
Directly connect to PCIe Device or
Slot.
Directly connect to PCIe Device or
Buffer IC
Signal
PCI_AD[0..31]
PCI_C/BE[0..3]#
PU/PD
-
Series
-
Notes
Directly connect to PCI Device
V
C36
PCI_DEVSEL#
PU
-
Directly connect to PCI Device
D36
PCI_FRAME#
PU
-
Directly connect to PCI Device
C37
PCI_IRDY#
PU
-
Directly connect to PCI Device
D35
PCI_TRDY#
PU
-
Directly connect to PCI Device
D34
PCI_STOP#
PU
-
Directly connect to PCI Device
D32
PCI_PAR
-
-
Directly connect to PCI Device
C34
PCI_PERR#
PU
-
Directly connect to PCI Device
PCI_REQ[0..3]#
PU
-
Directly connect to PCI Device
PCI_GNT[0..3]#
-
-
Directly connect to PCI Device
C23
PCI_RESET#
-
-
PCI_RESET# should be connected to
C35
PCI_LOCK#
PU
D33
PCI_SERR#
PU
-
Directly connect to PCI Device
C15
PCI_PME#
PU
-
Directly connect to PCI Device
D48
PCI_CLKRUN#
PU
-
Directly connect to PCI Device
PCI_IRQ[A..D]#
PU
-
Directly connect to PCI Device
33 ohm
Directly connect to PCIe Device or
Buffer IC
Directly connect to PCI Device
PCI slots and PCI down devices.
D50
PCI_CLK
Directly connect to PCI Device
If unused, these signals can be left as NC.
Pin
A19
A20
Signal
SATA0_RX+
SATA0_RX-
PU/PD
-
A16
A17
SATA0_TX+
SATA0_TX-
-
B19
B20
SATA1_RX+
SATA1_RX-
-
B16
B17
SATA1_TX+
SATA1_TX-
-
Series
0.01U
Cap
0.01U
Cap
0.01U
Cap
0.01U
Cap
0.01U
Cap
0.01U
Cap
0.01U
Cap
Notes
Directly connect to SATA Connector
V
Directly connect to SATA Connector
Directly connect to SATA Connector
Directly connect to SATA Connector
Page 111
ICE Module
0.01U
Cap
A25
SATA2_RX+
0.01U
A26
SATA2_RXCap
0.01U
Cap
A22
SATA2_TX+
0.01U
A23
SATA2_TXCap
0.01U
Cap
B25
SATA3_RX+
0.01U
B26
SATA3_RXCap
0.01U
Cap
B22
SATA3_TX+
0.01U
B23
SATA3_TXCap
0.01U
Cap
A28
SATA_ACT#
PU
If unused, these signals can be left as NC.
Directly connect to SATA Connector
Directly connect to SATA Connector
Directly connect to SATA Connector
Directly connect to SATA Connector
Please refer to ICE Demo Board
-
Pin
Signal
PU/PD Series
A46
USB0+
A45
USB0B46
USB1+
B45
USB1A43
USB2+
A42
USB2B43
USB3+
B42
USB3A40
USB4+
A39
USB4B40
USB5+
B39
USB5A37
USB6+
A36
USB6B37
USB7+
B36
USB7B44
USB_0_1_OC#
PU
A44
USB_2_3_OC#
PU
B38
USB_4_5_OC#
PU
If unused, these signals can be left as NC.
Notes
Pin
A30
A29
Signal
AC_RST#
AC_SYNC
PU/PD
-
Series
33 ohm
33 ohm
Notes
Directly connect to HAD Chip
Directly connect to HAD Chip
A32
AC_BITCLK
-
33 ohm
Directly connect to HAD Chip
A33
AC_SDOUT
-
33 ohm
Directly connect to HAD Chip
B30
B29
B28
AC_SDIN0
AC_SDIN1
AC_SDIN2
-
33 ohm
Directly connect to HAD Chip
Page 112
V
Directly connect to USB Device
Directly connect to USB Device
Directly connect to USB Device
Directly connect to USB Device
Directly connect to USB Device
Directly connect to USB Device
Directly connect to USB Device
Directly connect to USB Device
-
V
ICE Module
If unused, these signals can be left as NC.
Pin
B89
B91
Signal
VGA_RED
VGA_GRN
PU/PD
PD
PD
Series
-
Notes
Please refer to chapter 4
Please refer to chapter 4
B92
VGA_BLU
PD
-
Please refer to chapter 4
B93
VGA_HSYNC
-
Buffer
Please refer to chapter 4
B94
VGA_VSYNC
-
Buffer
Please refer to chapter 4
B95
VGA_I2C_CK
PU
-
Please refer to chapter 4
B96
VGA_I2C_DAT
PU
-
Please refer to chapter 4
V
If unused, these signals can be left as NC.
Pin
A71
A72
A73
A74
A75
A76
A78
A79
A81
A82
B71
B72
B73
B74
B75
B76
B77
B78
B81
B82
A77
Signal
LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2LVDS_A3+
LVDS_A3LVDS_A_CK+
LVDS_A_CKLVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2LVDS_B3+
LVDS_B3LVDS_B_CK+
LVDS_B_CKLVDS_VDD_EN
PU/PD
-
Series
-
Notes
Directly connect to LCD panel
-
-
Directly connect to LCD panel
-
-
Directly connect to LCD panel
-
-
Directly connect to LCD panel
-
-
Directly connect to LCD panel
-
-
Directly connect to LCD panel
-
-
Directly connect to LCD panel
-
-
Directly connect to LCD panel
-
-
Directly connect to LCD panel
-
-
Directly connect to LCD panel
PD
-
Please refer to chapter 4
B79
LVDS_BKLT_EN
-
-
Please refer to chapter 4
B83
-
-
Please refer to chapter 4
A83
LVDS_BKLT_CTR
L
LVDS_I2C_CK
PU
-
Directly connect to LCD panel
A84
LVDS_I2C_DAT
PU
V
Directly connect to LCD panel
If unused, these signals can be left as NC.
Pin
B97
Signal
TV_DAC_A
PU/PD
PD-
Series
-
Notes
Please refer to chapter 4
B98
TV_DAC_B
PD
-
Please refer to chapter 4
B99
TV_DAC_C
PD
-
Please refer to chapter 4
V
Page 113
ICE Module
If unused, these signals can be left as NC.
Pin
D7
Signal
IDE_D[0..15]
PU/PD
-
Series
-
Please refer to chapter 4
Notes
D13
D14
D15
D9
IDE_A[0:2]
-
-
Please refer to chapter 4
IDE_IOW#
-
-
Please refer to chapter 4
C14
IDE_IOR#
-
-
Please refer to chapter 4
D8
IDE_REQ
-
-
Please refer to chapter 4
D10
IDE_ACK#
-
-
Please refer to chapter 4
D16
IDE_CS1#
-
-
Please refer to chapter 4
D17
IDE_CS3#
-
-
Please refer to chapter 4
C13
IDE_IORDY
PU
-
Please refer to chapter 4
D18
IDE_RESET#
-
-
Please refer to chapter 4
D12
IDE_IRQ
PU
-
Please refer to chapter 4
D77
IDE_CBLID#
-
-
Please refer to chapter 4
V
If unused, these signals can be left as NC.
Pin
A13
A12
A10
A9
A7
A6
A3
A2
A14
Signal
GBE0_MDI0+
GBE0_MDI0GBE0_MDI1+
GBE0_MDI1GBE0_MDI2+
GBE0_MDI2GBE0_MDI3+
GBE0_MDI3GBE0_CTREF
PU/PD
PD RC
Series
-
Notes
Directly connect to LAN transformer
PD RC
-
Directly connect to LAN transformer
PD RC
-
Directly connect to LAN transformer
PD RC
-
Directly connect to LAN transformer
-
-
Please refer to chapter 4
A8
GBE0_LINK#
-
-
Please refer to chapter 4
A4
GBE0_LINK100#
-
-
Please refer to chapter 4
A5
GBE0_LINK1000#
-
-
Please refer to chapter 4
B2
GBE0_ACT#
V
Please refer to chapter 4
If unused, these signals can be left as NC.
Pin
A50
Signal
LPC_SERIRQ
PU/PD
-
Series
-
Please refer to chapter 4
B3
LPC_FRAME#
-
-
Please refer to chapter 4
B4
B5
B6
B7
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
-
-
Please refer to chapter 4
Page 114
Notes
V
ICE Module
B8
LPC_DRQ0#
B9
LPC_DRQ1#
B10
LPC_CLK
33ohm
If unused, these signals can be left as NC.
Please refer to chapter 4
Pin
B12
Notes
Signal
PWRBTN#
PU/PD
PU
Series
-
Please refer to chapter 4
B49
SYS_RESET#
PU
-
Please refer to chapter 4
B50
CB_RESET#
PU
-
Please refer to chapter 4
PWR_OK
PU
-
Please refer to chapter 4
B18
SUS_STAT#
-
-
Please refer to chapter 4
A15
PM_SLP_S3#
-
-
Please refer to chapter 4
A18
PM_SLP_S4#
-
-
Please refer to chapter 4
A24
PM_SLP_S5#
-
-
Please refer to chapter 4
B66
WAKE0#
PU
-
Please refer to chapter 4
B67
WAKE1#
PU
-
Please refer to chapter 4
A27
BATLOW#
PU
-
Please refer to chapter 4
B35
THRM#
PU
-
Please refer to chapter 4
A35
THERMTRIP#
PU
-
Please refer to chapter 4
C77
FAN_TACHOIN
PU
-
Please refer to chapter 4
C67
FAN_PWMOUT
PU
-
Please refer to chapter 4
B13
B14
SMB_CK
SMB_DAT
PU
-
Please refer to chapter 4
V
Page 115
ICE Module
Appendix
B
B Application Notes
Page 116
ICE Module
NOTE:
IEI is able to provide customers with the ICE module design guide and
information as well as many other application notes. IEI will keep the ICE
module information most updated. Please contact IEI for the latest design
guide and related information.
B.1 Terminology
Some of the following terms may be used throughout this section.
Term
Description
BIOS
Basic Input Output System. BIOS is actually firmware, the software that is
programmed into a ROM (Read-Only Memory) chip built onto the motherboard of
a computer
AFUWIN
AMI BIOS Update Tool
RTC
Real-Time Clock
B.2 Updating BIOS Version
There are two ways to update the BIOS version.
ƒ
In the OS environment, use AFUWIN application to update BIOS.
ƒ
In the DOS environment, use “GO” command to update BIOS.
The following sections describe how to use these two methods to update BIOS version.
Before updating BIOS, please check the BIOS version in the BIOS menu (Figure 6-13).
To get the BIOS menu, press the Delete key when the system is booting up.
Page 117
ICE Module
Figure 6-13: BIOS Main Menu (BIOS Version: MR10)
B.2.1 Using AFUWIN
To use AFUWIN application to update the BIOS version, follow the steps below.
Step 1: Install and launch AFUWIN.
Step 2: Click Open button to open the BIOS file (Figure 6-14).
Figure 6-14: AFUWIN – Open BIOS File
Page 118
ICE Module
Step 3: Locate the BIOS file that needs to be updated (Figure 6-15).
Figure 6-15: Locate BIOS File
Step 4: Check ”Program All Block” option (Figure 6-16).
Figure 6-16: Check Program All Block
Step 5: Click Flash button to start updating BIOS (Figure 6-17).
Page 119
ICE Module
Figure 6-17: AFUWIN – Flash
Step 6: Restart the system and check the BIOS menu. The BIOS version is changed
to MR11 (Figure 6-18).
Step 0:
Figure 6-18: BIOS Main Menu – Updated BIOS Version (MR11)
Page 120
ICE Module
6.7.2 Using DOS Command
To update BIOS in the DOS environment, prepare a USB flash drive that contains boot
files and BIOS updating files shown in Figure 6-19 and follow the steps below to
update BIOS.
Figure 6-19: USB Flash Drive and BIOS Updating Files
Step 1: Connect the USB flash drive to the system. Boot-up the system into DOS.
Input commands to get into the directory of the BIOS updating files
(ex. cd (folder name)). See Figure 6-20.
Figure 6-20: BIOS Updating File Directory
Page 121
ICE Module
Step 2: Input command GO and press Enter (Figure 6-21). The system starts
updating BIOS.
Figure 6-21: GO Command
Step 3: Figure 6-22 shows the screen when the updating is completed.
Figure 6-22: BIOS Updating Complete (DOS)
Step 4: Restart the system and check the BIOS menu. The BIOS version has been
changed to MR11 (Figure 6-23).
Page 122
ICE Module
Figure 6-23: BIOS Main Menu – Updated BIOS Version (MR11)
A.1 RTC Overview
A Real-time clock (RTC) is a basic hardware device that keeps track of the current
time of the computer. A RTC can be built in a chip or embedded in the system. When
the computer is turned off, the battery on the motherboard provides power to the RTC
to keep track of the current time. The RTC is usually used in personal computers and
embedded systems.
A.1.1 How to Calculate the Battery Life
The RTC requires an external battery connection to maintain functionality and its RAM
while the south bridge is not powered by the system.
The battery life can be calculated by dividing the capacity by the average current
required. For example, if the battery storage capacity is 170 mAh(assumed
usable)and the average current required is 6 μA, the battery life will be at least:
170,000μAh / 6 μA=28,333 h=3.2 years
The voltage oh the battery can affect the RTC accuracy. In general, when the battery
voltage decays, the RTC accuracy also decreases.
Page 123
ICE Module
Appendix
C
B Reference Carrier
Board Schematic
Page 124
Cover Page
PAGE1: Cover Page
PAGE2: System Block Diagram
PAGE3: COM_EXPRESS CONNECTOR
PAGE4: CLOCK BUFF
PAGE5: PCIEX1/EXPRESS CARD
PAGE6: PCIEX16
PAGE7: PCI SLOT1/2/3
PAGE8: MINI-PCI
PAGE9: PCI 80 PORT
PAGE10: PCI ExpressX1 Slot3/4
PAGE11: SATA,IDE,CF
PAGE12: LVDS/TV/CRT
PAGE13: SIO W83627EHG
PAGE14: SIO F81216D
PAGE15: LPT,FLOPPY,KB/MS/COM1
PAGE16: COM2,3,4,5,6/RS422,485
PAGE17: LAN,USB0,1,2,3,4,5
PAGE18: HDA ALC888
PAGE19: AUDIO 7.1CHANNEL
PAGE20: RTC/FAN/BIOS2/BUZZER
PAGE21: ATX POWER CONNECTOR
PAGE22: MISCELLANEOUS
PAGE23: Reversion History
PCI ROUTING
IDSEL
PREQ#
PGNT#
AD23
0
0
D,A,B,C
INT#
Mini PCI
DEVICE
AD22
3
3
C,D,A,B
PCISA SLOT3
AD21
2
2
B,C,D,A
PCISA SLOT2
AD20
1
1
A,B,C,D
PCISA SLOT1
Value Rule
@: Didn't install component.
P/N:Part_Number.
R: R_Package_(Precision) ; Package 4=0402, 6=0603, 8=0805, 12=1206, 1210=1210
L: L_Package_Current ; Package 4=0402, 6=0603, 8=0805, 12=1206, 1210=1210, DIP13.5X12, DIP16X8
C: C_Package_Material_Voltage ;
Package 4=0402, 6=0603, 8=0805, 12=1206, 1210=1210, DIP8=DIP phi=8, DIP10=DIP phi=10;
Material Y=Y5V, X=X7R, N=NPO, OS=OS CON, SP=SP CAP, POS=POS CAP, EC=EC CAP;
Voltage 6V3=6.3V..
D: D_Package_(Others) ; Package=SOT23...
Q: Q_Package_(Others) ; Package=SOT23, TO252, TO263, TO223, SO8
U: U_Package_(Others) ; Package=SSOP20, PQFP128, SO14...
IEI ELECTRONICS INC.
X: X_Package_(Others)
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
CN: CN function_Pin Count_Pin Pitch_(Others) ;
HEADER_2X6_2.54, ATX12V_2X2_4, DDRII_240_2
Title
COVER PAGE
Size
Document Number
Date:
Sunday , September 14, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
1
of
23
BUZZER
ATX/AT Power
SYSTEM FAN
+5V
+3.3V
Power Connector +12V
+5VSB
ATX2.0
SMART FAN
CPU FAN
Display Selection
Analog VGA
Audio 7.1 Channel
CD-IN
CENTER/LFE
SURROUND
FRONT_OUT
LINEIN_1/2
MIC_1/2
CRT Connector
LVDS ChannelA(18/24bits) LVDSA Connector
REALTEK
ALC888
LVDS ChannelB(18/24bits) LVDSB Connector
AC'97 / AZALIA
TV-Out
Embedded Connector
PCIEx16 / SDVO
PCIEx16 Connector
Six PCIEx1
PCIEx1 Slot 1
COMExpress
Module
SIO DIO1~8
Legacy IO
LPT
PCIEx1 Slot 2
PCIEx1 Slot 3
PS2 KB/MS
Floppy
Winbond SIO
W83627EHF
LPC
PCIEx1 Slot 4
WDT
USB port6
PCIE Express Card
COM1
USB port7
PCIE Mini Card
COM2/IR
PCI Bus
PCI Slot 1
COM3
COM4
COM5
PCI Slot 2
Fintek
F81216D
PCI Slot 3
COM6
(232/422/485)
Mini PCI Connector
Second BIOS
RJ45
USB Connector
CPLD
10/100Mbps or Giga LAN
USB 2.0 x8 (port0~port 7)
SATAx4
SATA x4
PIDE
IDE X1
I2C/SMBUS
Fintek
F75111R
Port 80 Display
GPIO1~8
I2C Bus
SMBus
CF
GPI1~4/GPO1~4
Battery
Super Cap
*No Battery Solution
IEI ELECTRONICS INC.
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
SYSTEM BLOCK DIAGRAM
Size
Document Number
Date:
Sunday , September 14, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
2
of
23
IDE_D[15..0]
PCI_AD[31..0]
+V12
+V12
IDE_D[15..0]
11
PCI_AD[31..0] 7,8,9
+V12
+V12
COMEXPRESS2
17 GBE0_MDI317 GBE0_MDI3+
17 GBE0_LINK100#
17 GBE0_LINK1000#
17 GBE0_MDI217 GBE0_MDI2+
17 GBE0_LINK#
17 GBE0_MDI117 GBE0_MDI1+
17 GBE0_MDI017 GBE0_MDI0+
+V1.8_LAN
13 PM_SLP_S3#
11 SATA0_TX+
11 SATA0_TXTP2
11 SATA0_RX+
11 SATA0_RX11
11
SATA2_TX+
SATA2_TXTP3
SATA2_RX+
SATA2_RXTP4
20,21 ATA_ACT#
18 AC_SY NC
18 AC_RST#
11
11
R1
0_4
1
1
1
18 AC_BITCLK
18 AC_SDOUT
20 BIOS_DISABLE#
1
TP9
5
USB65
USB6+
1
TP11
17
USB017
USB0+
17
USB417
USB4+
17 USB_2_3_OC#
17
USB217
USB2+
+VBAT
TP13
TP15
11,13,14 SERIRQ
10
10
20
10
10
PCIE_TX5+
PCIE_TX5GPI0
PCIE_TX4+
PCIE_TX4-
5
5
PCIE_TX3+
PCIE_TX3-
5
5
20
5
5
PCIE_TX2+
PCIE_TX2GPI1
PCIE_TX1+
PCIE_TX1-
20
5
5
GPI2
PCIE_TX0+
PCIE_TX0-
12
12
12
12
12
12
12
12
12
LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2LVDS_VDD_EN
LVDS_A3+
LVDS_A3-
12 LVDS_A_CK+
12 LVDS_A_CKTP30
TP31
20 GPI3
13
KB_RST#
13 KB_A20GATE
4 CLK100M_PCIE_REF+
4 CLK100M_PCIE_REF15 ATMEGA_SCK
15 ATMEGA_MOSI
20 GPO0
15 ATMEGA_MISO
15 ATMEGA_SS
1
1
1
1
EXCD0_RST#
LVDS_I2C_CK
LVDS_I2C_DAT
GBE0_CTREF
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
GND0
GBE0_MDI3GBE0_MDI3+
GBE0_LINK100#
GBE0_LINK1000#
GBE0_MDI2GBE0_MDI2+
GBE0_LINK#
GBE0_MDI1GBE0_MDI1+
GND1
GBE0_MDI0GBE0_MDI0+
GBE0_CTREF
SUS_S3#
SATA0_TX+
SATA0_TXSUS_S4#
SATA0_RX+
SATA0_RXGND2
SATA2_TX+
SATA2_TXSUS_S5#
SATA2_RX+
STAT2_RXBATLOW#
ATA_ACT#
AC_SY NC
AC_RST#
GND3
AC_BITCLK
AC_SDOUT
BIOS_DISABLE#
THRMTRIP#
USB6USB6+
USB6_7_OC#
USB4USB4+
GND4
USB2USB2+
USB2_3_OC#
USB0USB0+
VCC_RTC
EXCD0_PERST#
EXCD0_CPPE#
LPC-SERIRQ
GND5
PCIE_TX5+
PCIE_TX5GPI0
PCIE_TX4+
PCIE_TX4GND6
PCIE_TX3+
PCIE_TX3GND7
PCIE_TX2+
PCIE_TX2GPI1
PCIE_TX1+
PCIE_TX1GND8
GPI2
PCIE_TX0+
PCIE_TX0GND9
LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2LVDS_VDD_EN
LVDS_A3+
LVDS_A3GND10
LVDS_A_CLK+
LVDS_A_CLKLVDS_I2C_CK
LVDS_I2C_DAT
GPI3
KBD_RST#
KBD_A20GATE
PCIE0_CK_REF+
PCIE0_CK_REFGND11
RSVD0
RSVD1
GPO0
RSVD3
RSVD4
GND12
VCC_12V1
VCC_12V2
VCC_12V3
GND13
VCC_12V4
VCC_12V5
VCC_12V6
VCC_12V7
VCC_12V8
VCC_12V9
VCC_12V10
VCC_12V11
VCC_12V12
GND14
GND15
GBE0_ACT#
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ0#
LPC_DRQ1#
LPC_CLK
GND16
PWRBRN#
SMB_CK
SMB_DAT
SMB_ALERT#
SATA1_TX+
SATA1_TXSUS_STAT#
SATA1_RX+
SATA1_RXGND17
SATA3_TX+
SATA3_TXPWR_OK
SATA3_RX+
SATA3-RXWDT
AC_SDIN2
AC_SDIN1
AC_SDIN0
GND18
SPKR
I2C_CK
I2C_DAT
THRM#
USB7USB7+
USB4_5_OC#
USB5USB5+
GND19
USB3USB3+
USB0_1_OC#
USB1USB1+
EXCD1_PERST#
EXCD1_CPPE#
SY S_RESET#
CB_RESET#
GND20
PCIE_RX5+
PCIE_RX5GPO1
PCIE_RX4+
PCIE_RX4GPO2
PCIE_RX3+
PCIE_RX3GND21
PCIE_RX2+
PCIE_RX2GPO3
PCIE_RX1+
PCIE_RX1WAKE0#
WAKE1#
PCIE_RX0+
PCIE_RX0GND22
LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2LVDS_B3+
LVDS_B3LVDS_BKLT_EN
GND23
LVDS_B_CLK+
LVDS_B_CLKLVDS_BKLT_CTRL
VCC5SBY 1
VCC5SBY 2
VCC5SBY 3
VCC5SBY 4
RSVD5
VGA_RED
GND24
VGA_GRN
VGA_BLU
VGA_HSY NC
VGA_VSY NC
VGA_I2C_CK
VGA_I2C_DAT
TV_DAC_A
TV_DAC_B
TV_DAC_C
GND25
VCC_12V13
VCC_12V14
VCC_12V15
VCC_12V16
VCC_12V17
VCC_12V18
VCC_12V19
VCC_12V20
VCC_12V21
GND26
COMEXPRESS1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
B105
B106
B107
B108
B109
B110
1
SMB_ALERT# 1
SUS_STAT#
1
PWR_OK
AC_SDIN2
AC_SDIN1
1
1
1
EXCD1_RST#
WAKE0#
WAKE1#
1
1
GBE0_ACT#
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
TP1
CLK33M_LPC
17
5,11,13,14,20
5,11,13,14,20
5,11,13,14,20
5,11,13,14,20
5,11,13,14,20
11,13
PM_PWRBTN#
SMB_CK
SMB_DAT
TP5
SATA1_TX+
SATA1_TXTP6
SATA1_RX+
SATA1_RX-
13
4,5,6,10,11,17,20
4,5,6,10,11,17,20
SATA3_TX+
SATA3_TX-
11
11
SATA3_RX+
SATA3_RXWDT
TP7
TP8
AC_SDIN0
11
11
21
SPKR
I2C_CK
I2C_DAT
TP10
USB7USB7+
USB_4_5_OC#
USB5USB5+
18,20,21
17,20
17,20
USB3USB3+
USB_0_1_OC#
USB1USB1+
TP12
TP14
SY S_RESET#
CB_RESET#
17
17
17
17
17
21
5,6,10,11,14,20
PCIE_RX5+
PCIE_RX5GPO1
PCIE_RX4+
PCIE_RX4GPO2
PCIE_RX3+
PCIE_RX3-
10
10
20
10
10
20
5
5
PCIE_RX2+
PCIE_RX2GPO3
PCIE_RX1+
PCIE_RX1-
5
5
20
5
5
PCIE_RX0+
PCIE_RX0-
IDE_D7
IDE_D6
IDE_D3
IDE_D15
IDE_D8
IDE_D9
IDE_D2
IDE_D13
IDE_D1
13
11
11
11
11
IDE_D14
11
11
7,8
7
7
7
7
8
IDE_IORDY
IDE_IOR#
PCI_PME#
PCI_GNT#2
PCI_REQ#2
PCI_GNT#1
PCI_REQ#1
PCI_GNT#0
8
PCI_REQ#0
7,8,9,13 PCI_RST#
18
5
5
17
17
17
5
5
LVDS_B0+
12
LVDS_B012
LVDS_B1+
12
LVDS_B112
LVDS_B2+
12
LVDS_B212
LVDS_B3+
12
LVDS_B312
LVDS_BKLT_EN 12
LVDS_B_CK+ 12
LVDS_B_CK- 12
LVDS_BKLT_CRTL 12
+V5_DUAL
VGA_RED
12
VGA_GRN
VGA_BLU
VGA_HSY NC
VGA_VSY NC
VGA_I2C_CK
VGA_I2C_DAT
TV_DAC_A
TV_DAC_B
TV_DAC_C
12
12
12
12
12
12
12
12
12
COM_EXPRESS_A_REC
PCI_AD0
PCI_AD2
PCI_AD4
PCI_AD6
PCI_AD8
PCI_AD10
PCI_AD12
PCI_AD14
7,8,9
7,8
7
7,8
7,8,9
7,8,9
PCI_C/BE#1
PCI_PERR#
PCI_LOCK#
PCI_DEVSEL#
PCI_IRDY #
PCI_C/BE#2
PCI_AD17
PCI_AD19
PCI_AD21
PCI_AD23
7,8,9 PCI_C/BE#3
PCI_AD25
PCI_AD27
PCI_AD29
PCI_AD31
7,8 PCI_INT#A
7,8 PCI_INT#B
6
6
PEG_RX0+
PEG_RX0-
6
6
PEG_RX1+
PEG_RX1-
6
6
PEG_RX2+
PEG_RX2-
6
6
PEG_RX3+
PEG_RX3-
6
PEG_RX4+
6
PEG_RX420 FAN_PWMOUT
6
PEG_RX5+
6
PEG_RX56
6
6
6
6
PEG_RX6+
PEG_RX6SDVO_I2C_DAT
PEG_RX7+
PEG_RX7-
20 FAN_TACHOIN
6
PEG_RX8+
6
PEG_RX86
6
PEG_RX9+
PEG_RX9-
6
6
PEG_RX10+
PEG_RX10-
6
6
PEG_RX11+
PEG_RX11-
6
6
PEG_RX12+
PEG_RX12-
6
6
PEG_RX13+
PEG_RX13-
6
6
PEG_RX14+
PEG_RX14-
6
6
PEG_RX15+
PEG_RX15-
TP24
TP28
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
1 C54
C55
C56
1 C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
C109
C110
GND0
IDE_D7
IDE_D6
IDE_D3
IDE_D15
IDE_D8
IDE_D9
IDE_D2
IDE_D13
IDE_D1
GND1
IDE_D14
IDE_IORDY
IDE_IOR#
PCI_PME#
PCI_GNT2#
PCI_REQ2#
PCI_GNT1#
PCE_REQ1#
PCI_GNT0#
GND2
PCI_REQ0#
PCI_RESET#
PCI_AD0
PCI_AD2
PCI_AD4
PCI_AD6
PCI_AD8
PCI_AD10
PCI_AD12
GND3
PCI_AD14
PCI_CBE1#
PCI_PERR#
PCI_LOCK#
PCI_DEVSEL#
PCI_IRDY #
PCI_CBE2#
PCI_AD17
PCI_AD19
GND4
PCI_AD21
PCI_AD23
PCI_CBE3#
PCI_AD25
PCI_AD27
PCI_AD29
PCI_AD31
PCI_IRQA#
PCI_IRQB#
GND5
PEG_RX0+
PEG_RX0TY PE0#
PEG_RX1+
PEG_RX1TY PE1#
PEG_RX2+
PEG_RX2GND7
PEG_RX3+
PEG_RX3RSVD1
RSVD2
PEG_RX4+
PEG_RX4RSVD3
PEG_RX5+
PEG_RX5GND9
PEG_RX6+
PEG_RX6SDVO_DATA
PEG_RX7+
PEG_RX7GND8
RSVD4
PEG_RX8+
PEG_RX8GND10
PEG_RX9+
PEG_RX9RSVD5
GND6
PEG_RX10+
PEG_RX10GND35
PEG_RX11+
PEG_RX11GND27
PEG_RX12+
PEG_RX12GND11
PEG_RX13+
PEG_RX13GND12
RSVD6
PEG_RX14+
PEG_RX14GND13
PEG_RX15+
PEG_RX15GND
VCC_12V1
VCC_12V2
VCC_12V3
VCC_12V4
VCC_12V5
VCC_12V6
GND14
GND15
IDE_D5
IDE_D10
IDE_D11
IDE_D12
IDE_D4
IDE_D0
IDE_REQ
IDE_IOW#
IDE_ACK#
GND16
IDE_IRQ#
IDE_A0
IDE_A1
IDE_A2
IDE_CS1#
IDE_CS3#
IDE_RESET#
PCI_GNT3#
PCI_REQ3#
GND17
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_CBE0#
PCI_AD9
PCI_AD11
PCI_AD13
PCI_AD15
GND18
PCI_PAR
PCI_SERR#
PCI_STOP#
PCI_TRDY #
PCI_FRAME#
PCI_AD16
PCI_AD18
PCI_AD20
PCI_AD22
GND19
PCI_AD24
PCI_AD26
PCI_AD28
PCI_AD30
PCI_IRQC#
PCI_IRQD#
PCI_CLKRUN#
PCI_M66EN
PCI_CLK
GND20
PEG_TX0+
PEG_TX0PEG_LANE_RV#
PEG_TX1+
PEG-TX1TY PE2#
PEG_TX2+
PEG_TX2GND21
PEG_TX3+
PEG_TX3RSVD10
RSVD9
PEG_TX4+
PEG_TX4GND28
PEG_TX5+
PEG_TX5GND22
PEG_TX6+
PEG_TX6SDVO_CLK
PEG_TX7+
PEG_TX7GND29
IDE_CBLID#
PEG_TX8+
PEG_TX8GND23
PEG_TX9+
PEG_TX9RSVD8
GND30
PEG_TX10+
PEG_TX10GND31
PEG_TX11+
PEG_TX11GND24
PEG_TX12+
PEG_TX12GND32
PEG_TX13+
PEG_TX13GND33
PEG_ENABLE#
PEG_TX14+
PEG_TX14GND25
PEG_TX15+
PEG_TX15GND34
VCC_12V7
VCC_12V8
VCC_12V9
VCC_12V10
VCC_12V11
VCC_12V12
GND26
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49 1
D50
D51
D52
D53
D54 1
D55
D56
D57 1
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
IDE_D5
IDE_D10
IDE_D11
IDE_D12
IDE_D4
IDE_D0
IDE_RESET#
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
IDE_REQ
IDE_IOW#
IDE_ACK#
11
11
11
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_CS#1
IDE_CS#3
IDE_RESET#
PCI_GNT#3
PCI_REQ#3
11
11
11
11
11
11
11
7
7
V1.02 Modify
PCI_AD9
PCI_AD11
PCI_AD13
PCI_AD15
PCI_AD16
PCI_AD18
PCI_AD20
PCI_AD22
PCI_C/BE#0
7,8,9
PCI_PAR
PCI_SERR#
PCI_STOP#
PCI_TRDY #
PCI_FRAME#
7,8
7,8
7,8
7,8
7,8,9
PCI_AD24
PCI_AD26
PCI_AD28
PCI_AD30
PCI_INT#C
7
PCI_INT#D
7
PCI_CLKRUN# 11
TP17
PEG_TX0+
PEG_TX0TP25
TP29
PEG_TX1+
PEG_TX1PEG_TX2+
PEG_TX2PEG_TX3+
PEG_TX3PEG_TX4+
PEG_TX4PEG_TX5+
PEG_TX5PEG_TX6+
PEG_TX6-
CLK33M_PCI
4
PEG_TX0+
PEG_TX0-
6
6
PEG_TX1+
PEG_TX1-
6
6
PEG_TX2+
PEG_TX2-
6
6
PEG_TX3+
PEG_TX3-
6
6
PEG_TX4+
PEG_TX4-
6
6
PEG_TX5+
PEG_TX5-
6
6
PEG_TX6+
6
PEG_TX66
SDVO_I2C_CK 6
PEG_TX7+
6
PEG_TX76
PEG_TX7+
PEG_TX7PEG_TX8+
PEG_TX8PEG_TX9+
PEG_TX9PEG_TX10+
PEG_TX10PEG_TX11+
PEG_TX11PEG_TX12+
PEG_TX12PEG_TX13+
PEG_TX13PEG_ENABLE#
PEG_TX14+
PEG_TX14PEG_TX15+
PEG_TX15-
IDE_CBLID#
PEG_TX8+
PEG_TX8-
11
6
6
PEG_TX9+
PEG_TX9-
6
6
PEG_TX10+
PEG_TX10-
6
6
PEG_TX11+
PEG_TX11-
6
6
PEG_TX12+
PEG_TX12-
6
6
PEG_TX13+
PEG_TX13-
6
6
PEG_TX14+
PEG_TX14-
6
6
PEG_TX15+
PEG_TX15-
6
6
JP1(1-2)
JUMP_1X2_2.54mm
JP1
2
14.7K_41
2 R2
+V3.3
3
CON3_HDR
COM_EXPRESS_B2_REC
WAKE0#
WAKE1#
21
13
PWROK_ATX
PWROK_SIO
R3
R4
R5
R6
1
1
2 0_4
2 0_4
2
2
1 0_4
1 @0_4
PCIE_WAKE_UP# 5,6,10,16
WAKE_UP#
13
IEI ELECTRONICS INC.
PWR_OK
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
COM_EXPRESS CONNECTOR
Size
Document Number
Date:
Monday , September 15, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
3
of
23
PCIE Clock Buffer
+V3.3
+V3.3_CLK
FB1
FB30_8_3A
C1
10U_8_X_6V3
+V3.3_CLK_A
FB2
C2
10U_8_X_6V3
BEAD
C7
10U_8_X_6V3
C3
C4
C5
C6
0.1U_4_Y _16V 0.1U_4_Y_16V 0.1U_4_Y_16V 0.1U_4_Y _16V
C8
C9
0.1U_4_Y_16V0.1U_4_Y_16V
+V3.3_CLK_A
+V3.3_CLK
CLK100M_PCIEx1_SLOT1+
CLK100M_PCIEx1_SLOT1CLK100M_PCIEx1_SLOT2+
CLK100M_PCIEx1_SLOT2CLK100M_PCIEx1_SLOT3+
CLK100M_PCIEx1_SLOT3CLK100M_PCIEx1_SLOT4+
CLK100M_PCIEx1_SLOT4CLK100M_PCIEx1_SLOT5+
CLK100M_PCIEx1_SLOT5CLK100M_PCIEx1_SLOT6+
CLK100M_PCIEx1_SLOT6CLK100M_PCIEx16_SLOT+
CLK100M_PCIEx16_SLOT-
+V3.3_CLK
U1
CLK_DIV#
3 CLK100M_PCIE_REF+
3 CLK100M_PCIE_REF-
CLK_OE_0
CLK_OE_3
5 CLK100M_PCIEx1_SLOT1+
5 CLK100M_PCIEx1_SLOT15 CLK100M_PCIEx1_SLOT2+
5 CLK100M_PCIEx1_SLOT25 CLK100M_PCIEx1_SLOT3+
5 CLK100M_PCIEx1_SLOT35 CLK100M_PCIEx1_SLOT4+
5 CLK100M_PCIEx1_SLOT4-
R16
R18
2
2
1 33_4
1 33_4
R20
R21
2
2
1 33_4
1 33_4
R22
R23
2
2
1 33_4
1 33_4
R25
R27
2
2
1 33_4
1 33_4
CLK_OE_1
CLK_OE_2
CLK_PLL
3,5,6,10,11,17,20 SMB_CK
3,5,6,10,11,17,20 SMB_DAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SRC_DIV#
VDD01
GND01
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
GND02
VDD02
DIF_1
DIF_1#
OE_1
OE_2
DIF_2
DIF_2#
GND03
VDD03
DIF_3
DIF_3#
BY PASS#/PLL
SCLK
SDATA
VDDA
GNDA
IREF
LOCK
OE_7
OE_4
DIF_7
DIF_7#
OE_INV
VDD04
DIF_6
DIF_6#
OE_6
OE_5
DIF_5
DIF_5#
GND04
VDD05
DIF_4
DIF_4#
HIGH_BW#
SRC_SOP#
PD#
GND05
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK_IREF
CLK_LOCK
CLK_OE_7
CLK_OE_4
1
1
R10
475
TP32
TP33
R114
R115
CLK_OE_6
CLK_OE_5
R112
R113
2
2
1 33_4
1 33_4
2
2
1 33_4
1 33_4
33_4 1
33_4 1
CLK_HBW#
CLK_SRC_SOP#
CLK_PD#
2 R24
2 R26
@33_41
2 R34
R7
R8
R9
R11
R12
R13
R14
R15
R416
R415
R414
R413
R17
R19
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
49.9_4_1%
CLK100M_PCIEx1_SLOT6+ 10
CLK100M_PCIEx1_SLOT6- 10
CLK100M_PCIEx1_SLOT5+ 10
CLK100M_PCIEx1_SLOT5- 10
CLK100M_PCIEx16_SLOT+ 6
CLK100M_PCIEx16_SLOT- 6
ICS9DB801
+V3.3_CLK
10K_4 1
@10K_4 1
2 R28
2 R29
CLK_PLL
+V3.3_CLK
10K_4 1
@10K_4 1
2 R30
2 R31
CLK_OE_0
ON
+V3.3_CLK
10K_4 1
@10K_4 1
2 R32
2 R33
CLK_OE_1
ON
10K_4 1
@10K_4 1
2 R35
2 R36
CLK_OE_2
10K_4 1
@10K_4 1
2 R39
2 R42
CLK_OE_3
+V3.3_CLK
10K_4 1
@10K_4 1
2 R43
2 R46
CLK_OE_4
+V3.3_CLK
10K_4 1
@10K_4 1
2 R49
2 R50
CLK_OE_5
+V3.3_CLK
10K_4
1
@10K_41
2 R52
2 R53
CLK_OE_6
+V3.3_CLK
@10K_4 1
10K_4 1
2 R54
2 R55
CLK_OE_7
OFF
+V3.3_CLK
10K_4 1
@10K_4 1
2 R56
2 R57
CLK_HBW#
ON
+V3.3_CLK
10K_4 1
@10K_4 1
2 R58
2 R59
CLK_SRC_SOP#
+V3.3_CLK
10K_4 1
@10K_4 1
2 R60
2 R61
CLK_PD#
+V3.3_CLK
10K_4 1
@10K_4 1
2 R64
2 R66
CLK_LOCK
ON
+V3.3_CLK
10K_4 1
@10K_4 1
2 R68
2 R69
CLK_DIV#
ON
+V3.3_CLK
+V3.3_CLK
ON
ON
ON
PCI Clock Buffer
U2
V1.01 Modify
3 CLK33M_PCI
8 CLK33M_MINIPCI
7 CLK33M_SLOT3
9 CLK33M_80PORT
20 CLK33M_BIOS2
ON
11 CLK33M_TPM
R37
R40
2
2
1
2
3
4
5
6
7
8
1 33_4
1 33_4
+V3.3_CLKBUFFER
R44
R47
R51
2
2
1 33_4
1 33_4
CLKBUFFER_S2
2
1 33_4
REF
CLKOUT
CLKA1 CLKA4
CLKA2 CLKA3
VDD
VDD
GND
GND
CLKB1 CLKB4
CLKB2 CLKB3
S2
S1
16
15
14
13
12
11
10
9
33_4 1
33_4 1
2 R38
2 R41
+V3.3_CLKBUFFER
33_4 1
33_4 1
CLKBUFFER_S1
2 R45
2 R48
CLK33M_SLOT1 7
CLK33M_SLOT2 7
CLK33M_SIO2 14
CLK33M_MINICARD 5
CY 2309NZSXC-1H
ON
+V3.3
FB3
FB30_8_3A
CLK33M_SLOT1
C10
1
2 10P_4_N_50V
CLK33M_SLOT2
C11
1
2 10P_4_N_50V
CLK33M_SLOT3
C13
1
2 10P_4_N_50V
CLK33M_SIO2
C241 1
2 10P_4_N_50V
CLK33M_BIOS2
C265 1
2 10P_4_N_50V
CLK33M_TPM
C266 1
2 10P_4_N_50V
CLK33M_MINICARD C267 1
2 10P_4_N_50V
CLK33M_80PORT
C14
1
2 10P_4_N_50V
CLK33M_MINIPCI
C12
1
2 10P_4_N_50V
+V3.3_CLKBUFFER
ON
IEI ELECTRONICS INC.
ON
C15
10U_8_X_6V3
C16
10U_8_X_6V3
C17
C18
0.1U_4_Y_16V 0.1U_4_Y _16V
+V3.3_CLK
10K_4 1
@10K_4 1
2 R62
2 R63
CLKBUFFER_S1
+V3.3_CLK
10K_4 1
@10K_4 1
2 R65
2 R67
CLKBUFFER_S2
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
Title
Size
CLOCK BUFF
Document Number
Rev
1.02
F119 ICE-DB-9S-R10
Date:
Sunday , September 14, 2008
Sheet
4
of
23
Mini PCI Express
PCIEX1_Slot1
4 CLK33M_MINICARD
3,6,10,11,14,20 CB_RESET#
0_4 2
0_4 2
1 R122
1 R123
0_4 2
0_4 2
1 R70
1 R72
4 CLK100M_PCIEx1_SLOT4+
4 CLK100M_PCIEx1_SLOT4TP40
1
PCIE_WAKE_UP#
3,6,10,16 PCIE_WAKE_UP#
15
13
11
9
7
5
3
1
GND2
REFCLK+
REFCLKGND1
CLKREQ#
RESERVED_2
RESERVED_1
WAKE#
+V1.5
TP38
TP39
L1
4
1
SMB_DAT
SMB_CK
COMCHOKE_8_USB
3
USB7+
2
3,4,6,10,11,17,20
3
SMB_CK
3,4,6,10,11,17,20 SMB_DAT
3
USB7-
+V1.5
CB_RESET#
R71
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
PCIE_WAKE_UP#
+V3.3_DUAL
8.2K_4
+V1.5
+V3.3
MINICARD_DISABLE# 13
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
3
3
B12
B13
B14
B15
B16
B17
B18
PCIE_TX1+
PCIE_TX1-
3,11,13,14,20
3,11,13,14,20
3,11,13,14,20
3,11,13,14,20
3,11,13,14,20
PCIE1
+12V03
+12V04
RSVD01
GND05
SMBCLK
SMBDATA
GND06
3_3V03
JTAG1
3_3VAUX
WAKE#
PRSNT1#
+12V01
+12V02
GND01
JTAG2
JTAG3
JTAG4
JTAG5
3_3V01
3_3V02
PWRGD
RSVD02
GND07
HSOP0
HSON0
GND08
PRSNT2#
GND09
GND02
REFCLK+
REFCLKGND03
HSIP0
HSIN0
GND04
PCIE_X1
+V3.3
+V3.3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
CB_RESET# 3,6,10,11,14,20
A12
A13
A14
A15
A16
A17
A18
CLK100M_PCIEx1_SLOT2+ 4
CLK100M_PCIEx1_SLOT2- 4
0_4 2
0_4 2
+V12
1 R124
PCIE_RX1+
1 R125
PCIE_RX11
1
3
3
TP90
TP91
+V3.3
MINI PCIE CON_9MM_0.8
2
1
53
CN1(LATCH)1
1
1
16
14
12
10
8
6
4
2
UIM_VPP
UIM_RESET
UIM_CLK
UIM_DATA
UIM_PWR
1.5V_1
GND0
3.3V_1
+V12
NC2
PCIE_RX3+
PCIE_RX3-
3.3V_2
GND11
1.5V_3
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND10
USB_D+
USB_DGND8
SMB_DATA
SMB_CLK
1.5V_2
GND5
3.3VAUX1
PERST#
W_DISABLE#
GND3
+V12
NC1
3
3
PCIE_TX3+
PCIE_TX3-
RESERVED_10
RESERVED_9
RESERVED_8
RESERVED_7
RESERVED_6
RESERVED_5
RESERVED_4
RESERVED_3
GND9
PETp0
PETn0
GND7
GND6
PERp0
PERn0
GND4
UIM_C4
UIM_C8
+V3.3
+V3.3_DUAL
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
NC2
TP96
TP97
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
NC1
3
3
CN1
C21
0.1U_4_Y_16V
+V3.3
54
C20
10U_8_X_6V3
@150U_TNC_SMD_6.3V
1
1
+V1.5
G2
+V3.3
0.1U_4_Y _16V
C19
G1
+V3.3
EC11
C22
C23
10UF_1210_16V
C24
10U_8_X_6V3
0.1U_4_Y _16V
C25
0.1U_4_Y _16V
MINI PCIE LATCH_DIP
R350
+V3.3_ExpressCard
+V3.3_ExpressCard
+V3.3
2 R73
2 R74
PERST#
SY SRST#
SHDN#
STBY #
3.3VIN1
3.3VIN2
3.3VOUT1
3.3VOUT2
PERST#
NC
GND
OC#
RCLKEN
AUXIN
AUXOUT
1.5VIN2
1.5VIN1
1.5VOUT2
1.5VOUT1
CPPE#
CPUSB#
20
19
18
17
16
15
14
13
12
11
1
1
TP41
TP42
PCIEX1_Slot2
C27
0.1U_4_Y _16V
+V3.3
+V1.5_ExpressCard
+V1.5_ExpressCard
CPPE#
CPUSB#
C28
C29
10U_8_X_6V3 0.1UF
G
GND
3
3
R75
124 1%-RS
C30
10U_8_X_6V3
3
3
PCIE_RX2+
PCIE_RX2-
4 CLK100M_PCIEx1_SLOT3+
4 CLK100M_PCIEx1_SLOT3R76
24.9 1%-RS
+V3.3_ExpressCard
+V3.3_ExpressCard
+V1.5_ExpressCard
P26
P25
P24
P23
P22
P21
P20
PCIE_TX2+
PCIE_TX2-
+V3.3SB_ExpressCard
CPPE#
PERST#
PCIE_WAKE_UP#
+V1.5_ExpressCard
EC9
P15
P14
P13
P12
P11
P10
P9
P8
3,4,6,10,11,17,20 SMB_DAT
3,4,6,10,11,17,20 SMB_CK
C37
@150U_TNC_SMD_6.3V 0.1U_4_Y _16V
P19
P18
P17
P16
P7
P6
P5
+V3.3_ExpressCard
EC10
C35
0.1U_4_Y _16V
@150U_TNC_SMD_6.3V
+V3.3SB_ExpressCard
C36
10U_8_X_6V3
C38
0.1U_4_Y _16V
CPUSB#
L2
3
USB6+
3
USB6-
3
4
2
1
P4
P3
P2
P1
GND4
PETp0
PETn0
GND3
PERp0
PERn0
GND2
REFCLK+
REFCLKCPPE#
CLKREQ#
+3.3V2
+3.3V1
PERST#
+3.3VAUX
WAKE#
+1.5V
SMB_DATA
SMB_CLK
RESERVED3
RESERVED2
RESERVED1
+V12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
3,4,6,10,11,17,20 SMB_CK
3,4,6,10,11,17,20 SMB_DAT
E_Card_CON1
VCC1.5/1A
I
+V12
PCIE_WAKE_UP#
H1
H2
B12
B13
B14
B15
B16
B17
B18
H1
H2
3
3
PCIE_TX0+
PCIE_TX0-
PCIE2
+12V03
+12V04
RSVD01
GND05
SMBCLK
SMBDATA
GND06
3_3V03
JTAG1
3_3VAUX
WAKE#
PRSNT1#
+12V01
+12V02
GND01
JTAG2
JTAG3
JTAG4
JTAG5
3_3V01
3_3V02
PWRGD
RSVD02
GND07
HSOP0
HSON0
GND08
PRSNT2#
GND09
GND02
REFCLK+
REFCLKGND03
HSIP0
HSIN0
GND04
PCIE_X1
+V12
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
CB_RESET# 3,6,10,11,14,20
A12
A13
A14
A15
A16
A17
A18
CLK100M_PCIEx1_SLOT1+ 4
CLK100M_PCIEx1_SLOT1- 4
0_4 2
0_4 2
1 R126
1 R127
1
1
PCIE_RX0+
PCIE_RX0-
3
3
TP88
TP89
+V3.3
C31
10UF_1210_16V
C32
0.1U_4_Y _16V
C33
10U_8_X_6V3
CPUSB#
USB_D+
USB_DGND1
C34
0.1U_4_Y _16V
IEI ELECTRONICS INC.
COMCHOKE_8_USB
Express Card connector
+V3.3
+V3.3_DUAL
+V3.3SB_ExpressCard
TPS2231
+V1.5
Q1
GS1117-SOT223
<Output Current Capability >
O
V_IN
V_OUT 4
V_OUT1
C
LEDRED_8_2
NC2
10K_4 1
10K_4 1
470_6
NC1
3,6,10,11,14,20 CB_RESET#
+V3.3
+V3.3
1
2
3
4
5
6
7
8
9
10
A
+V3.3SB_ExpressCard
U3
1
TPS2231
C
LEDRED_8_2
LED7
NC2
+V3.3_DUAL
+V1.5
10U_8_X_6V3
470_6
R360
2
+V3.3
C26
LED6
A
+V3.3_ExpressCard
NC1
Express Card
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
PCIEX1/Express & Mini Card
Size
Document Number
Date:
Sunday , September 14, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
5
of
23
+V3.3 +V12
+V12
+V3.3_DUAL
3,5,10,16 PCIE_WAKE_UP#
B12
B13
B14
B15
B16
B17
B18
PEG_TX0+
PEG_TX0-
3 SDVO_I2C_CK
3
3
PEG_TX1+
PEG_TX1-
3
3
PEG_TX2+
PEG_TX2-
3
3
PEG_TX3+
PEG_TX3-
3
3
PEG_TX4+
PEG_TX4-
3
3
PEG_TX5+
PEG_TX5-
3
3
PEG_TX6+
PEG_TX6-
3
3
PEG_TX7+
PEG_TX7-
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
3 SDVO_I2C_DAT
TP43
3
3
PEG_TX8+
PEG_TX8-
3
3
PEG_TX9+
PEG_TX9-
3
3
PEG_TX10+
PEG_TX10-
3
3
PEG_TX11+
PEG_TX11-
3
3
PEG_TX12+
PEG_TX12-
3
3
PEG_TX13+
PEG_TX13-
3
3
PEG_TX14+
PEG_TX14-
3
3
PEG_TX15+
PEG_TX15-
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
PRSNT1#
+12V01
+12V02
GND01
JTAG2
JTAG3
JTAG4
JTAG5
3_3V01
3_3V02
PWRGD
RSVD06
GND37
HSOP0
HSON0
GND38
PRSNT2#01
GND39
GND02
REFCLK+
REFCLKGND03
HSIP0
HSIN0
GND04
HSOP1
HSON1
GND40
GND41
HSOP2
HSON2
GND42
GND43
HSOP3
HSON3
GND44
RSVD07
PRSNT2#02
GND45
RSVD01
GND05
HSIP1
HSIN1
GND06
GND07
HSIP2
HSIN2
GND08
GND09
HSIP3
HSIN3
GND10
RSVD02
HSOP4
HSON4
GND46
GND47
HSOP5
HSON5
GND48
GND49
HSOP6
HSON6
GND50
GND51
HSOP7
HSON7
GND52
PRSNT2#03
GND53
RSVD03
GND11
HSIP4
HSIN4
GND12
GND13
HSIP5
HSIN5
GND14
GND15
HSIP6
HSIN6
GND16
GND17
HSIP7
HSIN7
GND18
HSOP8
HSON8
GND54
GND55
HSOP9
HSON9
GND56
GND57
HSOP10
HSON10
GND58
GND59
HSOP11
HSON11
GND60
GND61
HSOP12
HSON12
GND62
GND63
HSOP13
HSON13
GND64
GND65
HSOP14
HSON14
GND66
GND67
HSOP15
HSON15
GND68
PRSNT2#04
RSVD08
NC1 NC2
NC1
PCIE_X16
RSVD04
GND19
HSIP8
HSIN8
GND20
GND21
HSIP9
HSIN9
GND22
GND23
HSIP10
HSIN10
GND24
GND25
HSIP11
HSIN11
GND26
GND27
HSIP12
HSIN12
GND28
GND29
HSIP13
HSIN13
GND30
GND31
HSIP14
HSIN14
GND32
GND33
HSIP15
HSIN15
GND34
NC2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
+V12
EC1
C39
100U_SMD6_3_EC_25V
0.1U_4_Y _16V
CB_RESET# 3,5,10,11,14,20
C40
C41
0.1U_4_Y _16V 0.1U_4_Y _16V
CLK100M_PCIEx16_SLOT+ 4
CLK100M_PCIEx16_SLOT- 4
0_4 2
0_4 2
1 R171
1 R223
PEG_RX0+
PEG_RX0-
3
3
+V3.3
0_4 2
0_4 2
1 R224
1 R225
0_4 2
0_4 2
1 R226
1 R227
0_4 2
0_4 2
1 R228
1 R376
PEG_RX1+
PEG_RX1-
3
3
PEG_RX2+
PEG_RX2-
3
3
PEG_RX3+
PEG_RX3-
3
3
1
TP61
1
1
TP62
TP63
1
1
TP68
TP71
EC2
C42
C43
0.1U_4_Y _16V
150U_TNC_SMD_6.3V
C44
0.1U_4_Y _16V 0.1U_4_Y _16V
+V3.3_DUAL
0_4 2
0_4 2
1 R377
1 R378
0_4 2
0_4 2
1 R379
1 R380
0_4 2
0_4 2
1 R381
1 R382
0_4 2
0_4 2
1 R383
1 R384
0_4 2
0_4 2
1 R385
1 R386
0_4 2
0_4 2
1 R387
1 R388
0_4 2
0_4 2
1 R389
1 R390
0_4 2
0_4 2
1 R391
1 R392
0_4 2
0_4 2
1 R393
1 R394
0_4 2
0_4 2
1 R395
1 R396
0_4 2
0_4 2
1 R397
1 R399
0_4 2
0_4 2
1 R400
1 R401
PEG_RX4+
PEG_RX4-
3
3
PEG_RX5+
PEG_RX5-
3
3
PEG_RX6+
PEG_RX6-
3
3
PEG_RX7+
PEG_RX7-
3
3
PEG_RX8+
PEG_RX8-
3
3
PEG_RX9+
PEG_RX9-
3
3
PEG_RX10+
PEG_RX10-
3
3
PEG_RX11+
PEG_RX11-
3
3
PEG_RX12+
PEG_RX12-
3
3
PEG_RX13+
PEG_RX13-
3
3
PEG_RX14+
PEG_RX14-
3
3
PEG_RX15+
PEG_RX15-
3
3
1
1
TP72
TP73
1
3,4,5,10,11,17,20 SMB_CK
3,4,5,10,11,17,20 SMB_DAT
+12V03
+12V04
RSVD05
GND35
SMBCLK
SMBDATA
GND36
3_3V03
JTAG1
3_3VAUX
WAKE#
2
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
3
3
+V3.3
PCIEX16_1
1
1
TP74
TP75
1
1
TP76
TP77
1
1
TP78
TP79
1
1
TP81
TP82
1
1
TP83
TP84
1
1
TP85
TP86
1
TP87
C45
C47
10U_8_X_6V3
0.1U_4_Y _16V
C46
0.1U_4_Y _16V
V1.01 Modify
IEI ELECTRONICS INC.
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
PCIEx16
Size
Document Number
Date:
Sunday , September 14, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
6
of
23
+V3.3_DUAL
PCI SLOT1:
AD20, REQ#1,GNT#1,INT#ABCD
3,8,9 PCI_AD[0..31]
+V3.3_DUAL
PCI SLOT2:
AD21, REQ#2,GNT#2,INT#BCDA
C48
0.1U_4_Y_16V
C49
+V3.3
0.1U_4_Y _16V
PCI SLOT3:
AD22, REQ#3,GNT#3,INT#CDAB
+V5
+V5
4 CLK33M_SLOT1
3
PCI_REQ#1
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
3,8,9 PCI_C/BE#3
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
3,8,9 PCI_C/BE#2
3,8,9 PCI_IRDY #
3,8 PCI_DEVSEL#
3
PCI_LOCK#
3,8 PCI_PERR#
3,8
PCI_SERR#
3,8,9 PCI_C/BE#1
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PCI_AD5
PCI_AD3
PCI_AD1
+V5
8.2K_4
X1
R85
AD8
AD7
+3.3V12
AD5
AD3
GND22
AD1
+5V10
ACK64#
+5V11
+5V12
C/BE0#
+3.3V06
AD6
AD4
GND10
AD2
AD0
+5V05
REQ64#
+5V
+5V06
R78
PCI_INT#A
PCI_INT#C
PCI_RST#
PCI_PME#
PCI_AD30
3,8
3
3
PCI_INT#C
3,8
PCI_INT#A
3,8,9,13
PCI_GNT#1
3
PCI_PME#
3,8
5.6K_4
C52
0.1U_4_Y _16V
C53
0.1U_4_Y _16V
4 CLK33M_SLOT2
3
PCI_REQ#2
PCI_AD31
PCI_AD29
PCI_AD28
PCI_AD26
PCI_AD27
PCI_AD25
PCI_AD24
PCI_AD20
2
100_4_1%
1
R79
PCI_AD22
PCI_AD20
3,8,9 PCI_C/BE#3
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD18
PCI_AD16
PCI_AD17
3,8,9 PCI_C/BE#2
PCI_FRAME# 3,8,9
PCI_TRDY #
PCI_STOP#
10K_4
10K_4
3,8,9 PCI_IRDY#
3,8
3,8 PCI_DEVSEL#
3,8
R81
R83
3
PCI_LOCK#
3,8 PCI_PERR#
+V3.3
3,8
PCI_PAR
PCI_AD15
3,8
PCI_SERR#
3,8,9 PCI_C/BE#1
PCI_AD13
PCI_AD11
PCI_AD12
PCI_AD10
PCI_AD9
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
PCI_AD14
PCI_C/BE#0
PCI_AD8
PCI_AD7
3,8,9
PCI_AD6
PCI_AD4
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PCI_AD5
PCI_AD3
PCI_AD2
PCI_AD0
+V5
PCI_AD1
+V5
R86
8.2K_4
R87
8.2K_4
+V3.3_DUAL
+V12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
PCI2
-12V
TCK
GND11
TDO
+5V07
+5V08
INTB#
INTD#
PRSNT1#01
RSVD03
PRSNT1#02
GND12
GND13
RSVD04
GND14
CLK
GND15
REQ#
+5V09
AD31
AD29
GND16
AD27
AD25
+3.3V07
C/BE3#
AD23
GND17
AD21
AD19
+3.3V08
AD17
C/BE2#
GND18
IRDY #
+3.3V09
DEVSEL#
GND19
LOCK#
PERR#
+3.3V10
SERR#
+3.3V11
C/BE1#
AD14
GND20
AD12
AD10
GND21
AD8
AD7
+3.3V12
AD5
AD3
GND22
AD1
+5V10
ACK64#
+5V11
+5V12
PCISLOT120_2.54
TRST#
+12V
TMS
TDI
+5V01
INTA#
INTC#
+5V02
RSVD
+5V03
RSVD02
GND01
GND02
3.3VAUX
RST#
+5V04
GNT#
GND03
PME#
AD30
+3.3V01
AD28
AD26
GND04
AD24
IDSEL
+3.3V02
AD22
AD20
GND05
AD18
AD16
+3.3V03
FRAME#
GND06
TRDY#
GND07
STOP#
+3.3V04
SMBCLK
SMDATA
GND08
PAR
AD15
+3.3V05
AD13
AD11
GND09
AD9
C/BE0#
+3.3V06
AD6
AD4
GND10
AD2
AD0
+5V05
REQ64#
+5V
+5V06
2
R121
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
PCI_INT#B
PCI_INT#D
3,8
3
C96
0.1U_4_Y_16V
C95
0.1U_4_Y_16V
4 CLK33M_SLOT3
3
PCI_RST#
PCI_PME#
PCI_AD30
PCI_REQ#3
PCI_AD31
PCI_AD29
3,8,9,13
PCI_GNT#2
3
PCI_PME#
3,8
PCI_AD27
PCI_AD25
3,8,9 PCI_C/BE#3
PCI_AD28
PCI_AD26
PCI_AD24
1
R80
PCI_AD22
PCI_AD20
PCI_AD21
2
100_4_1%
PCI_AD17
3,8,9 PCI_C/BE#2
3,8,9 PCI_IRDY #
PCI_AD18
PCI_AD16
3,8 PCI_DEVSEL#
PCI_FRAME# 3,8,9
PCI_TRDY#
PCI_STOP#
10K_4
10K_4
3,8
3,8
R82
R84
PCI_PAR
PCI_AD15
3
PCI_LOCK#
3,8 PCI_PERR#
3,8
+V3.3
PCI_SERR#
3,8,9 PCI_C/BE#1
PCI_AD13
PCI_AD11
PCI_AD8
PCI_AD7
PCI_AD9
PCI_AD5
PCI_AD3
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
PCI_C/BE#0
3,8,9
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
+V5
R88
PCI_AD1
+V5
R119
C57
0.1U_4_Y_16V
150U_TNC_SMD_6.3V
C58
C59
0.1U_4_Y_16V 0.1U_4_Y_16V
EC5
C60
0.1U_4_Y _16V
150U_TNC_SMD_6.3V
C61
AD8
AD7
+3.3V12
AD5
AD3
GND22
AD1
+5V10
ACK64#
+5V11
+5V12
C/BE0#
+3.3V06
AD6
AD4
GND10
AD2
AD0
+5V05
REQ64#
+5V
+5V06
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
+V3.3_DUAL
PCI_INT#C
PCI_INT#A
PCI_RST#
PCI_PME#
PCI_AD30
C415
0.1U_6_Y _25V
C420
0.1U_6_Y_25V
0.1U_4_Y _16V
150U_TNC_SMD_6.3V
C416
0.1U_6_Y _25V
0.1U_4_Y _16V 0.1U_4_Y_16V
3,8,9,13
PCI_GNT#3
3
PCI_PME#
3,8
PCI_AD28
PCI_AD26
PCI_AD24
1
R118
PCI_AD22
PCI_AD20
PCI_AD22
2
100_4_1%
PCI_AD18
PCI_AD16
PCI_FRAME# 3,8,9
10K_4
10K_4
PCI_AD15
PCI_TRDY #
3,8
PCI_STOP#
3,8
R116
R117
+V3.3
PCI_PAR
3,8
PCI_C/BE#0
3,8,9
PCI_AD13
PCI_AD11
PCI_AD9
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
+V5
R120
8.2K_4
PCISLOT120_2.54
C54
C55
C100
C99
C98
0.1U_4_Y _16V 0.1U_4_Y_16V
EC8
C281
0.1U_4_Y _16V
150U_TNC_SMD_6.3V
C101
C418
0.1U_6_Y _25V
C417
0.1U_6_Y _25V
C419
0.1U_6_Y _25V
0.1U_4_Y _16V
150U_TNC_SMD_6.3V
C102
0.1U_4_Y_16V 0.1U_4_Y _16V
-V12
IEI ELECTRONICS INC.
C56
C62
0.1U_4_Y _16V 0.1U_4_Y _16V -V12
3
3,8
+V3.3
0.1U_4_Y_16V
150U_TNC_SMD_6.3V
0.1U_6_Y_25V
EC3
TRST#
+12V
TMS
TDI
+5V01
INTA#
INTC#
+5V02
RSVD
+5V03
RSVD02
GND01
GND02
3.3VAUX
RST#
+5V04
GNT#
GND03
PME#
AD30
+3.3V01
AD28
AD26
GND04
AD24
IDSEL
+3.3V02
AD22
AD20
GND05
AD18
AD16
+3.3V03
FRAME#
GND06
TRDY #
GND07
STOP#
+3.3V04
SMBCLK
SMDATA
GND08
PAR
AD15
+3.3V05
AD13
AD11
GND09
AD9
+V12
C421
C65
-12V
TCK
GND11
TDO
+5V07
+5V08
INTB#
INTD#
PRSNT1#01
RSVD03
PRSNT1#02
GND12
GND13
RSVD04
GND14
CLK
GND15
REQ#
+5V09
AD31
AD29
GND16
AD27
AD25
+3.3V07
C/BE3#
AD23
GND17
AD21
AD19
+3.3V08
AD17
C/BE2#
GND18
IRDY#
+3.3V09
DEVSEL#
GND19
LOCK#
PERR#
+3.3V10
SERR#
+3.3V11
C/BE1#
AD14
GND20
AD12
AD10
GND21
PCISLOT120_2.54
+V3.3
C64
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PCI3
+V5
0.1U_6_Y _25V
C63
8.2K_4
+V12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
8.2K_4
C414
EC6
EC4
PCI_AD14
PCI_AD12
PCI_AD10
3,8
+V12
+V5
PCI_AD23
PCI_AD21
PCI_AD19
+V12
+V3.3
5.6K_4
3
PCI_INT#D
3,8
PCI_INT#B
EC7
+V5
1
X1
0.1U_4_Y_16V
1
X2
C50
2
X1
0.1U_4_Y_16V
-V12
+V3.3_DUAL
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
X1
C51
TRST#
+12V
TMS
TDI
+5V01
INTA#
INTC#
+5V02
RSVD
+5V03
RSVD02
GND01
GND02
3.3VAUX
RST#
+5V04
GNT#
GND03
PME#
AD30
+3.3V01
AD28
AD26
GND04
AD24
IDSEL
+3.3V02
AD22
AD20
GND05
AD18
AD16
+3.3V03
FRAME#
GND06
TRDY #
GND07
STOP#
+3.3V04
SMBCLK
SMDATA
GND08
PAR
AD15
+3.3V05
AD13
AD11
GND09
AD9
X2
3,8 PCI_INT#B
3
PCI_INT#D
-12V
TCK
GND11
TDO
+5V07
+5V08
INTB#
INTD#
PRSNT1#01
RSVD03
PRSNT1#02
GND12
GND13
RSVD04
GND14
CLK
GND15
REQ#
+5V09
AD31
AD29
GND16
AD27
AD25
+3.3V07
C/BE3#
AD23
GND17
AD21
AD19
+3.3V08
AD17
C/BE2#
GND18
IRDY#
+3.3V09
DEVSEL#
GND19
LOCK#
PERR#
+3.3V10
SERR#
+3.3V11
C/BE1#
AD14
GND20
AD12
AD10
GND21
X1
5.6K_4
PCI1
X2
R77
+V12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
1
X2
-V12
2
+V3.3
X2
+V5
+V3.3
X1
+V5
+V3.3
-V12
+V3.3
+V5
C97
0.1U_4_Y _16V
+V5
X2
+V3.3
+V3.3_DUAL
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
0.1U_4_Y _16V 0.1U_4_Y _16V
-V12
C422
0.1U_6_Y_25V
Title
PCI SLOT1/2/3
Size
Document Number
Date:
Sunday , September 14, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
7
of
23
MiniPCI:
AD23, REQ#0,GNT#0,INT#AB
PCI_AD[0..31] 3,7,9
+V3.3
PCI_C/BE#[0..3] 3,7,9
+V5
+V3.3_DUAL
CN2
3,7,9 PCI_FRAME#
3,7
PCI_TRDY #
3,7
PCI_STOP#
3,7 PCI_DEVSEL#
PCI_AD18
PCI_AD16
PCI_FRAME#
PCI_TRDY #
PCI_STOP#
PCI_DEVSEL#
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_C/BE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
R92
10K
R0402
.
miniPCI
C71
1
C70
0.1U_4_X_10V 0.1U_4_X_10V
2
0.1U_4_X_10V
1
1
C69
2
0.1U_4_X_10V
2
1
1
C68
2
2
2
1
2
1
0.1U_4_X_10V
C72
0.1U_4_X_10V
PCI_INT#B 3,7
CLK33M_MINIPCI 4
+V5
0.1U_4_X_10V
C74
1
C73
0.1U_4_X_10V
C77
2
PCI_AD27
PCI_AD25
1
PCI_AD31
PCI_AD29
1
PCI_REQ#0 3
2
PCI_REQ#0
2
PCI_PAR
C67
1
3,7
PCI_AD22
PCI_AD20
PCI_INT#B
C66
10U_8_X_6V3
C75
0.1U_4_X_10V
PCI_C/BE#3
PCI_AD23
+V3.3_DUAL
PCI_AD21
PCI_AD19
PCI_AD17
PCI_C/BE#2
PCI_IRDY #
R90
10K R0402
PCI_SERR#
PCI_PERR#
PCI_C/BE#1
PCI_AD14
C76
0.1U_4_X_10V
PCI_IRDY # 3,7,9
2
100
R0402
+V3.3
1
R89
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
2
PCI_AD23
PCI_AD28
PCI_AD26
PCI_AD24
MINI_IDSEL
128
PCI_AD30
127
PCI_PME#
128
PCI_GNT#0
126
3,7
PCI_GNT#0
TIP
8PMJ-3
8PMJ-6
8PMJ-7
8PMJ-8
LED1-GRNP
LED1-GRNN
CHSGND
INTB#
3.3V5
RESERVED5
GROUND8
CLK
GROUND9
REQ#
3.3V6
AD[31]
AD[29]
GROUND10
AD[27]
AD[25]
RESERVED6
C/BE[3]#
AD[23]
GROUND11
AD[21]
AD[19]
GROUND12
AD[17]
C/BE[2]#
IRDY #
3.3V7
CLKRUN#
SERR#
GROUND13
PERR#
C/BE[1]#
AD[14]
GROUND14
AD[12]
AD[10]
GROUND15
AD[08]
AD[07]
3.3V8
AD[05]
RESERVED7
AD[03]
5V2
AD[01]
GROUND16
AC_SY NC
AC_SDATD_IN
AC_BIT_CLK
AC_CODEC_ID1#
MOD_AUDIO_OUT
AUDIO_GND2
SY S_AUDIO_OUT
SY S_AUDIO_OUT GND
AUDIO_GND3
RESERVED8
VCC5VA
127
3
125
3,7,9,13 PCI_RST#
126
PCI_INT#A
RING
8PMJ-1
8PMJ-2
8PMJ-4
8PMJ-5
LED2_Y ELP
LED2_Y ELN
RESERVED1
5V1
INTA#
RESERVED2
3.3VAUX1
RST#
3.3V1
GNT#
GROUND1
PME#
RESERVED3
AD[30]
3.3V2
AD[28]
AD[26]
AD[24]
IDSEL
GROUND2
AD[22]
AD[20]
PAR
AD[18]
AD[16]
GROUND3
FRAME#
TRDY #
STOP#
3.3V3
DEVSEL#
GROUND4
AD[15]
AD[13]
AD[11]
GROUND5
AD[09]
C/BE[0]#
3.3V4
AD[06]
AD[04]
AD[02]
AD[00]
RESERVED_WIP1
RESERVED_WIP2
GROUND6
M66EN
AC_SDATA_OUT
AC_CODEC_ID0#
AC_RESET#
RESERVED4
GROUND7
SY S_AUDIO_IN
SY S_AUDIO_IN GND
AUDIO_GND1
MPCIACT#
3.3VAUX2
125
3,7
PCI_INT#A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
0.1U_4_X_10V
PCI_SERR# 3,7
PCI_PERR# 3,7
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
R91
0
R0402
C78
0.1uF
C0402
.
IEI ELECTRONICS INC.
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
Title
MINI-PCI
Size
Document Number
Date:
Sunday , September 14, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
8
of
23
4 CLK33M_80PORT
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
3,7,8 PCI_AD[31..0]
3,7,8 PCI_C/BE#[0..3]
R93
1
2 0_4
7-Segment LED with Common GND
PCI_RST#
3,7,8,13
PCI_FRAME# 3,7,8
PCI_IRDY # 3,7,8
TP44
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
80PORT_H_LED_A R94
80PORT_H_LED_B R95
80PORT_H_LED_C R96
80PORT_H_LED_D R97
80PORT_H_LED_E R98
80PORT_H_LED_F R99
80PORT_H_LED_G R100
80PORT_H_LED_DGR101
R102
+V3.3
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
+V3.3
TP53
TP54
TP55
TP56
TP57
TP58
TP59
TP60
80PORT_TCK
LC4064V-75TN100C-10I
VCC
TDO
I
D8
D9
D10
D11
GND(BANK1)
D12
D13
D14
D15
VCCO(BANK1)
I
C15
C14
C13
C12
GND(BANK1)
C11
C10
C9
C8
TMS
GND
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80PORT_TDO
ATMEGA88_80PORT_E
ATMEGA88_80PORT_F
ATMEGA88_80PORT_G
ATMEGA88_80PORT_H
+V3.3
TP45
TP46
TP47
TP48
TP49
TP50
TP51
TP52
80PORT_L_LED_A R103
80PORT_L_LED_B R104
80PORT_L_LED_C R105
80PORT_L_LED_D R106
80PORT_L_LED_E R107
80PORT_L_LED_F R108
80PORT_L_LED_G R109
80PORT_L_LED_DG R110
R111
+V3.3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
U5
470_4_5% 10
9
470_4_5%
8
470_4_5%
5
470_4_5%
470_4_5%
4
470_4_5%
2
3
470_4_5%
7
470_4_5%
@470_4_5%
HA
HB
HC
HD
HE
HF
HG
DP
U6
470_4_5% 10
470_4_5%
9
8
470_4_5%
5
470_4_5%
4
470_4_5%
2
470_4_5%
3
470_4_5%
7
470_4_5%
@470_4_5%
HA
HB
HC
HD
HE
HF
HG
DP
7-LED_TOP
1
COMMON1
COMMON2
6
7-LED_TOP
1
COMMON1
COMMON2
6
80PORT_L_LED_DG
80PORT_L_LED_G
80PORT_L_LED_F
80PORT_L_LED_E
80PORT_L_LED_D
80PORT_L_LED_C
80PORT_L_LED_B
80PORT_L_LED_A
80PORT_TMS
Debug 80 Programimg Port(Reserve)
80PORT_H_LED_DG
80PORT_H_LED_G
80PORT_H_LED_F
80PORT_H_LED_E
80PORT_H_LED_D
80PORT_H_LED_C
80PORT_H_LED_B
80PORT_H_LED_A
+V3.3
+V3.3
ATMEGA88_80PORT_A
ATMEGA88_80PORT_B
ATMEGA88_80PORT_C
ATMEGA88_80PORT_D
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
+V3.3
GND
TDI
A8
A9
A10
A11
GND(BANK0)
A12
A13
A14
A15
I
VCCO(BANK0)
B15
B14
B13
B12
GND(BANK0)
B11
B10
B9
B8
I
TCK
VCC
GND
I
B7
B6
B5
B4
GND(BANK0)
VCCO(BANK0)
B3
B2
B1
B0
CLK1/I
CLK2/I
VCC
C0
C1
C2
C3
VCC0(BACK1)
GND(BANK1)
C4
C5
C6
C7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
80PORT_TDI
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
A7
A6
A5
A4
GND(BANK0)
VCCO(BANK0)
A3
A2
A1
A0/GOE0
VCC
CLK0/I
CLK3/I
D0/GOE1
D1
D2
D3
VCCO(BANK1)
GND(BANK1)
D4
D5
D6
D7
I
GND
U4
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
+V3.3
CN3
+V3.3
1
80PORT_TDO 2
80PORT_TDI 3
4
5
80PORT_TMS 6
7
80PORT_TCK 8
@80PORT_JTAG
1
C83
0.1U_4_Y _16V
C84
0.1U_4_Y _16V
2
1
C82
0.1U_4_Y _16V
2
1
C81
0.1U_4_Y _16V
2
1
C80
0.1U_4_Y _16V
2
1
C79
0.1U_4_Y _16V
2
2
1
+V3.3
IEI ELECTRONICS INC.
Title
Size
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
PCI 80 PORT
Document Number
Rev
1.02
F119 ICE-DB-9S-R10
Date:
Sunday , September 14, 2008
Sheet
9
of
23
PCIEX1_Slot3
+V12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
3,4,5,6,11,17,20 SMB_CK
3,4,5,6,11,17,20 SMB_DAT
PCIE_WAKE_UP#
3
3
B12
B13
B14
B15
B16
B17
B18
PCIE_TX4+
PCIE_TX4-
PCIE3
+12V03
+12V04
RSVD01
GND05
SMBCLK
SMBDATA
GND06
3_3V03
JTAG1
3_3VAUX
WAKE#
PRSNT1#
+12V01
+12V02
GND01
JTAG2
JTAG3
JTAG4
JTAG5
3_3V01
3_3V02
PWRGD
RSVD02
GND02
GND07
REFCLK+
HSOP0
REFCLKHSON0
GND03
GND08
HSIP0
PRSNT2#
HSIN0
GND09 NC1 NC2
GND04
NC1 NC2
PCIE_X1
+V3.3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
+V12
CB_RESET# 3,5,6,11,14,20
A12
A13
A14
A15
A16
A17
A18
CLK100M_PCIEx1_SLOT5+ 4
CLK100M_PCIEx1_SLOT5- 4
0_4 2
0_4 2
1R403
1R404
1
1
PCIE_RX4+
PCIE_RX4-
1
+V12
2
+V3.3
+V3.3_DUAL
+V3.3
C86
C87
10UF_1210_16V
0.1U_4_Y _16V
TP92
TP93
PCIEX1_Slot4
+V12
+V12
PCIE_WAKE_UP#
3
3
PCIE_TX5+
PCIE_TX5-
B12
B13
B14
B15
B16
B17
B18
PCIE4
+12V03
+12V04
RSVD01
GND05
SMBCLK
SMBDATA
GND06
3_3V03
JTAG1
3_3VAUX
WAKE#
PRSNT1#
+12V01
+12V02
GND01
JTAG2
JTAG3
JTAG4
JTAG5
3_3V01
3_3V02
PWRGD
RSVD02
GND02
GND07
REFCLK+
HSOP0
REFCLKHSON0
GND03
GND08
HSIP0
PRSNT2#
HSIN0
GND09 NC1 NC2
GND04
NC1 NC2
PCIE_X1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
+V12
1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C94
0.1U_4_Y_16V
+V3.3
2
3,4,5,6,11,17,20 SMB_CK
3,4,5,6,11,17,20 SMB_DAT
3,5,6,16 PCIE_WAKE_UP#
+V3.3_DUAL
C93
0.1U_4_Y _16V
+V3.3
C85
0.1U_4_Y _16V
3
3
+V3.3_DUAL
+V3.3_DUAL
C88
10U_8_X_6V3
+V3.3
C90
10UF_1210_16V
C91
0.1U_4_Y _16V
C92
10U_8_X_6V3
C89
0.1U_4_Y _16V
CB_RESET# 3,5,6,11,14,20
CLK100M_PCIEx1_SLOT6+ 4
CLK100M_PCIEx1_SLOT6- 4
0_4 2
0_4 2
1R405
1R406
1
1
PCIE_RX5+
PCIE_RX5-
3
3
TP94
TP95
IEI ELECTRONICS INC.
Title
Size
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
PCI ExpressX1 Slot3/4
Document Number
Rev
1.02
F119 ICE-DB-9S-R10
Date:
Sunday , September 14, 2008
Sheet
10
of
23
2
+V3.3
R130
4.7K_4
1
R129
8.2K_4
3
3
3
3
3
3
3
3
3
20,21
IDE_REQ
IDE_IOW#
IDE_IOR#
IDE_IORDY
IDE_ACK#
IDE_IRQ
IDE_A1
IDE_A0
IDE_CS#1
HDD_LED#
R134
R137
1
1
IDE_SDA1
IDE_SDA0
2 33_4
2 33_4
20
22
24
26
28
30
32
34
36
38
40
R132
IDE_D3
IDE_D4
IDE_D5
IDE_D6
IDE_D7
IDE_CS#1
C383
1
470_4
R135 1
IDE_SDA2
R138 1
2 0_4
2 33_4
IDE_CBLID#
IDE_A2
IDE_CS#3
10U_8_X_6V3
2 +VCC_CF
3
3
3
IDE_SDA2
IDE_SDA1
IDE_SDA0
IDE_D0
IDE_D1
IDE_D2
BOXHEADER_2X20_2.54
1
R140
10K_4
R142
100_4_1%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CF1 5152
5152
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND1
CD1
D3
D11
D4
D12
D5
D13
D6
D14
D7
D15
CE
CE2
A10
VS1
OE
IOR
A9
IOW
A8
WE
A7
IRQ
VCC1
VCC2
A6
CSEL
A5
VS2
A4
RESET
A3
WAIT
A2
INPACK
A1
REG
A0
BVD2
D0
BVD1
D1
D8
D2
D9
IOCS16
D10
CD2545556
GND2
545556
CFIIB-SMD
R131
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
100_4_1%
2
C104
0.1U_4_X_10V 0.1U_4_X_10V
C105
10U_8_X_6V3
JCF1
1-2
R133
+VCC_CF
IDE_CS#3
3
IDE_IOR#
IDE_IOW#
10K_4
3
3
IDE_IRQ
3
R136
10K_4
2-3
+V5
1
+V3.3
3
HEADER_1X3_2
R141
1K_4
JP4
2
JP4
1-2
+5V (Default)
2-3
+3.3V
+VCC_CF
JP4(1-2)
JUMP_1X2_2
HEADER_1X3_2
TPM Connector
SATA Connector
S_ATA1
SATA_1X7_1
+V5
2 33_4
+V3.3
+V3.3_DUAL
R144
+V3.3
4.7K_4
C106
0.1U_4_X_10V
1
+V3.3
2
2
1
+V5
C107
0.1U_4_X_10V
LCLK
GND2
LFRAME# KEY
LRESET#
+5V
LAD3
LAD2
+3V
LAD1
LAD0
GND3
SCL
SDA
SB3V SERIRQ
GND1GLKRUN#
LPCPD# LDRQ#
@TPM_connector
+V3.3_DUAL
1
3,5,13,14,20 LPC_AD0
3,4,5,6,10,17,20 SMB_CK
R1431
1
3
5
7
9
11
13
15
17
19
2
4 CLK33M_TPM
3,5,13,14,20 LPC_FRAME#
3,5,6,10,14,20 CB_RESET#
3,5,13,14,20 LPC_AD3
CN4
C108
2
4
6
8
10
12
14
16
18
20
Master
JCF1(1-2)
JUMP_1X2_2
JCF1
IDE_IORDY 3
IDE_REQ
3
IDE_ACK#
3
HDD_LED# 20,21
+V5
Slave
1
2
3
+V5
233_4 IDE_RESET#
R1391
IDE_CBLID#
IDE_D8
IDE_D9
IDE_D10
C103
1
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
2
2
4
6
8
10
12
14
16
18
53
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
53
IDE_D7
IDE_D6
IDE_D5
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0
IDE_D[15..0] 3
2
3 IDE_RESET#
33_4
2
1
CF Connector
IDE1
R128
1
2
IDE Connector
1
+V5
LPC_AD2 3,5,13,14,20
LPC_AD1 3,5,13,14,20
SMB_DAT 3,4,5,6,10,17,20
SERIRQ 3,13,14
PCI_CLKRUN# 3
LPC_DRQ#0 3,13
8 GND1
8 A+
A9
GND2
9
BB+
GND3
S_ATA3
SATA_1X7_1
8 GND1
8 A+
A9
GND2
9
BB+
GND3
1
2
3
4
5
6
7
S_ATA2
SATA_1X7_1
SATA0_TX+
SATA0_TXSATA0_RXSATA0_RX+
SATA0_TX+ 3
SATA0_TX- 3
SATA0_RX- 3
SATA0_RX+ 3
8 GND1
8 A+
A9
GND2
9
BB+
GND3
S_ATA4
SATA_1X7_1
1
2
3
4
5
6
7
SATA1_TX+
SATA1_TXSATA1_RXSATA1_RX+
SATA1_TX+ 3
SATA1_TX- 3
SATA1_RX- 3
SATA1_RX+ 3
8 GND1
8 A+
A9
GND2
9
BB+
GND3
1
2
3
4
5
6
7
1
2
3
4
5
6
7
SATA2_TX+
SATA2_TXSATA2_RXSATA2_RX+
SATA3_TX+
SATA3_TXSATA3_RXSATA3_RX+
SATA2_TX+ 3
SATA2_TX- 3
SATA2_RX- 3
SATA2_RX+ 3
SATA3_TX+ 3
SATA3_TX- 3
SATA3_RX- 3
SATA3_RX+ 3
0.1U_4_X_10V
IEI ELECTRONICS INC.
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
Title
Size
IDE,SATA,TPM CF CONN
Document Number
Rev
1.02
F119 ICE-DB-9S-R10
Date:
Monday , September 15, 2008
Sheet
11
of
23
+V3.3_LCD_PANEL
+V5
R361
C110
10U_8_X_6V3
C111
10U_8_X_6V3
C112
C113
0.1U_4_Y _16V
0.1U_4_Y _16V
470_4
+V12_LCD_BKL
C
LED-RED(0603)
C114
+V3.3_LCD_PANEL
1
R149
1K_4
Q5
2N3904_SOT23
B
Q4
2N3904_SOT23
IO_GND
D3
L8
FB47_6_300MA
CRT_DDCDATA
R160
1
2 33_4
13
CRT_HSY NC
R162
1
2 33_4
14
CRT_VSY NC
R164
1
2 33_4
15
CRT_DDCCLK
R165
1
2 33_4
IO_GND
C123
10P_4_N_50V
C124
22P_4_N_50V
VGA_I2C_DAT_Z
+V3.3
2
G
VGA_VSY NC
VGA_I2C_CK_Z
VGA_I2C_DAT 3
3
R166 1
2 0_4
VGA_I2C_CK 3
D5
BAV99LT1G_SOT23
CRT_HSY NC
C127
@22P_4_N_50V
2 0_4
+V3.3
D4
BAV99LT1G_SOT23
C125
10P_4_N_50V
R161 1
VGA_HSY NC 3
IO_GND
C
R167
150_4_1%
FB47_6_300MA
L7
CRT_B_Y
17
12
C
BAV99LT1G_SOT23
VGA_BLU
VGA_I2C_DAT
IO_GND
11
VGA SOCKET
<1ST PART FIELD>
A
K
+V3.3
IO_GND
R157
@2.7K_4
S
A
C122
10P_4_N_50V
16
K
C121
22P_4_N_50V
D
@2N7002_SOT23
A
CRT_G
K
C120
10P_4_N_50V
Q7
VGA_I2C_DAT_Z
A
C
6
1
7
2
8
3
9
4
10
5
CRT_R
CRT_B
R163
150_4_1%
R159
@2.2K_4
VGA_I2C_CK
CON7
BAV99LT1G_SOT23
FB47_6_300MA
R158
@2.7K_4
S
@2N7002_SOT23
D2
FB47_6_300MA
L6
CRT_G_Y
2
2
D
G
@2.2K_4
Q6
IO_GND
K
IO_GND
L5
+V5
@4.7K_4
+V3.3
1
VGA_I2C_CK_Z
1
C119
10P_4_N_50V
+V3.3
VGA_GRN
+V3.3
+V5
C
C118
22P_4_N_50V
@4.7K_4
R154
C
R156
C117
10P_4_N_50V
1
R155
150_4_1%
LVDS_BRIGHTNESS
R153
+V3.3
2
VGA_RED
FB47_6_300MA
WAFER_1X5_2
10U_1210_Y _25V
+V3.3
+V5
BAV99LT1G_SOT23
FB47_6_300MA
L4
CRT_R_Y
C116
INVERTER1
LCD_Adj
GND1
12V
GND2
BL_EN
IO_GND
D1
L3
LVDS_BRIGHTNESS 1
2
3
4
LVDS_ENABKL
5
C
1K_4 B
R152
100K_4
A
K
+V3.3
3
3 LVDS_BKLT_CRTL
39_4_1%
2
R150
2
CRT
3
+V12_LCD_BKL
R147
47K_4
Q2B
FDS6975_SOP8
3 LVDS_BKLT_EN
+V5
R146
1K_4
R148
4
FB4
FB11_12_600MA
LVDS_A3- 3
LVDS_A_CK- 3
LVDS_A2- 3
LVDS_A1- 3
LVDS_A0- 3
PIN HEADER/15X2 2.0MM/SMD
100K_4
3
+V12
C
LED-RED(0603)
2
C272
10U_1210_Y _25V
3
3
3
3
3
E
1
C271
0.1U_4_Y _16V
+V12_LCD_BKL
LVDS_B3LVDS_B_CKLVDS_B2LVDS_B1LVDS_B0-
E
R151
3
LVDS_A3+
3 LVDS_A_CK+
3
LVDS_A2+
3
LVDS_A1+
3
LVDS_A0+
3334 30
29
30 28
27
28 26
25
26 24
23
24 22
21
22 20
19
20 18
17
18 16
15
16 14
13
14 12
11
12 10
9
10 8
7
8 6
5
6 4
3
4 2
1 3132 2
3132
C
LVDS_B3+
LVDS_B_CK+
LVDS_B2+
LVDS_B1+
LVDS_B0+
33
34
CN5
1
3
3
3
3
3
7
8
C270
0.1U_4_Y _16V
S
1
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
+V3.3_LCD_PANEL
3 +V5
Q3
2N7002_SOT23
G
3 LVDS_VDD_EN
1 +V3.3
HEADER_1X3_2
Q2A
FDS6975_SOP8 D
D
2
1M_4
C273
2.2U_6_Y _10V
1
2
G S
3
2
2
C269
1000P_4_X_50V
1
2
R417
100K_4
6
5
R145
1
5V
1
3.3V(Default)
2-3
1K_4
2
+V12
1-2
LED9
A
+V12_LCD_BKL
0.1U_4_Y _16V
J_VLVDS1
2
J_VLVDS1
R363
C115
10U_1210_16V
2
C109
10U_8_X_6V3
1
J_VLVDS1(1-2)
MINIJUMPER_1X2_2
LED8
A
+V3.3_LCD_PANEL
1
+V3.3
1
LVDS
CRT_VSY NC
C126
@22P_4_N_50V
IO_GND
TV-OUT
A
K
+V3.3
D6
1
C128
3.3P_4_N_50V
2
R168
150_4_1%
A
K
+V3.3
FB150_6_200MA
TV_ABLUE_CVBS
1
L9
TV_DAC_A
TV1
C129
3.3P_4_N_50V
2
C
BAV99LT1G_SOT23
3
C
BAV99LT1G_SOT23
L10
TV_DAC_B
FB150_6_200MA
TV_AGREEN_Y
GND
Y
GND
C
GND
CVBS
A
K
R169
150_4_1%
C130
3.3P_4_N_50V
1
C131
3.3P_4_N_50V
2
1
HEADER_2X3_2.54
+V3.3
2
3
1
2
3
TV_ARED_C
4
5
TV_ABLUE_CVBS6
TV_AGREEN_Y
D7
D8
1
C132
3.3P_4_N_50V
2
R170
150_4_1%
FB150_6_200MA
TV_ARED_C
IEI ELECTRONICS INC.
1
L11
TV_DAC_C
C133
3.3P_4_N_50V
2
C
BAV99LT1G_SOT23
3
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
LVDS/TV/CRT
Size
Document Number
Date:
Monday , September 15, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
12
of
23
+V5
IR1
IR_5X1_2.54
1
2
3
4
5
UART_RX2
UART_TX2
D-
C427 0.1U_4_Y _16V
R176
R177
4.7K_4
1K_4_1%
SIO_DOUT3
SIO_DOUT2
SIO_DOUT1
SIO_DOUT0
FB31
SIO_DIN3
FB80_6_600MA
SIO_DIN2
SIO_DIN1
SIO_DIN0
AUXTIN
VREF
CPUVCORE
VIN0
VIN1
VIN2
VIN3
VIN4
RSTOUT0
RSTOUT1
GP30
GP31
SCL/GP32/RSTOUT2
SDA/GP33/RSTOUT3
GP34/RSTOUT4
GP35
PME
RIB/GP40
DCDB/GP41
SOUTB/IRTX
SINB/IRRX
DTRB/GP44
RTSB/GP45
DSRB/GP46
CTSB/GP47
GP50/WDTO/EN_VRM10
CASEOPEN
RSMRST/GP51
VBAT
SUSB/GP52
PSON/GP53
PWROK/GP54
GP55/SUSLED
GP36
PSIN/GP56
PSOUT/GP57
MDAT/GP24
MCLK
W83627EHG
WDTO : 6F02
DIO in : 6F08
DIO out : 6F09
GP37
KDAT/GP26
KCLK/GP27
3VSB
KBRST
GA20M
SO/AUXFANIN1
RIA/GP60
DCDA/GP61
VSS_2
SOUTA/GP62/PENKBC
SINA/GP63
DTRA/GP64/PENROM
RTSA/GP65/HEFRAS
DSRA/GP66
CTSA/GP67
VCC3_3
STB
AFD
ERR
INIT
SLIN
PD0
PD1
PD2
PD3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
15
15
15
15
15
15
R181
R183
R185
R187
R189
1K_4_1%
@1K_4_1%
1K_4_1%
@1K_4_1%
@1K_4_1%
DTR-A
* DISABLE SPI
SOUTA
KBC DISABLE
SIO_DOUT0
SIO_DOUT1
SIO_DOUT2
SIO_DOUT3
SIO_DOUT3
SIO_DOUT2
SIO_DOUT1
SIO_DOUT0
7
5
3
1
SIO_DIN3
SIO_DIN2
SIO_DIN1
SIO_DIN0
2.7K_8P4R04
RN21
7
8
5
6
3
4
1
2
8
6
4
2
LPT_STB#
LPT_AFD#
LPT_ERR#
LPT_INIT#
LPT_SLIN#
LPT_PD[7..0]
15
15
15
15
15
15
LPT_PD0
LPT_PD1
LPT_PD2
LPT_PD3
LPT_PD4
LPT_PD5
LPT_PD6
LPT_PD7
W83627EHG_PQFP128
15
15
15
15
Temperature Sensing for Future(Reserve)
RT2
0
2E
2
4
6
8
10
VTIN3
CLK48M_SIO1
UART_RTS#1
UART_DTR#1
UART_TX1
SIO_WDT#
SUS_LED
RTS-A
DIO1
1
3
5
7
9
2.7K_8P4R04
RN22
LPT_ACK#
LPT_BUSY
LPT_PE
LPT_SLCT
R182
R184
R186
R188
R190
HM_VREF
+V3.3
3 CLK33M_LPC
3,11 LPC_DRQ#0
3,11,14 SERIRQ
3,5,11,14,20 LPC_AD3
3,5,11,14,20 LPC_AD2
3,5,11,14,20 LPC_AD1
3,5,11,14,20 LPC_AD0
+V3.3
3,5,11,14,20 LPC_FRAME#
3,7,8,9 PCI_RST#
@10K_6_1%
R359 1
@10K_4_1%
VTIN1
@1K_4_1%
1K_4_1%
@1K_4_1%
@1K_4_1%
1K_4_1%
C137
1
C138
D+
C139
R352
@30K_4_1%
0.1U_4_X_10V 0.1U_4_X_10V 0.1U_4_X_10V 0.1U_4_X_10V
2
0.1U_4_X_10V
C136
2
"power use"
RT1
C135
2
C134
0.1U_4_Y_16V OSC48MHZ_SMD
+V3.3
+V3.3
+V3.3
+V3.3
+V3.3_DUAL
UART_TX1
UART_RX1
UART_DTR#1
UART_RTS#1
UART_DSR#1
UART_CTS#1
LPT_PD[7..0]
1
VDD OUT
EN GND
R179 2
15 FDD_RWC#
15 FDD_INDEX#
15
FDD_MOA#
15
FDD_DSA#
15
FDD_DIR#
15 FDD_STEP#
15
FDD_WD#
15
FDD_WE#
+V3.3
15 FDD_TRACK0#
15
FDD_WP#
15 FDD_RDATA#
15 FDD_HEAD#
15 FDD_DSKCHG#
1 33_4
2
1
R180
3
2
+V3.3
1
+V3.3
Y1
UART_RI#1
15
UART_DCD#1 15
2
+V3.3_DUAL
KB_RST#
3
KB_A20GATE 3
SIO_SMI-
R178
10K_4
+V5
SIO_DIN0
SIO_DIN1
SIO_DIN2
SIO_DIN3
MINICARD_DISABLE# 5
KB_DAT#
15
KB_CLK#
15
+V3.3_DUAL
2
1
21
3
15
15
2 @0_4
1
FAN_PWM1
FAN_PWM2
CPUTIN
SY STIN
VID5
VID4
VID3
VID2
VID1
VID0
AUXFANIN0
CPUFANIN0
SY SFANIN
AVCC3
CPUFANOUT0
SY SFANOUT
AGND
BEEP/SI
GP21/CPUFANIN1/MSI
GP20/CPUFANOUT1/MSO
GP17/GPSA2
GP16/GPSB2
GP15/GPY 1
GP14/GPY 2
GP13/GPX2
GP12/GPX1
GP11/GPSB1
GP10/GPSA1
R175 1
1
20
20
PANSWIN
PM_PWRBTN#
MS_DAT#
MS_CLK#
+V3.3_DUAL
@10K_4
+V5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
2
FB32
FB80_6_600MA
FAN_IO1
FAN_IO2
3
21
3
R172
21
HEADER_2X5_2.54
DRVDEN0
GP23/SCK
INDEX
MOA
HM_SMI / OVT
DSA
AUXFANOUT0
DIR
STEP
WD
WE
VCC3_1
TRAK0
WP
RDATA
HEAD
DSKCHG
IOCLK
GP22/SCE
VSS_1
PCICLK
LDRQ
SERIRQ
LAD3
LAD2
LAD1
LAD0
VCC3_2
LFRAME
LRESET
SLCT
PE
BUSY
ACK
PD7
PD6
PD5
PD4
20
20
IOAVCC
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
SIO_WDT#
+VBAT
+V3.3_DUAL
+VBAT
PM_SLP_S3#
PS_ON#
PWROK_SIO
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
HM_VREF
VTIN3
D+
VTIN1
4
4.7K 1
10M_4
10K_4
SUS_LED
U13
TP67
R173
R174
+5VIN
+3.3VIN
VIN2
VIN1
+12VIN
C260
0.1U_4_Y _16V
+V5
PM_PWRBTN#
CASEOPEN#
t
IR CONNECTOR
UART_CTS#2
UART_DSR#2
UART_RTS#2
UART_DTR#2
UART_RX2
UART_TX2
UART_DCD#2
UART_RI#2
WAKE_UP#
@10K_6_1%
R351 1
@10K_4_1%
C426
@3300P_4_X_50V
t
16
16
16
16
16
16
16
16
3
2
"system use"
D-
Voltage Sensing
1
* 4E
ENABLE SPI
* KBC ENABLE
I/O CONFIGURATION ADDRESS
ENABLE SPI
+V12
+V3.3
KBC FUNCTION ENABLE
WDTO#
* TTL LEVEL
VRM10 LEVEL
VID LEVEL SELECTION
SUS_LED
* DISABLE
ENABLE
TEST MODE
+V5
TP69
TP70
1
1
R356
100K_4_1%
+12VIN
R354
10K_4_1%
+3.3VIN
R348
10K_4_1%
R357
10K_4_1%
+5VIN
R349
10K_4_1%
R355
R353
10K_4_1%
10K_4_1%
VIN1
VIN2
R358
10K_4_1% D-
IEI ELECTRONICS INC.
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
SIO(W83627EHG)
Size
Document Number
Date:
Sunday , September 14, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
13
of
23
Default Address: 2E/2F, Entry Key=0X77
UART_RI#3
UART_DCD#3
UART_TX3
UART_RX3
UART_DTR#3
UART_RTS#3
UART_DSR#3
UART_CTS#3
UART_RI#4
UART_DCD#4
U14
ON: UART 4 Addr:0x2e8 IRQ9
OFF :UART 4 Disabled
ON: UART 3 Addr:0x3e8 IRQ5
OFF :UART 3 Disabled
(X,ON) : UART 2 Addr:0x2f8 IRQ4
(ON,OFF): UART 2 Addr:0x2e0 IRQ4
(OFF,OFF):UART 2 disabled.
(X,ON) : UART 1 Addr:0x3f8 IRQ3
(ON,OFF): UART 1 Addr:0x3e0 IRQ3
(OFF,OFF):UART 1 disabled.
ON: Watch Dog Timer enabled and setting
to 10 second when the clock input
is 24Mhz. If the clock input
is 48Mhz , the timer is setting to
5 second.
OFF :disabled.
F81216_PIN18
48
47
46
45
44
43
42
41
40
39
38
37
1
C141
0.1U_4_Y _16V
IRTX
IRRX
RI1
DCD1
SOUT1
SIN1
DTR1
RTS1
DSR1
CTS1
RI2
DCD2
2
C140
0.1U_4_Y _16V
2
1
+V3.3
16
16
16
16
16
16
16
16
16
16
3,5,6,10,11,20 CB_RESET#
TP66
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME#
SERIRQ
+V3.3
CLK48M_SIO2
1
2
3
4
5
6
7
8
9
10
11
12
PCIRST
WDT
GND1
LAD3
LAD2
LAD1
LAD0
PCICLK
LFRAME
SERIRQ
VCC1
CLKIN
SOUT2
SIN2
DTR2
RTS2
DSR2
CTS2
VCC2
GND2
RI3
DCD3
SOUT3
SIN3
36
35
34
33
32
31
30
29
28
27
26
25
+V3.3
UART_TX4
UART_RX4
UART_DTR#4
UART_RTS#4
UART_DSR#4
UART_CTS#4
16
16
16
16
16
16
UART_RI#5
UART_DCD#5
UART_TX5
UART_RX5
16
16
16
16
13
14
15
16
17
18
19
20
21
22
23
24
F81216_PIN34
F81216_PIN36
F81216_PIN42
F81216_PIN44
F81216_PIN24
CTS4
DSR4
RTS4
DTR4
SIN4
SOUT4
DCD4
RI4
CTS3
DSR3
RTS3
DTR3
3,5,11,13,20 LPC_AD3
3,5,11,13,20 LPC_AD2
3,5,11,13,20 LPC_AD1
3,5,11,13,20 LPC_AD0
4 CLK33M_SIO2
3,5,11,13,20 LPC_FRAME#
3,11,13 SERIRQ
1
F81216_PIN26
F81216D
+V3.3
4.7K
C142
0.1U_4_Y _16V
4
1
Y2
VDD OUT
EN GND
3 R192 2
2
UART_DTR#5
UART_RTS#5
UART_DSR#5
UART_CTS#5
UART_RI#6
UART_DCD#6
UART_TX6
UART_RX6
UART_DTR#6
UART_RTS#6
UART_DSR#6
UART_CTS#6
1 33_4 CLK48M_SIO2
OSC48MHZ_SMD
2
1
R191
+V3.3
16
16
16
16
16
16
16
16
16
16
16
16
PIN33
PIN23
PIN41
Address
Entry Key
0
0
0
0x4E/0x4F
0x77
0
0
1
0x2E/0x2F
0x77(D)
0
1
0
0x4e/0x4f
0xa0
0
1
1
0x2E/0x2F
0xa0
1
0
0
0x4E/0x4F
0x87
R193
4.7K
UART_RTS#5
R194
@4.7K
1
0
1
0x2E/0x2F
0x87
R195
4.7K
UART_RTS#4
R196
@4.7K
1
1
0
0x4e/0x4f
0x67
R197
@4.7K
UART_RTS#3
R198
4.7K
1
1
1
0x2E/0x2F
0x67
ON:1
OFF:0
D:default
IEI ELECTRONICS INC.
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
Title
SIO(F81216D)
Size
Document Number
Rev
1.02
F119 ICE-DB-9S-R10
Date:
Sunday , September 14, 2008
Sheet
14
of
23
FLOPPY(only Device A)
KB/MS
F1
2
+V5_KB_R
1
FB19_6_500MA
FUSE_12_1.1A_6V
KB_DAT#
DI
2
13
3
KB_CLK#
13
GND
1
MS_DAT#
13
5
DI
GND
KBCLK
MSDAT
6
DO
5
VCC
L_KDAT
1
L13 FB19_6_500mA
2
L_KCLK
1
L14 FB19_6_500mA
2
L_MDAT
1
L15 FB19_6_500mA
2
L_MCLK
+V5_DUAL
MSCLK
4
CLKI CLKO
CN6A
1
+V5_DUAL
4
CLKI CLKO
3
MS_CLK#
DO
VCC
KBMF01SC6
U16
2
KBDAT
6
L12 FB19_6_500mA
2
KBMF01SC6
1
C145
0.1U_4_Y _16V
C146
0.1U_4_Y _16V
16
17
Dual Mini Din
12
14
13
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
TIN1
TIN2
TIN3
TIN4
EN
SHDN#
C1+
C1V+
FDD1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
R200
1K_4
R201
1K_4
R202
1K_4
R203
1K_4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
FDD_RWC#
13
FDD_INDEX# 13
FDD_MOA#
13
FDD_DSA#
13
FDD_DIR#
13
FDD_STEP# 13
FDD_WD#
13
FDD_WE#
13
FDD_TRACK0# 13
FDD_WP#
13
FDD_RDATA# 13
FDD_HEAD# 13
FDD_DSKCHG# 13
BOXHEADER_2X17_2.54_BLACK
RIN1
RIN2
RIN3
RIN4
RIN5
TOUT1
TOUT2
TOUT3
TOUT4
VCC
GND
C2+
C2V-
9
4
27
23
18
232_DCD#1
232_DSR#1
232_RX1
232_CTS#1
232_RI1
2
3
1
28
232_TX1
232_RTS#1
232_DTR#1
11
10
+V5
COM1
11
232_RI1
16
232_DCD#1
232_DSR#1
232_RX1
232_RTS#1
232_TX1
232_CTS#1
232_DTR#1
232_RI1
ADM213LEEA_SSOP28
0_6
0_6
0_6
0_6
0_6
0_6
0_6
0_6
1
6
2
7
3
8
4
9
5
CN7
180P_8P4C_N_50V
15 0.1U_4_Y _16V
C148
16
17
R204
R205
R206
R207
R208
R209
R210
R211
2
4
6
8
24
25
0.1U_4_Y_16V
C147
B7
B8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
1
3
5
7
7
6
20
21
+V5
B1
B2
B3
B4
B5
B6
13
14
15
IO_GND
U17
8
5
26
22
19
13
UART_TX1
13 UART_RTS#1
13 UART_DTR#1
A7
A8
A9
2
1
2
C144
0.1U_4_Y _16V
13 UART_DCD#1
13 UART_DSR#1
13
UART_RX1
13 UART_CTS#1
13
UART_RI#1
7
8
9
10
11
12
R199
1K_4
Dual Mini Din
A1
A2
A3
A4
A5
A6
CN6B
+V5_KB_R
C143
10U_8_X_6V3
1
2
3
4
5
6
2
4
6
8
13
1
U15
+V5
+V5_KB_RR
C149
0.1U_4_Y _16V
IO_GND
+V5
COM1
10
CN8
180P_8P4C_N_50V
1
3
5
7
+V5_DUAL
FB5
IO_GND
DB9
IO_GND
ATMEGA Programimg Port(Reserve)
LPT
+V5
1
A
U18
LPT_PD7
LPT_PD6
LPT_PD5
LPT_PD4
LPT_PD3
LPT_PD2
LPT_PD1
LPT_PD0
13
LPT_STB#
13
13
13
LPT_SLIN#
LPT_INIT#
LPT_AFD#
13
LPT_ERR#
14
13
11
9
7
6
5
4
3
2
1
28
27
Select
PError
BUSY
ACK
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PSTROBE
SelectIn
INIT
AUTOFD
FAULT
PD_7
PD_6
PD_5
PD_4
PD_3
PD_2
PD_1
PD_0
STROBE
16
17
18
19
21
23
24
25
26
C150
0.1U_4_Y _16V
LPT_PDD7
LPT_PDD6
LPT_PDD5
LPT_PDD4
LPT_PDD3
LPT_PDD2
LPT_PDD1
LPT_PDD0
LPT_STB#_R
LPT_PD[7..0]
LPT_PDD4
LPT_PDD5
LPT_PDD6
LPT_PDD7
LPT_PD[7..0]
LPT_ACK#
13
LPT_BUSY
GND
22
LPT_PE
LPT_SLCT
PACSZ128402_QSOP28
IO_GND
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
LPT1
+V5
C255
0.1U_4_Y_16V
J2
2
LPT_STB#_R
LPT_AFD#
LPT_PDD0
LPT_ERR#
LPT_PDD1
LPT_INIT#
LPT_PDD2
LPT_SLIN#
LPT_PDD3
20
1
LPT_SLCT
LPT_PE
LPT_BUSY
LPT_ACK#
VCC
2
13
13
13
13
8
10
12
15
C1
C2
Q8
BAT54A_SOT23_3
3 ATMEGA_MISO
3 ATMEGA_SCK
3
ATMEGA_SS
ATMEGA_MISO 1
ATMEGA_SCK 3
ATMEGA_SS 5
2
4 ATMEGA_MOSI
6
ATMEGA_MOSI 3
@HEADER_2X3_2.54
28
27
26
IO_GND
IEI ELECTRONICS INC.
Title
DB25
Size
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
LPT,FLOPPY,KB/MS,COM1
Document Number
Rev
1.02
F119 ICE-DB-9S-R10
Date:
Sunday , September 14, 2008
Sheet
15
of
23
+V5
0.1U_4_Y_16V
C152
C151
0.1U_4_Y _16V
12
14
13
11
10
VCC
GND
C1+
15 0.1U_4_Y _16V
C153
C2+
C1V+
+V5
16
17
C2V-
ADM213LEEA_SSOP28
232_DSR#2
232_RTS#2
232_CTS#2
232_RI2_SELECT
6
7
8
9
10
6
7
8
9
10
COM_5X2_2.54
CN9
180P_8P4C_N_50V
CN10
180P_8P4C_N_50V
JP2(3-4)
+V5
0.1U_4_Y _16V
C155
C154
0.1U_4_Y_16V
JP2
232_RI2_SELECT
C158
0.1U_4_Y _16V
7
6
20
21
14
UART_TX4
14 UART_RTS#4
14 UART_DTR#4
24
25
+V5
0.1U_4_Y_16V
C166
12
2
4
6
RIN1
RIN2
RIN3
RIN4
RIN5
TIN1
TIN2
TIN3
TIN4
TOUT1
TOUT2
TOUT3
TOUT4
EN
SHDN#
VCC
GND
C1+
+V5
232_RI2
+V12
9
4
27
23
18
232_DCD#4
232_DSR#4
232_RX4
232_CTS#4
232_RI4
2
3
1
28
232_TX4
232_RTS#4
232_DTR#4
11
10
+V5
+V12
COM4
RXD232
7
6
20
21
14
UART_TX6
14 UART_RTS#6
14 UART_DTR#6
VCC
GND
+V5
C1+
C2+
8
5
26
22
19
14 UART_DCD#5
14 UART_DSR#5
14
UART_RX5
14 UART_CTS#5
14
UART_RI#5
C162
0.1U_4_Y_16V
7
6
20
21
14
UART_TX5
14 UART_RTS#5
14 UART_DTR#5
1
2
3
4
5
COM4
1
2
3
4
5
232_DSR#4
232_RTS#4
232_CTS#4
232_RI4
6
7
8
9
10
6
7
8
9
10
24
25
+V5
0.1U_4_Y _16V
C169
C1V+
C2V-
12
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
RIN1
RIN2
RIN3
RIN4
RIN5
TIN1
TIN2
TIN3
TIN4
TOUT1
TOUT2
TOUT3
TOUT4
EN
SHDN#
VCC
GND
C1+
C2+
C1V+
C2V-
C168
0.1U_4_Y_16V
COM_5X2_2.54
16
17
C2V-
C160
10U_8_X_6V3
0.1U_4_Y _16V
232_DCD#4
232_RX4
232_TX4
232_DTR#4
16
17
C157
0.1U_4_Y_16V
14
13
C171
0.1U_4_Y _16V
9
4
27
23
18
232_DCD#5
232_DSR#5
232_RX5
232_CTS#5
232_RI5
2
3
1
28
232_TX5
232_RTS#5
232_DTR#5
11
10
+V5
15 0.1U_4_Y_16V
C170
TOUT1
TOUT2
TOUT3
TOUT4
+V5
0.1U_4_Y_16V
C174
C173
0.1U_4_Y _16V
12
14
13
EN
SHDN#
232_DCD#6
232_DSR#6
232_RX6
232_CTS#6
232_RI6
9
4
27
23
18
VCC
GND
C1+
C2+
C1V+
C2V-
232_RI4
232_RI5
232_RI6
COM5
2
4
6
232_RI3
+V5
+V12
+V12
+V5
C161
C163
10U_8_X_6V3
0.1U_4_Y_16V
232_DCD#5
232_RX5
232_TX5
232_DTR#5
1
2
3
4
5
COM5
1
2
3
4
5
6
7
8
9
10
C164
0.1U_4_Y _16V
232_DSR#5
232_RTS#5
232_CTS#5
232_RI5
6
7
8
9
10
COM_5X2_2.54
C172
0.1U_4_Y_16V
RS232
RS422
232_DCD#6
232_RX6
232_TX6
232_DTR#6
RS485
MINIJUMPER_1X2_2
232_TX6
232_RTS#6
232_DTR#6
2
3
1
28
14
UART_RX6
11
10
UART_RX6
1
3
5
JP6
RXD232
RXD422
RXD485
2
4
6
TXD485+
RXD485+
1
3
5
7
9
11
13
COM6
DCD
RXD
TXD
DTR
GND1
T_485
R_485
232_DSR#6
232_RTS#6
232_CTS#6
232_RI6
2
4
6
8
10
12
14
DSR
RTS
CTS
RI
GND2
T_485
R_485
TXD485#
RXD485#
BOXHEADER_2X7_2.54_BLACK
V1.01 Modify
+V5
15 0.1U_4_Y _16V
C175
16
17
RXD422
1
2
3
4
U24
8
7
6
5
+V12
R212
@120_4
+V5
C176
0.1U_4_Y _16V
+V5
C177
RXD485#
RXD485+
0.1U_4_Y_16V
R213
@120_8
C178
10U_8_X_6V3
C179
0.1U_4_Y_16V
ADM485AR_SOP8
+V5
C
A2
Q20
BAT54C_SOT23
D23
MMBT2222ALT1_SOT23
A1
CR484
75K_6
A2
BAT54C_SOT23
D24
A1
C
A2
+V5
R214
@0_4
R485
8.2K_4
E
232_RI3
232_RI3_SELECT
PCIE_WAKE_UP# 3,5,6,10
C
B
232_RI2
JP3
1
3
5
JP6(1-2)
UART_RTS#6
D25
A1
JP3(3-4)
COM6 PIN HEADER
232_RI1
232_RI1
CN12
180P_8P4C_N_50V
COM6 Signal Jumper Setting
ADM213LEEA_SSOP28
15
232_DSR#3
232_RTS#3
232_CTS#3
232_RI3_SELECT
6
7
8
9
10
6
7
8
9
10
COM_5X2_2.54
CN11
180P_8P4C_N_50V
16
17
HEADER_2X3_2
24
25
1
2
3
4
5
ADM213LEEA_SSOP28
RIN1
RIN2
RIN3
RIN4
RIN5
TIN1
TIN2
TIN3
TIN4
COM3
HEADER_2X3_2
COM6(RS232/422/485)
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
1
2
3
4
5
15 0.1U_4_Y_16V
C156
+V5
C159
U23
14 UART_CTS#6
14
UART_RI#6
11
10
232_DCD#3
232_RX3
232_TX3
232_DTR#3
ADM213LEEA_SSOP28
HEADER_2X3_2
15 0.1U_4_Y _16V
C167
C2+
C1V+
8
5
26
22
19
232_TX3
232_RTS#3
232_DTR#3
MINIJUMPER_1X2_2
14
13
ADM213LEEA_SSOP28
14 UART_DCD#6
14 UART_DSR#6
2
3
1
28
U22
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
C165
0.1U_4_Y _16V
14
13
TOUT1
TOUT2
TOUT3
TOUT4
EN
SHDN#
12
U21
8
5
26
22
19
14 UART_DCD#4
14 UART_DSR#4
14
UART_RX4
14 UART_CTS#4
14
UART_RI#4
TIN1
TIN2
TIN3
TIN4
24
25
MINIJUMPER_1X2_2
1
3
5
7
6
20
21
14
UART_TX3
14 UART_RTS#3
14 UART_DTR#3
COM3
2
4
6
8
1
2
3
4
5
232_DCD#3
232_DSR#3
232_RX3
232_CTS#3
232_RI3
2
4
6
8
COM2
1
2
3
4
5
9
4
27
23
18
1
3
5
7
EN
SHDN#
232_DCD#2
232_RX2
232_TX2
232_DTR#2
RIN1
RIN2
RIN3
RIN4
RIN5
1
3
5
7
TOUT1
TOUT2
TOUT3
TOUT4
232_TX2
232_RTS#2
232_DTR#2
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
2
4
6
8
TIN1
TIN2
TIN3
TIN4
2
3
1
28
8
5
26
22
19
14 UART_DCD#3
14 UART_DSR#3
14
UART_RX3
14 UART_CTS#3
14
UART_RI#3
1
3
5
7
24
25
RIN1
RIN2
RIN3
RIN4
RIN5
232_DCD#2
232_DSR#2
232_RX2
232_CTS#2
232_RI2
2
4
6
8
7
6
20
21
13
UART_TX2
13 UART_RTS#2
13 UART_DTR#2
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
9
4
27
23
18
1
3
5
7
13 UART_DCD#2
13 UART_DSR#2
13
UART_RX2
13 UART_CTS#2
13
UART_RI#2
U20
COM2
U19
8
5
26
22
19
R218
1K_4
SOT23
D9
C441
2.2U_8_Y _25V
UART_TX6C
R215
0_4
+V5
R216
@1K_4
1
A2
2
A1
3
BAT54C_SOT23_3 C180
0.01U_4_X_16V
U25
5
R219
4.7K_4
+V5
RXD485
4
SN74LVC1G00DCKR_SOT23_5
R217
@120_4
T485_EN
1
2
3
4
U26
R220
2.2K_4
+V5
+V5
8
7
6
5
TXD485#
TXD485+
R221
120_8
IEI ELECTRONICS INC.
ADM485AR_SOP8
BAT54C_SOT23
R222
2.2K_4
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
Title
COM2,3,4,5,6/RS422/485
Size
Document Number
Date:
Sunday , September 14, 2008
+V5
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
16
of
23
R249
@0_4
U31
2
1
FLGB
GND
FLGA
IN
ENA
OUTA
FB6
5
+V5_USB0
1
OUTB
6
C286+
7
GCB1608K-300
3
USB0-
3
USB0+
FB7
8
C287+
ENA
7
+V5_USB2
3
USB2-
3
USB2+
COMCHOKE_8_USB
2
1
3
C289
+
150U_TNC_SMD_6V3
4
+V5_USB2
USB2-_R
USB2+_R
H3
U1
U2
U3
U4
H4
2
1
OUTB
FLGB
GND
FLGA
IN
ENA
OUTA
FB36
5
+V5_USB4
1
ENB
C290
+
150U_TNC_SMD_6V3
6
7
USB0+_R 3
4
USB1+_R
6
USB3-_R
PACDN006
COMCHOKE_8_USB
1
2
4
3
USB2-_R 1
USB3-
3
USB3+
3
D11
5 +V5_USB23
2
IO_GND
USB2+_R 3
4
USB3+_R
6
USB5-_R
PACDN006
L20
3
USB4-
3
USB4+
COMCHOKE_8_USB
2
1
3
+V5_USB4
USB4-_R
USB4+_R
4
1
3
5
7
V1.01 Modify
2
4
6
8
USB5+_R
USB5-_R
+V5_USB5
L21
1
USB4-_R 1
3
2
USB5+
3
USB5-
3
D12
5 +V5_USB45
2
IO_GND
USB4+_R 3
USB5+_R
4
PACDN006
COMCHOKE_8_USB
L19
GCB1608K-300
4
HEADER_2X4_2.54
2
3
5 +V5_USB01
IO_GND
USB1
FB37
8
+V5_USB5
1
4
3 USB_4_5_OC#
USB1-_R
6
IO_GND
GCB1608K-300
U33
3
IO_GND
+V5_USB3
USB3-_R
U7 USB3+_R
U8
IO_GND
+V5_USB3
2
MIC2026
USB1+
D10
2
IO_GND
IO_GND
L18
GCB1608K-300
FB33
8
3
H6
IN
OUTA
C288
+
150U_TNC_SMD_6V3
3
USB0-_R 1
USB1-
L17
CN26
2
FLGA
1
FB8
5
6
4
IO_GND
1
GND
COMCHOKE_8_USB
1
2
LJ-G40BU1-10
2
OUTB
FLGB
4
+V5_USB1
USB1-_R
USB1+_R
5
6
7
8
VCC1VCC2
D1D2D1+
D2+
GND1GND2
+V5_USB1
1
2
ENB
1
2
3
4
GCB1608K-300
U32
3
3
LAN_USB1B
+V5_USB0
USB0-_R
USB0+_R
L16
150U_TNC_SMD_6V3
4
COMCHOKE_8_USB
2
1
150U_TNC_SMD_6V3
MIC2026
3 USB_2_3_OC#
USB for ESD Protect
2
3
ENB
USB Port0~6
1
4
3 USB_0_1_OC#
USB Power control
H5
U6U5
+V5_DUAL
C291
+
150U_TNC_SMD_6V3
GCB1608K-300
+V5_USB01C181 0.1U_4_Y _16V
2
MIC2026
R375
0_4
+V5_USB01C182 0.1U_4_Y _16V
+V5_USB23C183 0.1U_4_Y _16V
+V5_USB23C184 0.1U_4_Y _16V
+V5_USB45C185 0.1U_4_Y _16V
+V5_USB45C186 0.1U_4_Y _16V
+V3.3_DUAL
8
6
4
2
Giga Lan Connector
RN28
330_8P4R04
1
3
5
7
3,20
I2C_CK
3,20
I2C_DAT
3,4,5,6,10,11,20 SMB_CK
3,4,5,6,10,11,20 SMB_DAT
CN25
2
4
6
8
7
5
3
1
I2C BUS/SMBUS：GPI0~3, GPI0~3,
F75111R_CK
F75111R_DAT
LAN_USB1A
HEADER_2X4_2.54
+V3.3
8
6
4
2
RN25
8.2K_8P4R04
FADDR
F75111R_GPIO1
F75111R_GPIO2
F75111R_GPIO3
F75111R_GPIO4
TP64
1
+V3.3
+V3.3
R364
10K_4
F75111R_DAT
F75111R_CK
7
5
3
1
C259 0.1U_4_Y _16V
U30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
GPIO30
GPIO13/I2C_ADDR
GPIO16
GPIO17
GPIO20
GPIO21
GPIO22
GPIO14
WDT2#
GPIO11
GPIO12
DATA
CLOCK
GND
GPIO31
GPIO32
GPIO33
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO15
VCC
GND
GND
WDT1#
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+V3.3
+V5
F75111R_GPIO5
F75111R_GPIO6
F75111R_GPIO7
F75111R_GPIO8
+V3.3
1
R362 @10K_4
Stuff ADDRESS=0x6Eh
NL
ADDRESS=0x9Ch
FB35
GCB1608K-300
FB34 @GCB1608K-300
CN27
1
F75111R_GPIO1 3
F75111R_GPIO2 5
F75111R_GPIO3 7
F75111R_GPIO4 9
11
+V3.3
R365
10K_4
P8
P9
3 GBE0_MDI3+
3 GBE0_MDI3-
RN24
8.2K_8P4R04
TP65
+V3.3
FADDR
P6
P7
3 GBE0_MDI2+
3 GBE0_MDI2-
C258 0.1U_4_Y _16V
7
5
3
1
CN25(7-8)
JUMP_1X2_2.54mm
P4
P5
3 GBE0_MDI1+
3 GBE0_MDI1-
8
6
4
2
+V3.3
CN25(5-6)
JUMP_1X2_2.54mm
P2
P3
3 GBE0_MDI0+
3 GBE0_MDI0-
C280 0.1U_4_Y _16V
F75111R_GPIO1R366
470_4
LED-GREEN(0603)
C
LED10
A
F75111R_GPIO2R367
470_4
LED-GREEN(0603)
C
LED11
A
F75111R_GPIO3R368
470_4
LED-GREEN(0603)
C
LED12
A
F75111R_GPIO4R369
470_4
LED-GREEN(0603)
C
LED13
A
0_4
P1
P10
2
4
6
8
10
12
Y ELLOW
LEFT-P
LEFT-N
MD1+
MD1-
RIGHT-P
RIGHT-N
GREEN
FG1
FG2
PG3
FG4
FG5
FG6
FG7
FG8
MD2+
MD2MD3+
MD3CT1
GND
P14
P13
P12
P11
R229
220_4
R230
R231
0_4
220_4
R232
0_4
15
16
9
10
11
12
13
14
GBE0_ACT#
GBE0_LINK#
3
3
GBE0_LINK1000# 3
GBE0_LINK100# 3
V1.02 Modify
C187
0.1U_4_Y _16V
F75111R_GPIO5
F75111R_GPIO6
F75111R_GPIO7
F75111R_GPIO8
IO_GND
HEADER_2X6_2.54
+V3.3
FINTEK F75111R
+V1.8_LAN
R233
LJ-G40BU1-10
MD0+
MD0-
+V3.3
F75111R_GPIO5R373
470_4
LED-GREEN(0603)
C
LED16
A
F75111R_GPIO6R370
470_4
LED-GREEN(0603)
C
LED14
A
F75111R_GPIO7R371
470_4
LED-GREEN(0603)
C
LED15
A
F75111R_GPIO8R372
470_4
LED-GREEN(0603)
C
LED17
A
IEI ELECTRONICS INC.
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
LAN,USB01,2,3,4,5,I2C GPIO
Size
Document Number
Date:
Monday , September 15, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
17
of
23
Digital
VOUT
VIN
GND
FB9
2
3
2
C188
0.1U_4_Y _16V
GS78L05N_TO92_3
TO92_123
+V12
EC12
100U_SMD6_3_EC_25V
3
AC_SYNC
3
3
AC_SDOUT
AC_SDIN0
3
AC_BITCLK
R236 2
1 0_4
AC_RST#_R
11
R234 2
1 0_4
AC_SYNC_R
10
R237 2
R238 2
1 0_4
1 0_4
AC_SDOUT_R
AC_SDIN0_R
5
8
R239 2
1 0_4
AC_BITCLK_R
PRESENCE#
10K_4_1%
2
SPKR
C196
1U_6_Y _10V
2
1HDA_PCBEEPC
R241
1
2
R243
1K_4_1%
C197
100P_4_N_50V
1 0_4 GPIO
2
3
HDA_PCBEEPC
12
R240 2
1
AUDIO_LINE2-L
AUDIO_LINE2-R
14
15
AUDIO_MIC2-L
AUDIO_MIC2-R
16
17
AUDIO_CD_L
AUDIO_CD_GND
AUDIO_CD_R
18
19
20
25
38
VAUX
SYNC
FRONT-OUT-L
FRONT-OUT-R
SDATA-OUT
SDATA-IN
BITCLK
SURR-OUT-L
SURR-OUT-R
SPDIFI / EAPD
SPDIFO
CEN-OUT
LFE-OUT
GPIO0
GPIO1
SIDESURR-OUT-L
SIDESURR-OUT-R
PC-BEEP
SenseA
SenseB
LINE2-L
LINE2-R
Analog
19
19
MIC1-L
MIC1-R
19
19
LINE_IN_L
LINE_IN_R
MIC1-L
MIC1-R
21
22
LINE_IN_L
LINE_IN_R
23
24
CD-L
CD-G
CD-R
MIC1-VREFO-L
LINE1-VREFO
MIC2-VREFO
MIC1-L
MIC1-R
LINE2-VREFO
MIC1-VREFO-R
LINE1-L
LINE1-R
VREFO
24.7K_4
1
R2581
2
1
2
SURR_OUT_L
SURR_OUT_R
43
44
CEN-OUT
LEF-OUT
45
46
SIDESURR_L
SIDESURR_R
13
34
SenseA
SenseB
CEN-OUT
LEF-OUT
2 4.7K_4
1
2
2 4.7K_4
1
2
AVSS1
AVSS2
MIC1-VREFO-L
29
LINE1-VREFO
30
MIC2-VREFO
31
LINE2-VREFO
32
MIC1-VREFO-R
37
SURR-VREFO
40
JDREF
27
VREF
1
2
3
4
LCD_GND
MIC1-VREFO-L 19
LINE1-VREFO 19
C
3
1
AUDIO_MIC2-L
AUDIO_MIC2-R
K1
C207
100U_TNC_SMD_6V3
CMIC2-L
1
2
C208
100U_TNC_SMD_6V3
CMIC2-R
1
2
Analog_GND
@HEADER_1X4_2.54
Digital
LCD_R
D13
AUDIO_LINE2-L
19
R245 1
2 20K_6_1% MIC1-JD
MIC1-JD
19
SURR-JD
19
39.2K_8_1%SURR-JD
R247 1
2 5.1K_6_1% SIDESURR-JD
SIDESURR-JD 19
R248 1
2 10K_4_1% CEN-JD
CEN-JD
R250 2
1 0_4
1
RMIC2-L
75_4
2
1
RMIC2-R
75_4
1
1
1
1
R271
47K_4
2
R272
47K_4
2
Analog_GND
LMIC2-L
Analog_GND
C199
10U_8_X_6V3
R253
20K_6_1%
LMIC2-L
1
LMIC2-R
3
LLINE2-R
5
FRONT-IO
7
LLINE2-L
9
CN20
MIC2-L
GND
MIC2-R
Presence#
LINE2-R
MIC2-JD
Sense
Key
LINE2-L
LINE2-JD
R251
10K_4_1%
2
1
4
PRESENCE#
6
MIC2-JD
8
10
LINE2-JD
2
HEADER_2X5-8_2.54
R256
20K_6_1%
R255
39.2K_8_1%
1
C
BAT54A_SOT23
K2
2
D3-2
R261 4.7K_4
1
2
K1
D3-1
R262 4.7K_4
1
2
3
C203
100U_TNC_SMD_6V3
CLINE2-R
1
2
2
C204
R263
100U_TNC_SMD_6V3
CLINE2-L
1
2
2
R265
1
1
Analog_GND
FB15
FB_80_6_600MA
RLINE2-R
1
2
RLINE2-L
1
2
75_4
75_4
1
2
R268
47K_4
LLINE2-R
LLINE2-L
FB16
FB_80_6_600MA
1
C205
100P_4_N_50V
2
2
1
C206
100P_4_N_50V
2
LMIC2-R
2
FB18
FB_80_6_600MA
1
2
Front_Audio
R267
47K_4
2
1
+V3.3
FB17
FB_80_6_600MA
2
Digital
19
FRONT-IO
1
R266 4.7K_4
D1-1 1
2
R270
19
LINE1-JD
Analog_GND
R264 4.7K_4
D1-2 1
2
R269
FRONT-JD
2 10K_4_1% LINE1-JD
1
AUDIO_LINE2-R
MIC2-VREFO
2 5.1K_6_1% FRONT-JD
R244 1
SURR-VREFO 19
1
BAT54A_SOT23
K2
2
R242 1
MIC1-VREFO-R 19
CN21
LINE2-VREFO
D14
19
19
SIDESURR_L 19
SIDESURR_R 19
2
C198
0.1U_4_Y _16V
FB14
1@4.7K_4 Analog_GNDFB_80_6_600MA
R2601
28
Analog_GND
SURR_OUT_L 19
SURR_OUT_R 19
ALC883
LCD_L
FB13
1@4.7K_4 Analog_GNDFB_80_6_600MA
C202
1U_6_Y _10V R259 2
AUDIO_CD_R
39
41
FB11
FB_80_6_600MA
FRONT_OUT_L 19
FRONT_OUT_R 19
2
R2541
2
QFP48_9X9
FB12
1@4.7K_4 Analog_GNDFB_80_6_600MA
C201
1U_6_Y _10V R257 2
1
VREF
26
42
DVSS1
DVSS2
4
7
C200
1U_6_Y _10V R252 2
AUDIO_CD_GND
FRONT_OUT_L
FRONT_OUT_R
R246
CD_IN(Reserve)
2
35
36
Analog_GND
MIC2-L
MIC2-R
JDREF
1
VAUX
2
1
AUDIO_CD_L
FB10
FB_80_6_600MA
R235 10K_4_1%
1
2
33
1
3,20,21
6
47
48
19 SPDIFIN
19 SPDIFOUT
RESET#
C195
10U_8_X_6V3
Analog_GND
U27
AVDD1
AVDD2
1
9
AC_RST#
DVDD1
DVDD2
3
C194
10U_8_X_6V3
1
C193
0.1U_4_Y _16V
2
C192
0.1U_4_Y _16V
1
C191
10U_8_X_6V3
2
C190
0.1U_4_Y _16V
2
C189
0.1U_4_Y _16V
1
2
+V3.3
FB_80_6_600MA
1
2
Q9
1
+V5_AUDIO
Analog_GND
1
2
C209
100P_4_N_50V
1
Analog_GND
C210
100P_4_N_50V
IEI ELECTRONICS INC.
2
Analog_GND
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
HDA ALC888
Size
Document Number
Date:
Sunday , September 14, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
18
of
23
Audio Rear Jack
C28-1
@1U_6_Y _10V
1
2
LEF-OUT
18
CEN-OUT
LEF-OUT
CEN-OUT
1
R273 75_4
2
1
CLEF-OUT
CCEN-OUT 2
2
C212
100U_TNC_SMD_6V3
1
FB19
FB_80_6_600MA
1
2
1
R278
47K_4
SURR_OUT_R
D4-2
R281 4.7K_4
1
2
K1
D4-1
R282 4.7K_4
1
2
C221
100U_TNC_SMD_6V3
1
2
SURR_OUT_L
18 SURR_OUT_L
1
LCEN-OUT
2
2
1
1
2
2
Analog_GND
18
LFRONT-R
FRONT-JD
25
24
23
22
18
MIC1-JD
LMIC1-R
MIC1-JD
C216
100P_4_N_50V
5
4
3
2
1
LMIC1-L
Audio Rear Header
35
34
33
32
LINE IN
(Bule)
25
24
23
22
LINE OUT
(Green)
5
4
3
2
1
MIC IN
(Ping)
18
CEN-JD
18 SIDESURR-JD
LLEF-OUT
CEN-JD
LSURR-R
SIDESURR-R
SIDESURR-JD
AUDIO2
1
3
5
7
9
2
4
6
8
10
LCEN-OUT
SURR-JD
LSURR-L
SIDESURR-L
SURR-JD
18
IO_GND
HEADER_2X5_2.54
CEN/LFE OUT
(Orange)
SURR. OUT
(Black)
IO_GND
SIDE OUT
(Gray)
R285 75_4
2
1
CSURR-L
2
1
R286 75_4
1
R289
47K_4
C37-1
@1U_6_Y _10V
RSURR-R
1
RSURR-L
1
LSURR-L
2
FB26
FB_80_6_600MA
1
R290
47K_4
2
Desktop Configuation 1: (7.1 Channel Solution)
Rear Panel: 6 jacks have specific functionality
Front Panel: 2 jacks are Universal Audio Jack
FB25
FB_80_6_600MA
FB0603
LSURR-R
2
C225
100P_4_N_50V
2
1
MIC1-VREFO-R
R2911
2 4.7K_4
MIC1-VREFO-L
R2921
2 4.7K_4
1
2
Analog_GND
18 MIC1-VREFO-L
LLINE-L
AUDIO1
EARPHONE JACK STAND
IO_GND
CSURR-R
C222
100U_TNC_SMD_6V3
1
2
18 MIC1-VREFO-R
35
34
33
32
LFRONT-L
C215
100P_4_N_50V
C35-1
@1U_6_Y _10V
1
2
18 SURR_OUT_R
2
1
R277
47K_4
3
1
1
LLEF-OUT
LLINE-R
LINE1-JD
NC5
NC4
NC3
NC2
NC1
D15
BAT54A_SOT23
K2
2
C
RCEN-OUT
2
LINE1-JD
FB20
FB_80_6_600MA
2
SURR-VREFO
1
R274 75_4
C30-1
@1U_6_Y _10V
18 SURR-VREFO
RLEF-OUT
18
NC5
NC4
NC3
NC2
NC1
18
C211
100U_TNC_SMD_6V3
1
2
C226
100P_4_N_50V
2
IO_GND
Pin Assignment
Location
FUNCTION
FRONT(pin-35/36)
Back Panel
Front line out w/ ampifier,Line_in
SURR (pin-39/41)
Back Panel
Surround line out, Line_in
Back Panel
Center/Lft line out,Line_in
CEN/LFE (pin-43/44)
SIDESURR (pin-45/46) Back Panel
Side surround line out,Line_in
LINE1 (pin-23/24)
Back Panel
Line in / Shared surround out
MIC1 (pin-21/22)
Back Panel
Mic in / Shared Center-Lft out/Line_in
LINE2 (pin-14/15)
Front Panel
Headphone out/ line in/ mic in
Front Panel
MIC2 (pin-16/17)
Mic in/ Headphone out / line in
SPDIF Connector(Reserve)
C38-1
@1U_6_Y _10V
1
2
18
MIC1-R
MIC1-R
18
MIC1-L
MIC1-L
C227
100U_TNC_SMD_6V3
1
2
1
2
R293 75_4
CMIC1-R 2
1
RMIC1-R 1
CMIC1-L 2
RMIC1-L 1
C228
100U_TNC_SMD_6V3
1
2
1
R294 75_4
1
R295
47K_4
C36-1
@1U_6_Y _10V
R296
47K_4
SPDIFOUT
C744 0.01U
C229
100P_4_N_50V
1
2
C230
2 100P_4_N_50V
10K@ALC880/260,
12K@ALC882,
NC@ALC883/262
2
IO_GND
18 SPDIFIN
SPDIFIN
10
2
K2
D2-2
R297 4.7K_4
1
2
K1
D2-1
R298 4.7K_4
1
2
3
1
LINE_IN_R
LINE_IN_R
18
LINE_IN_L
LINE_IN_L
C231
100U_TNC_SMD_6V3
1
2
1
R299 75_4
CLINE-R 2
1
CLINE-L
2
C232
100U_TNC_SMD_6V3
1
2
2
R300 75_4
FB29
FB_80_6_600MA
2
RLINE-R 1
RLINE-L
1
1
R301
47K_4
C43-1
@1U_6_Y _10V
1
18 SIDESURR_L
FB30
FB_80_6_600MA
R302
47K_4
2
18 SIDESURR_R
LLINE-L
2
1
LLINE-R
1
C233
2
100P_4_N_50V
2
Analog_GND
18 FRONT_OUT_L
1
C234
2 100P_4_N_50V
C639
R545
@10K
.
SPDIF_IN
0.01UF
.
1
R583
75
RFRONT-R
FRONT_OUT_L
RFRONT-L
1
2
C638
100P_4_N_50V
FB23
FB_80_6_600MA
C219
100U_TNC_SMD_6V3
SIDESURR_R
1
2
R283 75_4
2
1
1
2
SIDESURR-R
SIDESURR_L
2
1
2
SIDESURR-L
1
2
C220
100U_TNC_SMD_6V3
1
R284 75_4
FB24
FB_80_6_600MA
1
R287
47K_4
CFRONT-L 2
1
1
1
R276 75_4
1
R288
47K_4
2
1
C223
2
100P_4_N_50V
1
C224
2 100P_4_N_50V
IO_GND
FB21
FB_80_6_600MA
C213
100U_TNC_SMD_6V3
R275 75_4
FRONT_OUT_R 1
CFRONT-R 2
2
1
C214
100U_TNC_SMD_6V3
3
4
5
@PIN HEADER 1*5
2
18 FRONT_OUT_R
1
3
4
5
R547
@10K
.
R546
SPDIF1
1
2
C44-1
@1U_6_Y _10V
1
2
18
C745
100P_4_N_50V
2
D16
BAT54A_SOT23
C
1
R582
100
+V3.3
1
10K@ALC880/882/882,
NC@ALC883/262
LINE1-VREFO
SPDIF_OUT
+V5_AUDIO
Analog_GND
18 LINE1-VREFO
100__6_5%
R581
LMIC1-L
2
FB28
FB_80_6_600MA
1
2
18 SPDIFOUT
FB27
FB_80_6_600MA
LMIC1-R
2
Analog_GND
2
LFRONT-R
2
LFRONT-L
IO_GND
FB22
FB_80_6_600MA
1
R279
47K_4
1
R280
47K_4
2
2
Analog_GND
C217
100P_4_N_50V
1
1
2
C218
2 100P_4_N_50V
IO_GND
IEI ELECTRONICS INC.
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
AUDIO 7.1 Channel
Size
Document Number
Date:
Sunday , September 14, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
19
of
23
Q10
CLEAR CMOS/Super CAP
A1
1 4.7K_4
1
C235
Q11
4 CLK33M_BIOS2
A1
R305
1K_4
1
A2
2
+V3.3
+VBAT
8.2K_4
CON3_HDR
BAT54C
SOT23_AAC
BAT1
C237
10U_8_X_6V3
R307
1K_4
BT2
C239
0.1U_4_Y _16V
FPG14
2 R306
FGPI3
1
FGPI2
3
FGPI1
5
FGPI0
7
1
2
4
6
8
8.2K_8P4R04
DCBAT_3V
RN23
5
6
7
8
9
10
11
12
13
U28(ROM)
+V3.3
R309 2
R310 2
1 4.7K_4
1 4.7K_4
PLCC32
+V12
FGPI1
FGPI0
WP#
TBL#
ID3
ID2
ID1
ID0
FWH0
C240
+V12
U28
FWH
IC
GNDA
VCCA
GND
VCC
INIT#
FWH4
RFU22
RFU21
C236
C238
0.1U_4_Y _16V 0.1U_4_Y _16V
FW_IC
29
28
27
26
25
24
23
22
21
8.2K_4 1
FWH_INIT#
2 R308
R311 2
1K_4
1 @4.7K_4
R312
+V3.3
FWH1
FWH2
GND
FWH3
RFU18
RFU19
RFU20
SKT_PLCC32_SMD
CPU FAN W/FAN Control
JP8(1-2)
JUMP_1X2_2.54mm
3,5,6,10,11,14 CB_RESET#
JP9
3
CR2032-HOLDER
BIOS_DISABLE# 3
1
C
2
CON3_HDR
1
@0.22F Super Cap
JP8
3
2
2
BAT54C
SOT23_AAC
R303 2
+V3.3
JP9(1-2)
JUMP_1X2_2.54mm
4
3
2
1
32
31
30
A2
Second BIOS
R304
FGPI2
FGPI3
RST#
VPP
VCC
CLK
FPG14
1
1K_4
2
C
+V3.3_DUAL
1
14
15
16
17
18
19
20
0.1U_4_Y _16V
C268
+V5
2
10UF_1210_16V
FAN1
R313
4.7K
1
2
3
4
GND
+12V
SENSE
CONTROL
1K_4
CPUFAN_4_2.54
13
FAN_PWM1
FAN_PWM1 1K_4
3,5,11,13,14 LPC_AD0
3,5,11,13,14 LPC_AD1
3,5,11,13,14 LPC_AD2
3,5,11,13,14 LPC_AD3
3,5,11,13,14 LPC_FRAME#
1N4148
D33
R314
FAN_IO1
FAN_IO1
LPC_AD0
13
R315
10K_4
SMBus/I2C
R316
1
2
3
4
5
+V5_DUAL
3,4,5,6,10,11,17 SMB_CK
3,4,5,6,10,11,17 SMB_DAT
SYSTEM FAN W/FAN Control
+V12
4.7K
+V5_DUAL
+V5_DUAL
+V12
R374
LPC_AD1
LPC_AD2
LPC_AD3
CN22
1
2
3
4
5
C242
0.1U_4_Y _16V
1
2
3
4
5
+V5_DUAL
3,17 I2C_CK
3,17 I2C_DAT
CON5/2mm
JST_1X5_2MM
CN23
1
2
3
4
5
C243
0.1U_4_Y _16V
CON5/2mm
JST_1X5_2MM
1K_4
R320 G
FAN2
FDN335N
E
1K_4
2
1
3
2
1
Q18
FAN_IO2
GPI0~3/GPO0~3
+V5
13
R319
3
3
3
3
10K_4
1
3
5
7
9
GPI0
GPI1
GPI2
GPI3
CN24
2
4
6
8
10
GPO0
GPO1
GPO2
GPO3
3
3
3
3
HEADER_2X5_2.54
B
+V5
FAN3
FDN335N
C263
0.1U_4_Y _16V
FAN_IO2
1K_4
2
1
3
2
1
C261
Q23
2N3906_SOT23_3
1N4148
R407
D35
4.7K
C
D
R410 G
S
1K_4
1K_4
10UF_1210_16V
COMExpress
R318
+V12
DET
VCC
GND
3 FAN_PWMOUT
4.7K
R412
C245
0.1U_4_Y _16V
+V12
SYSTEM FAN2 W/FAN Control
R411
C244
Q22
2N3906_SOT23_3
1N4148
R317
D34
4.7K
C
Q13
S
FAN_PWM2
DET
VCC
GND
13
1K_4
E
D
R402
B
+V5
C262
10UF_1210_16V
0.1U_4_Y _16V
R409
C264
0.1U_4_Y _16V
FAN_TACHOIN 3
R408
10K_4
+V5
R321
Buzzer
33_4
+V5S_BUZZER
C246
0.1U_4_Y _16V
1
2
+V3.3
HDD LED
SP1
SATG1205NP45_DIP12X10_6.5
R322
4.7K
R323
4.7K
D17
HDD_LED#
K1
LED1
1
C
11,21 HDD_LED#
Q14
2N3904_SOT23
3,21 ATA_ACT#
K2
3
C
2
C
A
R324
470_6_5% +V5
IEI ELECTRONICS INC.
LEDRED_8_2
3,18,21
SPKR
2
2.7K_4
E
1
R325
B
BAW56LT1_SOT23
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
RTC/FAN/BIOS2/BUZZER
Size
Document Number
Date:
Monday , September 15, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
20
of
23
ATX Power Connector
+V5SB
-V12
+V3.3
+V5 +V3.3
+V5
+V5SB +V12
Frount Panel
+V5
ATX CONNECTOR
PWR1
ATX_PSON#
R327
11
12
13
14
15
16
17
18
19
20
0R
JP10(1-2)
MINIJUMPER_1X2_2
JP10
1
3
5
PS_ON#
2
4
6
ATX_PSON#
3V32
3V33
GND
5V3
GND
5V4
GND
PW-OK
5VSB
12V
1
2
3
4
5
6
7
8
9
10
R328
4.7K
PWROK_ATX
+V5
3
+V5_DUAL +V5
1
R329
220_4
R331
330_4
R398
220_4
10UF_1210_16V +V5
+V3.3
2
EC15
470U_SMD8_EC_16V
EC13
100U_SMD6_3_EC_25V
2
PWR2
ATX4P
EC16
470U_SMD8_EC_16V
+V12
PANSWIN
12V 4
GND
1
3
GND
2
F_PANEL1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
C256
R330
22_4
--PWR_LED+| 1
|
| 3
PWR_LED-|
| 5
|
| 7
PWR_BTN+
|
PWR_BTN-| 9
|
HDD_LED+| 11
|
HDD_LED| 13
---
--2 |
|
4 |
|
6 |
|
8 |
|
10 |
|
12 |
|
14 |
---
SPKR+
X
X
SPKRX
RESET+
RESET-
SPKR
3,18,20
SYS_RESET#
C247
12V
HEADER_2X7_2.54
PW_ATX4
TH_CON_ATX4P
470P_4_X_50V
2
10UF_1210_16V
2
1
+V12
1
1
1
+V12
C257
2
+V12
+V5
ATX-NOPOST_CNTR_2X10
HEADER_2X3_2
D18
11,20 HDD_LED#
K1
1
3
2
1
2
SW2
2
RESET BUTTON
3
1
K1
SIO_WDT#
R337
2
BAT54A_SOT23
D20
K2
C
2
BAW56LT1_SOT23
F_PANEL1(3-4)
@JUMP_1X2_2.54mm
PANSWIN
PANSWIN
1
4.7K_4
1
+V5
3
2
2
POWER BUTTON
R336
100K_4
C248
0.1U_4_Y_16V
WDT
R334
220_4
2
2
13
13
1
C
3 SY S_RESET#
1
K2
K2
1
1
1
D19
+V5_DUAL
R333 SW1
4.7K_4
1
2
R332
4.7K_4
R335
4.7K_4
Power Button/Reset Button
3,20 ATA_ACT#
2
+V5
+V5
2
+V5
C
3
1
K1
POWER LED(For Debug Use)
BAT54A_SOT23
+V12
D21
MST_DO241AA
1
1
C250
0.1U_4_Y _16V
C251
10U_8_X_6V3
C
C249
470_6_5%
R339
LEDRED_8_2
LED2
2
2
Q17
2N3904_SOT23
E
470_6_5%
R340
LEDGREEN_8_2
LED3
470_6_5%
R341
LEDGREEN_8_2
LED4
LEDRED_8_2
LED5
4.7U_8_Y _16V
+V5_DUAL -> +V3.3_DUAL@1A
+V5_DUAL
U29
4
+V3.3_DUAL
I
O
G
C252
0.1u_S4_Y _16
R346
60.4_S4_1
IEI ELECTRONICS INC.
2
+V3.3_DUAL
AMS1117-ADJ
R347
100_S4_1
1
R345
1K_4
2
E
2
B
+V5_DUAL
D
Q16
2N3904_SOT23
C
B
+V5
A
D22
MST_DO241AA
A
Q15
AOD452_TO252_3
1
1
G
C
1
S
R344
1K_4
1
R342
6.19K_6_1%
+V3.3_DUAL
A
470_6_5%
R338
2
2
R343
4.7K_4
+V5_DUAL
+V5SB,+5V -> +V5A@10A
C
+V5SB
A
+V5
C
+V12
C
+V5_DUAL
2
+V5
1
13
3V31
-12V
GND
PS-ON
GND
GND
GND
-5V
5V1
5V2
1
R326
4.7K
C253
C254
10U_8_X_6V3 0.1u_S4_Y _16
Title
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
ATX Power Connector
Size
Document Number
Date:
Monday , September 15, 2008
Rev
1.02
F119 ICE-DB-9S-R10
Sheet
21
of
23
Express Card Module
COM Module
H4
H5
1
SCREW1
H6
1
1
E_Card_CON1_Bracket
E_Card_CON1(H1)
@D=3.00mm
ROUND HEAD MACHINE SCREW
D=3.00mm
D=3.00mm
H8
D=3.00mm
H9
1
H10
E_Card_CON1(H2)
1
1
ROUND HEAD MACHINE SCREW
D=3.00mm
@D=3.00mm
D=3.00mm
7
8
3
4
IO_GND
IO_GND
7
8
HOLE
7
8
3
4
3
4
7
8
HOLE
HOLE
H141
6
2 9
5
H131
6
2 9
5
H121
6
2 9
5
H111
6
2 9
5
ATX
3
4
Express Card Bracket
PCB1
HOLE
H191
6
7
8
7
8
3
4
HOLE
7
8
2 9
5
2 9
5
IO_GND
IO_GND
3
4
HOLE
NANO MODULE
HOLE
3
4
H181
6
2 9
5
HOLE
7
8
H171
6
COMPACT MODULE
3
4
IO_GND
EXTENDED MODULE
7
8
H161
IO_GND6
2 9
6
5
H151
2 9
5
BASIC MODULE
3
4
HOLE
PCB_F119V101
IEI ELECTRONICS INC.
Title
Size
NO. 29, Chung-Shing Rd.,
Shin-Chi City , Taipei Hsien. Taiwan, R.O.C
TEL:886-2-86916798
FAX:886-2-66160030
Miscellaneous
Document Number
Rev
1.02
F119 ICE-DB-9S-R10
Date:
Sunday , September 14, 2008
Sheet
22
of
23