Review
総 説
Novel Technology for Digital Controlled UPS Inverter
Lipei Huang* Yadong Liu** Meng Wang***
*Dept. of Electrical Engineering, Tsinghua University, Beijing 100084, China Philips
Research Asia-Shanghai, Lane 888, Tianlin Road, Shanghai 200233, China **
***School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853, U.S.A
Abstract
A novel digital PID control scheme for UPS inverter based on digital signal processing (DSP) is proposed in this
paper. The capacitor current of output filter comes from the differential of the measurement of output voltage.
Thus, a quasi double loop control is achieved. The analysis on dead time effect allows us to propose its compensation method to weaken the effect and reduce the total harmonic distortion (THD) in the output voltage in steady
state. Experimental results show that the quasi double loop control with dead time compensation is effective.
Moreover, to limit the output voltage distortion and improve the performance of UPS inverters, a novel robust
deadbeat control method is proposed in this paper to deal with the problem. In this control method, a proportional element is added to the traditional deadbeat control in order to improve the robustness to parametric imprecision. Experimental results show that the robustness for parametric variation of the proposed method is much
better than the traditional deadbeat control. This method has also very good static performance under linear
load or nonlinear load compared with digital PID control. Therefore, this novel technology is easy to be realized
in DSP and suitable for full digital realization of UPS.
Key words : UPS inverter; Deadbeat control; Robustness
1 Introduction
Conventionally, the controllers of UPS inverter
were usually designed by frequency-domain-based
UPS has been widely used in the fields of commu-
analog control scheme. Compared with the analog
nication, networks, medical treatment, etc, feeding
implementation, digital control based on micropro-
various critical loads such as communication device,
cessor has many advantages such as no aging effect,
computer server, and life support system. Low total
avoiding temperature drift, and easy adjustment of
harmonic distortion (THD) in the output voltage of
control parameters. 2
)
UPS inverter under various loads and fast dynamic
In this paper, a novel digital control scheme was
response in presence of unknown distorting load are
proposed. It has two features : (1) neither the output-
1)
the main requirement for high-performance UPS. It
filtering capacitor current nor inductor current is
is worth noting that maintaining low distortion wave-
sensed ; instead, the capacitor current needed by in-
form under rectifier load is especially important in
ternal loop is from the differential of the output volt-
order to ensure that the usual loads, computers, and
age and (2) a dead time compensation method is pro-
communication devices work well.
posed to improve the performance in steady state.
© 2009 GS Yuasa Corporation, All rights reserved.
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GS Yuasa Technical Report
2009 年 6 月 第 6 巻 第 1 号
To limit the output voltage distortion and improve
modulation stage can be considered as an approxi-
the performance of UPS inverters, various digital
mate proportional element, since the switching fre-
control methods have been proposed
2- 4)
, such as re-
quency is much higher than the bandwidth of control
petitive control, deadbeat control, and sliding mode
system, and most of high frequency component will
control.
be absorbed by output filter. Then the modeling of
Deadbeat control, which originated from state
main circuit part of inverter can be shown as Fig. 2.
equations, has very fast dynamic response and can
u x is the calculation result of digital signal processing
4)
(DSP) controller acting as reference wave in PWM
eliminate voltage variation in several control periods.
However, stability of deadbeat control is poor espe-
modulation stage. <u in> is the average value of u in in
cially when the inverter feeds no load ; robustness
a control period (half of switching period in this pa-
is poor, that is, the control performance is sensitive
per).
to parameters of output filter. A robust deadbeat
3 Digital control scheme
control method is proposed to solve this problem.
This method adds a proportional element to the tra-
3.1 Quasi double control
ditional deadbeat control and can effectively improve
the robustness of deadbeat control with the expense
Multi- loop control has been researched in some
of little increased static error and slower dynamic
papers.2 In these control schemes, in addition to out-
response.
put voltage feedback loop, output filtering capacitor
)
current or inductor current is also sensed to consti-
2 Structure of digital controlled UPS inverter
tute a faster internal feedback loop. This sensing is
conducive to widen the bandwidth of control system
and improve the dynamic response of inverter.
An UPS inverter is usually a voltage source
According to Fig. 1, it holds :
SPWM inverter in series with output filter. Take the
du o
i c = C dt half bridge inverter with IGBT switches as example,
as shown in Fig. 1. The output filter consists of an
(1)
inductor and a capacitor with equivalent series re-
Equation 1 shows that the capacitor current can
sistance (ESR) r L and r C, respectively. In approximate
be got by differentiating the output voltage. Noting
analysis, the two ESR can be assumed to be zero.
that differential element can be easily got using back-
The inverter is a nonlinear system due to the ex-
ward Euler method or Trapezoidal Rule in DSP, the
istence of power switches. Fortunately, the SPWM
current sensor for capacitor current can be saved.
Then quasi double loop control can be got as shown
in Fig. 3.
Ud
VT
Ug1 1
DC
link
D1
rL
Ud
Ug2
VT2
iL
L
iC
uin
D2
Gv(s), Gi(s), and Gh(s) are voltage controller, current
Main circuit
controller, and zero order hold element, respectively.
io
rC
C
Load
io
SPWM
modulation
uo
ux
km
<uin>+
-
1 iL
sL +
ic
1
sC
uo
DSP
Fig. 1 Equivalent circuit of a half bridge UPS inverter.
Fig. 2 Modeling of main circuit of UPS inverter.
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GS Yuasa Technical Report
2009 年 6 月 第 6 巻 第 1 号
io
kf
ur
Gh(s)
+uerr
-
Gv(s)
++
ux
Gi(s)
+-
km
+
-
1
sL
udead
Main
circuit
iL - i c 1 uo
sC
+
iL is negtive
Udead
t
-Udead
kd
s
Gh(s)
iL is positive
kfu
Fig. 4 Disturbance voltage equivalent to dead time
effect.
Fig. 3 Block diagram of quasi double loop control
system.
udead
It holds :
-T s
T
G h(s ) = 1 − e ∼
∼ s
s
0.5T ss +1
s
kf
(2)
ur
Gh(s)
+ uerr
- Gv(s)
where T s is the sampling period.
After Gh(s) is linearized, the standard design ap-
Main
circuit
- ux
+ +
ic
+ + 1 iL
+
1
km
Gi(s)
+
sL
+ +
- sC
Gio(s)
kd
io
s
Kdrad
Gh(s)
proaches such as Bode plot approach can be used
to design the controllers Gv(s) and Gi(s). Then all the
uo
kfu
Fig. 5 Control diagram with dead time compensation and output current compensation.
control parts should be discretized. In ref. 5 there is
a comparison of several discretization methods for
the application of switchmode power converters. The
D2 provides current until VT1 turns on. So dead time
conclusion is that backward Euler method is the best
between (0, 1) to (1, 0) prolongs negative time of u in.
one in terms of performance. Also backward Euler
If i L is negative:
method is very simple, and s- domain function can
To switch (0,1) to (1,0), diode D1 provides current
be transferred to a z-domain by replacing“s”with
1 −z 1 ”
“ . Thus, its method is chosen to all the con-
immediately once VT2 turns off, which is equivalent
to on-state of VT1. So dead time between switch (0,1)
TS
to (1,0) does not affect u in.
trol parts including dead time compensation and out-
To switch (1,0) to (0,1), diode D2 provides current
put current compensation as described below.
kf is a feed-forward control element, which is con-
until VT1 turns on. So dead time between switch (1, 0)
to (0, 1) prolongs positive time of u in.
ducive to decrease static error.
Combine the two situations and suppose i L is an
3.2 Dead time compensation
Referring to Fig. 1, specify that“1”denotes on-
approximate sine wave with power frequency when
state and“0”denotes off - state. Then state ( 1, 0 )
load is heavy enough, dead time effect is equivalent
denotes that VT1 is on and VT2 is off, and other situ-
to a square wave disturbance to u in according to
ation is analogic. In each switching period there is
principle of area equivalence. The square wave is as
two switches: one is (1,0) to (0,1), and the other is (0,1)
shown in Fig. 4.
to (1,0). Analyze the effect of dead time in two situa-
It holds:
tions.
U dead = 2U dT df switch
If i L is positive:
As far as switch (1,0) to (0,1) is concerned, diode
(3)
where T d is dead time, f switch is switching frequency.
D2 provides current immediately once VT1 turns off,
Feedforward compensation based on disturbance
which is equivalent to on-state of VT2. So dead time
is available to weaken the dead time effect as shown
between switch (1,0) to (0,1) does not affect u in.
in Fig. 5.
As far as switch (0,1) to (1,0) is concerned, diode
If k dead = 1/k m holds, the effect on u o of the distur-
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GS Yuasa Technical Report
2009 年 6 月 第 6 巻 第 1 号
pulse width ΔT (k ) can be computed by making u o(k
bance u dead will be eliminated.
+ 1) in the first equation in 6 equal to the voltage ref-
Note that when an inverter feeds light load or no
erence u ref (k + 1). It holds
load, i L can not be considered as a sine wave with
power frequency, but a wave with switching fre-
ΔT (k ) =
quency, then the dead time effect can be neglected.
1
Ψ
u (k + 1) - 11 u o (k ) g1 ref
g1
Ψ 12
Then, the dead time compensation should be enabled
g1
only if the load is heavy. In this situation, inductor
iL (k ) -
P1
g1
i o (k) -
h1
(11)
g1
current i L is similar to load current i o. So it is reason-
Deadbeat control depends on the precise mathe-
able to decide the sign of u dead according to the sign
matical models of controlled object. Ideally the actual
of i o in this paper.
parameters of the inverter should be identical with
A single phase UPS inverter is implemented using
calculating parameters used in equation11. However,
the proposed control scheme. Experimental results
the precise systemic model is difficult to be obtained;
of the inverter under rated resistive load show that
moreover, the actual parameters may change during
THD of u o is 2.94% when the dead time compensa-
operation.
tion is disabled, while THD of u o is 2.64% when its
A typical UPS inverter main circuit is considered
compensation is enabled. Thus, the proposed dead
to study the influence of parametric mismatching.
time compensation is effective.
Fig. 6 (a) shows the discrete system block diagram
of traditional deadbeat control. Symbols with“^”
4 Robust deadbeat control
stand for calculating values and symbols without“^”
stand for actual values. The poor robustness makes
In the circuit of a single-phase half-bridge UPS
it almost impracticable in UPS application. The pro-
inverter (Fig. 1). If ESR of capacitor is neglected, the
posed deadbeat control is shown in Fig. 6 (b). The
capacitor voltage u c equals to the output voltage u o.
difference between two types of control methods is a
u o and the inductance current i L are chosen as state
proportional element k w added to the new proposal,
variables, and the load current i o is treated as disturbance. The system state equation is
・
x = A ･ x + B ・u in + D ・i o
(4)
y = C ・x
(5)
r
Io(z)
CTP̂
CTĜ
Uref(z)
T
T
where x =［u o i L］
, A =［0 1/C ; -1/L 0］
, , B =［0 1/L ］
,
+
T
T
D =［-1/C 0］
, C =［1 0］
+
ΔT(z)
CTĤ CTĜ
-
u in is input voltage of LC filter (that is output voltage
of inverter bridge) and is either +U d or -U d in the
Φ= e
=［Ψ 11 Ψ 12 ; Ψ 21 Ψ 22］
T
P = -A 1(I - e AT ) D =［p 1 p 2］
-1
H = U dA (I - e
AT
(6)
) B =［h 1 h 2］
C P̂
CTĜ
Uref(z)
(7)
+
(9)
T
Φ
Io(z)
(8)
T
G = 2U d e(AT /2) B =［g1 g2］
X(z)
T
where
T
H
1/z
(a) Traditional deadbeat control
The discrete state equation can be expressed as
AT
G
+ +
++ +
CTΦ̂
two level patterns.
x (k + 1) = Φx (k ) + GΔT (k ) + Pi o(k ) + H
P
-
1/(CTĜ )
1/(CTĜ )
-
KW
+ ΔT(z)
CTĤ CTĜ
P
G
H
+ +
+ +
1/z
X(z)
Φ
CTΦ̂
(10)
(b) Proposed deadbeat control
where T is the control period, ΔT (k ) is the acting
time of positive voltage +U d in the k th control period.
Fig. 6 Discrete system block diagram of deadbeat control for UPS inverter.
In the traditional deadbeat control, the required
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GS Yuasa Technical Report
2009 年 6 月 第 6 巻 第 1 号
^
where usually 0 < k w < 1 and disappears if k w = 1.
ter deviate from the calculating parameters ( L =
^
The transfer function from U ref(z) to X (z) in Fig. 6
1.3 mH, C = 20 μF). L changes from 0.5 to 2.0 mH
^
(b) is
( 38.5 - 153.8% L ) , and C changes from 10 to 30μF
^
^
^
X (z)
CTG
=［
(zI - Φ) + GCTΦ］-1G
U ref(z)
kw
( 50 - 150%C ) . The prototype still has good perfor-
(12)
mance when the deviation is within a certain range.
The RMS value deviation of voltage is less than 2%
The transfer function from voltage reference to out-
under rated load and less than 4% under no load, and
put voltage is
the THD of voltage is less than 1.5%. Only when both
T^
C G
^ -1
U (z)
C TX (z)
(zI -Φ)+G CT Φ］
G i(z) = o
=
= CT[
G
U ref(z)
U ref(z)
kw
k (g z + g2Ψ 12 - g1Ψ 2)
(13)
= w 1
q (z)
L and C are reduced to 38.5%L (0.5 mH) and 50%
where
proposed robust deadbeat control and the digital
^
^
^
^
^
(30 μF), respectively, the system becomes unstable.
Table 3 shows performance comparison of the
^
q (z) = g 1z +［g1Ψ11k w + g2Ψ12k w - g1Ψ22 - g1Ψ11］z +
2
^
^
^
PID control. The prototype has desirable static per-
^
g2k w(Ψ11Ψ 12 - Ψ 11Ψ12) + Ψ 21(g1Ψ12k w - g 1Ψ 12) +
^
formance under different kinds of load. Besides, load
^
Ψ 22 (g 1Ψ 11 - g1Ψ11k w)
change also causes little disturbance to the output
If k w = 1, and the calculating values and the actual
voltage during dynamic process. Moreover, experi-
values are the same, equation 10 can be simplified as
mental results prove that the system can remain
G (z) = 1/z
stable when actual parameters deviate from calcu-
(14)
lating parameters. Thus, with the proposed control
It means that with the traditional deadbeat control,
method, the inverter has both small static error and
the output voltage follows the reference in one control period in case that there is no parametric misTable 2 Static performance with parametric deviation for proposed robust deadbeat control method.
match.
Table 1 lists the constraints for actual parameters
Output filter
L / mH C / μF
2.0
30
1.5
30
1.0
30
0.5
30
2.0
20
1.5
20
1.0
20
0.5
20
10
2.0
10
1.5
10
1.0
10
0.5
in traditional and proposed deadbeat control to make
the system stable. It is obvious that constraints in
the proposed method are much loose, and the control
method is robust when actual parameters deviate
from calculating parameters.
5 Experimental results
Experiments using the proposed robust deadbeat
control method were carried out on a half-bridge in-
Rated load
No load
THD / % U o / V
100.3 1.09
101.5
100.0 1.11
102.1
100.5 1.12
102.4
100.9 1.19
102.9
100.3 1.10
102.3
100.5 1.10
101.4
100.6 1.13
101.8
101.0 1.30
103.3
100.1 1.12
101.5
101.2 1.15
101.9
101.4 1.27
103.1
Unstable
Uo / V
THD / %
1.07
1.07
1.07
1.20
1.05
1.11
1.13
1.34
1.14
1.17
1.30
verter system.
Table 2 shows the static performance of the output
Table 3 Performance comparison of the robust
deadbeat control and the digital PID control.
voltage when the actual parameters of output fil-
THD of output voltage
under no load / %
THD of output voltage
under rated load / %
THD of output voltage
under rectifier load / %
Voltage regulation of
output voltage / %
Sampling frequency / kHz
Table 1 Constraints for systemic parameters in deadbeat.
Parameters L / mH
C / μF
Ud / V
Constraints
^
^
^
＿L
＿C
＞
＿U ｄ
＞
Traditional deadbeat ＞
^
^
^
Proposed deadbeat >70.23%L >49.1%C <146.94%Uｄ
(k w = 0.7)
5
Proposed robust Digital PID
deadbeat control control
1.57
2.51
1.56
2.64
2.82
3.8
2.19
6.75
17.24
34.48
GS Yuasa Technical Report
2009 年 6 月 第 6 巻 第 1 号
fast dynamic response and is robust for parametric
experimental results on this method prove that it
deviation.
greatly improves the robustness of deadbeat control
and has good steady state performance.
6 Conclusion
References
A novel digital control scheme for UPS inverter
has been proposed. The quasi double loop control
1) Liviu Mihalache, Proc . IEEE APEC , p. 590-596 (2002).
with dead-band compensation can make inverter
2) Ying-Yu Tzou, IEEE PESC , 1, 138-144 (1995).
working stable with small output filter. A novel dead-
3) Kai Zhang, Yong Kang, Jian Xiong, and Jian Chen,
beat control method for UPS converters was also
IEEE Transactions on Power Electronics , 18(3),
proposed to improve the performance of UPS invert-
784-792 (2003).
4) Chihchiang Hua, IEEE Transactions on Power Elec-
ers. A proportional element is added in this method
tronics , 10(3), 310-317 (1995).
to improve the robustness to systemic parameters.
5) Duan Y and Jin H, IEEE APEC , 2, 14-18 (1999).
The method does not require much computation and
can be easily realized in DSP. Systemic analysis and
6