International Journal of
Applied Mathematics,
Electronics and Computers
ISSN: 2147-82282147-6799
Advanced Technology and Science
http://ijamec.atscience.org
Original Research Paper
Comparison of Three, Five and Seven Levels Diode Clamped Multilevel
Inverter Topologies based Shunt Hybrid Active Power Filter for
Harmonics Compensation with Equal DC Link
Tugce Demirdelen *1, Mustafa Inci 2, Mehmet Tumay 3
Accepted 10th August 2015
DOI: 10.18100/ijamec.83268
Abstract: The multilevel inverter is coming out as a new type of power inverter choice for high power applications. This type of inverter
can constitute high voltage and decrease harmonics by its own circuit topology. This paper presents comparison of three, five and seven
levels diode clamped multilevel inverter (DCMLI) topologies based shunt hybrid active power filter for harmonics mitigation of the
nonlinear loads. The compensation process is based on synchronous reference frame method. Theoretical analyses and simulation results
are obtained from an actual industrial network model in PSCAD. The simulation results are presented for a proposed system in order to
demonstrate that the harmonic compensation performance meets the IEEE-519 standard.
Keywords: Harmonic compensation, high power applications, hybrid active power filter, multilevel inverter, power quality
1. Introduction
Recently, higher power apparatus have started to be used in
industrial applications. Many medium voltage motor drives
demand medium voltage and megawatt power level. Connecting
only one power semiconductor switch is difficult directly to
megawatt power grids. Due to this condition, multilevel power
converters are to be used as an alternative solution in medium and
high voltage applications. Multilevel converters have the ability
to increase the output voltage without rising the voltage rating of
switching components. Thus, they are preferred to connect to
medium voltage grids without using transformers. Multilevel
converters have more advantages than conventional two level
converters. Some attractive features are;

Generate output voltages with very low distortion

Reduce the dv/dt stresses

Reduce the electromagnetic compatibility problems

Generate low common mode voltage

Draw input current with low distortion
In power transmission/distribution systems, the proliferation of
nonlinear loads cause several power quality problems. The grid
voltage and currents are distorted non sinusoidal form due to
these types of loads. In order to reduce the current harmonic
pollution, passive filter is one of the traditional solution
ineffectively. As another of the key technologies in combating
power grid pollution and improving the power quality, active
power filter has become a new research emphasis in power
electronics technology. Hybrid active power filters effectively
smooth the problems of the passive filter and an active power
filter solution with ensuring cost effective harmonic
compensation. To ameliorate the performance of the hybrid
active power filters, numerous control methods such as pq theory
_______________________________________________________________________________________________________________________________________________________________
1
Cukurova University Department of Electrical and Electronics
Engineering Adana, TURKEY
* Corresponding Author: Email: tdemirdelen@cu.edu.tr
Note: This paper has been presented at the International Conference on
Advanced Technology&Sciences (ICAT’15) held in Antalya (Turkey),
August 04-07, 2015
This journal is © Advanced Technology & Science 2013
[1-3], fast fourier transform [3], dq theory [4-5], fuzzy controller
[6-7] etc. have been applied in literature.
Several hybrid APF (HAPF) topologies constitute active and
passive parts in series and/or parallel have been proposed in [810]. Between these HAPF topologies, active power filter
connected in series with shunt passive filter (Shunt HAPF) [1-7,
11-18] has been proposed, implemented for harmonic and
reactive power compensation. Most of articles are obtained for
low voltage level. On the contrary, Multilevel SHAPF [19-21] is
the most used in medium voltage levels in industrial applications.
This paper presents analysis of the current THD and comparison
of different levels diode clamped multilevel inverter topologies
for shunt hybrid active power filter. The main aim of this paper is
to observe and minimize the source-side current THD values by
applying different voltage level multilevel inverters in SHAPF.
Theoretical analyses and simulation results are obtained from an
actual industrial network model in PSCAD. The simulation
results are presented for a proposed system in order to
demonstrate that the harmonic compensation performance meets
the IEEE-519 standard.
2. Review of Multilevel Inverters
There are numerous multilevel inverter topologies in literature.
Diode clamped inverter [22-23] is the most popular and the most
commonly used multilevel topology in industrial applications.
The structure of capacitor clamped inverter [24-25] is nearly
same as diode clamped inverter except that instead of using
clamping diodes, the inverter uses capacitors in their place.
Cascaded multilevel inverters [26-27] include series H bridge
inverters. Cascaded inverters have structurally no problem of dclink voltage unbalancing but have a problem to require many
separated dc sources in the motor drive applications [27]. Table 1
shows the comparison of power component for the main
multilevel inverter topologies.
Besides three common multilevel inverter topologies, different
multilevel inverter topologies are seen in the literature. These are
generalized multilevel inverters [28], soft switching multilevel
inverters [29], hybrid multilevel inverters [30] and back to back
IJAMEC, 2016, 4(1), 24-30 | 24
diode clamped multilevel inverters [31]. The generalized
multilevel converter achieves to stabilize each voltage level by
itself regardless of inverter control and load characteristics.
Hybrid Multilevel Inverter uses the three-level diode-clamped
converter. Conventional cascaded H-bridge multilevel converter
needs four separate dc link capacitors for one phase leg and
twelve separate dc link capacitors for a three phase converter.
When a five level converter replaces the full bridge cell, the
voltage level is increased doubled for each cell. For nine voltage
levels, the converter requires only two separate dc link capacitors
for one phase leg and six separate dc link capacitors for a three
phase converter. This configuration is called hybrid multilevel
converter topology. This topology can achieve higher voltage
level with less separate dc link capacitors. The control of this
topology is more complex compared with other topologies. Softswitching can be implemented for different multilevel converters
such as diode-clamped, capacitor-clamped, cascaded multilevel
inverters to decrease the switching loss and redound efficacy. A
balancing scheme based on the application of redundant vectors
is therefore required in addition to the natural balancing offered
by the back-to-back connection [32]. Figure 1 shows the
different multilevel topologies.
Diode-Clamped 5-Level
(a)
Table 1. Comparison for Power Component
Inverter
Configuration
Main switching
devices
Main diodes
Clamping
Diodes
DC bus
capacitor
Balancing
Capacitors
Diode
Clamped
Flying
Capacitor
Cascaded
Inverter
2(m-1)
2(m-1)
2(m-1)
2(m-1)
2(m-1)
2(m-1)
(m-1)(m-2)
0
0
(m-1)
(m-1)
(m-1)/2
0
(m-1) (m-2)/2
0
Three major modulation techniques are seen in the literature for
multilevel inverters. The most popular method is carrier based
PWM modulation [33-34]. This method is based on the
comparison of reference signal with carrier signals. The
controller of this modulation method is simple and effective. For
“m” level inverter, (m-1) triangular carriers are needed. The other
method is space vector modulation [35]. The main principle of
this method is to control the inverter output voltages. Thus, the
Parks representation will be nearly equals the reference voltage
vector. Space vector modulation techniques can be implemented
to all multilevel topologies. The advantages of this method are
good utilization of dc link voltage, low current ripple, easy
implementation to DSP, suitable for high voltage high power
applications. The last technique is the selective harmonic
elimination. This technique is pre calculated. In this method, the
basic square wave output is “chopped” a number of times, which
are obtained by proper offline calculations [36].
Different types of control methods are available for the multilevel
inverters in literature. These are direct torque control [37],
capacitor balancing technique [38], linear control [39], predictive
control [40]. In order to increase the efficiency of the multilevel
inverter, these control methods are improved day by day.
25 | IJAMEC, 2016, 4(1), 24-30
Capacitor-Clamped 5-Level
(b)
This journal is © Advanced Technology & Science 2013
a
Soft-Switch Multilevel Inverter
b
(e)
Cascaded
(c)
2 Level
3 Level
4 Level
Hybrid Multilevel inverter
using three level NPC
5 Level
(f)
Generalized Multilevel Inverter
N Level
(d)
Back-to-Back Diode Clamped Multilevel Inverter
(g)
This journal is © Advanced Technology & Science 2013
IJAMEC, 2016, 4(1), 24-30 | 26
Figure 1. Multilevel Inverter Topologies
Ibg
Ea
C
Icg
Eb
Ib
Lac
Ic
Lac
Line Voltage
Line frequency
Supply inductance
(Ls)
Rectifier inductance
(Ll)
Filter Capacitor
(CF)
Filter Inductance
(LF)
Tuned freq. of
series filter (ftuned)
50 Hz
1 mH
0.6 mH
16 µF
Linear Load
R
L
Ifc
Ifa
Lf
Lf
Lf
Cf
Cf
Cf
Passive Filter
Diode Clamped
Multilevel
Inverter
Topologies
Five Level
Seven Level
SHAPF
(a)
Phase Locked Loop
αβ/DQ
𝒘𝒐
+
+
𝑬𝒂
αβ/DQ
𝑬𝜷
𝑬𝒅 𝒌𝒑 + 𝒌𝒊
𝑬𝒒
Simulation Step Time
25 mH
250 Hz
DC Link Gain (K)
Harmonic Voltage
Reference gain K1
100
Ω
600
mH
13
mH
10
kHz
20
µs
1
750
𝜽𝒑
𝒘
Harmonics Compensation Reference Current
𝜽𝒑
Iag
Ibg
Icg
Id
Id,lpf
-
Σ
3Ф/DQ
Iq,lpf
Iq
𝜽𝒑
+Id,ref
Σ
Iq,ref
-+
𝒌𝒑 + 𝒌𝒊
DQ/3Ф
DC Link Control
0
Load
Resistances(Rload1 )
Load
Inductances(Lload1)
Load
Inductances(Lac1)
Switching frequency
(fswitching)
Nonlinear Load
Three Level
Table 2. Simulation Parameters
6.3 kV
Cl Rl
Ec
Grid
4. Simulation Results of the Multilevel Converters
based SHAPF
The simulation studies are carried out using PSCAD/EMTDC.
The main purpose of the simulation is to evaluate the effect of
different level diode clamped multilevel topology to consider
THD value of source current in power system. The performance
results of diode clamped multilevel converter topologies at
different voltage levels (3,5 and 7 levels) are compared.
Parameters used in simulations are given in Table 2. In
simulation, the nominal frequency of the power grid is 50 Hz and
the harmonic current source is generated by the three phase diode
rectifier. The phase to the phase grid voltage is 6.3 kV. The
passive filters are tuned at 250 Hz and the control signals of
IGBTs are generated through the pulse width modulation
generator whose amplitude and frequency of carrier wave are ± 1
and 10 kHz, respectively.
B
Ll
Lac
Ia
APF
Figure 2 shows the proposed Multilevel SHAPF system and
controller block diagram, in which it consists of three main
control block; These are harmonic compensation, dc link voltage
controller and final reference compensation current- pwm control
block. The harmonic control of Multilevel SHAPF is shown in
Figure 2 (b). The first step is to isolate the harmonic components
from the fundamental component of the grid currents. This is
achieved through dq transformation using the phase angle which
is get from PLL, synchronized with the PCC voltage vector, and a
first order low pass filter with cut off frequency of 10 Hz. Then
the dq inverse transformation produces the harmonic currents in
abc referential frame. The DC link control of Multilevel SHAPF
is shown in Figure 2 (b). By using the error signal generated by
the conventional PI controller, the dq inverse transformation
produces the reference DC link control signals in the abc
referential frame. A limiter is also applied to avoid the overflow
problem of the controller. DC link is controlled by the reactive
component of the error signal. Thus, only the q component is
used for dq inverse transformation. The final reference current
consists of three phase harmonic reference current signals and dc
link control signals. The reference signal (In_harmonic_ref + Vcappi_n)
is generated using these signals together. Then, the reference
signals are compared with carrier signal to generate switching
signals shown in Figure 2 (b).
Iag
Ifb
3. Proposed System and Controller
A LS
Vdc
- Σ
+
𝜽𝒑
d
DQ/3Ф
𝒌𝒑 + 𝒌𝒊
Ia_harmonic_ref
Ib_harmonic_ref
Ic_harmonic_ref
q
Vcappi_a
Vcappi_b
Vcappi_c
Limiter
Vdc_ref
Pulse Width Modulation
(n=a,b,c)
In_harmonic_ref
Σ
Reference
PWM
Gate
Signals
Vcappi_n
Switching
Signals
Carrier
(b)
Figure 2. Multilevel Inverter Based SHAPF a)Topology b)Control Block
Diagram
27 | IJAMEC, 2016, 4(1), 24-30
This journal is © Advanced Technology & Science 2013
Source Voltages (kV)
Ea
6.0
4.0
Eb
DC Link Voltage (kV)
Vcap
Ec
1.50
1.40
1.30
1.20
1.10
1.00
0.90
2.0
0.0
-2.0
-4.0
-6.0
vc1
Ia
0.080
0.060
0.040
0.020
0.000
-0.020
-0.040
-0.060
-0.080
Ib
Load Currents (kA)
0.750
0.700
0.650
0.600
0.550
0.500
0.450
Ic
3 LEVEL
vc2
0.750
0.700
0.650
0.600
0.550
0.500
0.450
0.40
Ifa
0.040
Ifb
SHAPF Currents (kA)
Ifc
0.60
0.80
Time (s)
1.00
1.20
DC Link Voltage (kV)
Vcap
3 LEVEL
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.400
vc1
-0.050
Iag
0.050
Ibg
Source Currents (kA)
Icg
0.200
0.380
vc2
5 LEVEL
0.200
0.380
-0.050
1.00
5 LEVEL
0.040
0.030
0.020
0.010
0.000
-0.010
-0.020
-0.030
-0.040
0.050
Ifa
Ifb
1.10
Time (s)
SHAPF Currents (kA)
vc3
1.20
Ifc
0.200
0.400
vc4
0.200
0.40
Iag
Ibg
Source Currents (kA)
Icg
1.60
0.50
0.60
0.70
0.80
Time (s)
0.90
1.00
1.10
1.00
1.10
1.20
DC Link Voltage (kV)
Vcap
0.80
0.280
-0.050
0.120
7 LEVEL
1.00
0.040
0.030
0.020
0.010
0.000
-0.010
-0.020
-0.030
-0.040
0.050
Vc1
1.10
Time (s)
Ifa
Ifb SHAPF Currents (kA)
1.20
Ifc
0.260
Vc2
0.120
0.260
Vc3
7 LEVEL
0.120
0.260
Iag
Ibg Source Currents (kA)
Vc4
0.120
Icg
0.260
Vc5
0.120
0.280
Vc6
-0.050
1.00
1.10
Time (s)
1.20
0.120
0.40
0.50
0.60
0.70
0.80
Time (s)
0.90
1.20
Figure 3. Simulation Results
Figure 3 illustrates the three phase source voltages, the load
currents, the SHAPF currents, the source currents, DC link
voltages of Multilevel SHAPF with different voltage levels cases.
In the three level diode clamped multilevel inverter based SHAPF
simulation results, the dc link voltage is adjusted to 1.5 kV. The
THD value of load is nearly 28.5%. After the SHAPF
This journal is © Advanced Technology & Science 2013
IJAMEC, 2016, 4(1), 24-30 | 28
compensates the harmonics, the source side THD is nearly
2.65%. In the five level diode clamped multilevel inverter based
SHAPF simulation results, after the SHAPF compensates the
harmonics, the source side THD is nearly 2.30%. In the seven
level diode clamped multilevel inverter based SHAPF simulation
results, after the SHAPF compensates the harmonics, the source
side THD is nearly 1.9%.
The THD values for all different level multilevel inverters are
shown in Table 3. According to the simulation results, it can
reduce the source side current THD with increasing the level of
multilevel inverter structures.
[4]
[5]
Table 3. Individual Harmonic Distortion of the Load and Source
Currents
Harmoni
c Order
Load
THD
Source
THD 3
level
Source
THD 5
level
Source
THD 7
level
Harmoni
c Order
Load
THD
Source
THD 3
level
Source
THD 5
level
Source
THD 7
level
3
5
7
9
11
13
15
0.05
0
0.04
5
25.7
0
0.38
0
10.6
2
0.96
0
0.00
9
0.00
5
4.80
0
1.21
0
2.46
0
0.71
0
0.00
5
0.00
4
0.04
0
0.08
7
0.83
0
0.00
3
1.13
0
0.65
0
0.03
5
0.03
5
0.06
7
0.72
0
0.00
2
1.07
0
0.47
0
0.03
0
[6]
[7]
[8]
Total THD
(%)
28.5
17
19
21
23
25
2.15
0
1.12
0
1.24
0
0.60
0
0.04
0
0.11
0
1.18
0
0.55
0
0.83
0
0.48
0
0.87
0
0.48
0
0.02
5
0.43
0
0.40
0
2.30
0.78
0
0.24
5
0.02
4
0.01
6
0.32
0
1.9
2.65
5. Conclusion
Different level diode clamped multilevel inverter topologies are
applied for the three phase shunt hybrid active power filter. The
control scheme of the SHAPF is based on the synchronous
reference frame and is simpler and easier to implement. The
harmonic compensation is obtained by regulating directly the
currents of the power systems. The simulation results of the three
phase three wire SHAPF under the harmonics compensation are
illustrated to verify all discussion and analysis and also show the
effect of the level of multilevel topologies. According to the
simulation results, it can reduce the source side current THD with
increasing the level of multilevel inverter structures.
[9]
[10]
[11]
[12]
[13]
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