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Department of Electrical and Computer Engineering
Answer all Questions.
All Questions carry equal marks
Exam Duration 3 hour
Examiner: A.J. Al-Khalili
Note: No books, papers are allowed.
Hand held calculator is permitted.
In case of doubt as to the meaning of a question, clearly state any assumption you make.
All necessary constants and formulas are provided in Annex A
You may use the CMOSIS5 and the SPICE parameters provided in Annex B
===============================================================
1. Design a four stage pad driver to drive 200 pf load with 20 ns rise and fall time.
Calculate also: a) the approximate dynamic power dissipation at 10 Mhz; b) the
power bus width if the limiting value of current density is 1.5 mA/μm.
2. Design a 3 input CMOS static NAND gate for: a) minimum area; b) minimum
propagation delay; c) equal rise and fall time; d) determine the worst case rise and
fall time if the NAND gate is driving a 0.1 pf load.
3. Design a gate to implement the function F(A,B,C,D) = (AB + CD)’ in Pseudo
NMOS. Analyze the circuit for valid operation at logic high and logic low.
4. Design and implement a 4 input AND gate using Dynamic DOMINO logic.
Analyze your circuit from charge sharing point of view. Size your circuit and
determine frequency of operation.
5. Analyze the Master Slave flip-flop given in Fig. 1, and determine: a) set up time; b)
hold time; c) high clock period; d) low clock period; and e) maximum frequency of
operation of circuit (Assume all transmission gates to have equal propagation delay,
and all inverters to have equal propagation delay).
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SPICE Transistor Parameters
Parameter
NMOS
PMOS
Units
Source
Description
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VTO
KP
GAMMA
PHI
LAMBDA
RD
RS
CBD
CBS
IS
PB
CGSO
CGDO
CGBO
RSH
CJ
MJ
CJSW
MJSW
JS
TOX
NSUB
NSS
NFS
TPG
XJ
LD
UO
VMAX
0.7
40E-6
1.1
0.6
0.01
(40)
(40)
-0.8
12E-6
0.6
0.6
0.03
(100)
(100)
0.7
3.0E-10
3.0E-10
5.0E-10
25
4.4E-10
0.5
4.0E-10
0.3
1.0E-5
5.0E-8
1.7E16
0
0
1
6.0E-7
3.5E-7
775
1.0E5
0.6
2.5E-10
2.5E-10
5.0E-10
80
1.5E-4
0.6
4.0E-10
0.6
1.0E-5
5.0E-8
5.0E15
0
0
1
5.0E-7
2.5E-7
250
0.7E5
V
(A/V2)
(V0.5)
V
1/V
ohms
ohms
F
F
A
V
F/m
F/m
F/m
Ohms/sq
.
(F/m2)
F/m
(A/m2)
m
(1/cm3)
(1/cm2)
(1/cm2)
m
m
(cm2/Vs)
m/s
(1)
(5)
(1)
(3)
(5)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(3)
(3)
(3)
(1)
(1)
(1)
(1)
-zero bias threshold voltage
-transconductance parameter
-bulk threshold parameter
-surface potential
-channel-length modulation
-drain ohmic resistance (w=6μ)
-source ohmic resistance(″)
-zero bias B-D juction cap.
-zero bias B-S juction cap.
-bulk junction sat.current
-bulk junction potential;
-G-S overlap capacitance
-G-D overlap capacitance
-G-bulk overlap capacitance
-diffusion sheet resistance
-zero bias bulk junction cap.
-bulk junction grading coef.
-bulk junction sidewall cap.
-sidewall cap. Grading coef.
-bulk jinction sat.current
-oxide thickness
-substrate doping
-surface state density
-fast surface state density
-type of gate material
-metallurgical junction depth
-lateral diffusion
-surface mobility
-maximum drift velocity
SPICE Level 3 Parameters
Parameter
NMOS
PMOS
Units
Source Description
THETA
KAPPA
ETA
0.11
1.0
0.05
0.13
1.0
0.3
1/V
-
(1)
(1)
(1)
-mobility modulation
-saturation field factor
-static feedback
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Other Electrical Parameters
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Gate (Cox)
Metal1 – Field
Metal1 – Poly
Metal1 – Diffusion
Poly – Field
Metal2 – Field
Metal2 – Diffusion
Metal2 – Poly
Metal2 – Metal1
Capacitor P + - Poly
(0.1%/V linearity)
Capacitance
(pF/μm2)
6.9E-4
2.7E-5
5.0E-5
5.0E-5
6.0E-5
1.4E-5
1.6E-5
2.0E-5
2.5E-5
6.9E-4
Edge Component
(pF/μm)
0.5E-4
0.4E-4
Source
(1)
(1)
(1)
(1)
(1)
(4)
(4)
(4)
(4)
(*)
(1)
0.2E-4
2.0E-5
0.5E-4
Resistance
(ohms/sq.)
Source
N+ Diffusion
P+ Diffusion
N+ Poly
Capacitor P+
P-well
Metal1
Metal2
3 × 3 metal1 – P + Diffusion Contact
3 × 3 metal1 – N + Diffusion Contact
3 × 3 metal1 – N + Poly Contact
25
80
18
300
4K
0.035
0.030
121
44
25
(1)
(1)
(5)
(1)
(1)
(4)
(4)
(5)
(5)
(5)
Maximum operating voltage: 5 volts.
Sources: (1) D. Smith of NTE, presented at CMC Workshop June 6-7, 1985.
(2) Calculated by SPICE: e.g. –RSH is used to calculate RD & RS.
(3) SPICE default.
(4) D. Smith of NTE, April 1986.
(5) Typical Measured DC result.
(*) Estimate – Capacitors assumed to be equal to gate capacitance.
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Page 4 of 12
D
QN
CP
G3
G1
G2
G7
G10
G6
G4
G5
G8
Master
G9
Slave
Fig. 1
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Solution
Q
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S = CL/CN-1 Y = CLoad/Cin N =log Y/log S Y = S4 N = log S4/ log S = 4
CLoad = 200 pF 4 stages
tr = tf = 20 ns Wp = 3 Wn
1.
1
tr = 4CL / βpVdd
2
3
4
C1
C2
C3
CLoad
200pF
CL = 200pF neglecting drain capacitance
tr = 4CL / Kp’(Wp/Lp)Vdd
Wp4 = 4CL / Kp’(1/Lp)Vdd tr Let Lp = Lin = 3μm
= (4)(200 × 10-12)/(12 × 10-6) (1/3μ)(5)(20 × 10-9)
Wp4 = 2000 μm
Wn4 = Wp4 /3 = 666.67 μm
C3 = Cox [ WnLn + WpLp] = Cox [ WnLn + 3WnLp] = 4Cox Wn4Ln4
C3 = (4)(6.9x10-4 pF/μ2)(666.67μ)(3μ) = 5.52 pF
Using a scaling factor of 4 (Why scaling of 4? First one scaled for tr & tf . The last 3
scaled equally.)
Wp3 = Wp4/4 = 2000/4 = 500μ
Wn3 = Wn4/4 = 66,67/4 = 166.67μ
Wp2 = Wp3/4 = 500/4 = 125μ
Wn2 = Wn3/4 = 166.67/4 = 41.67μ
Wp1 = Wp2/4 = 125/4 = 31.25μ
Wn1 = Wn2/4 = 41.67/4 = 10.41μ
All lengths = 3 μm
C2= 4Cox Wn3Ln3 = (4)(6.9 × 10-4p)(166.67)(3) = 1.38 Pf
C1= 4Cox Wn2Ln2 = (4)(6.9 × 10-4p)(41.67)(3) = 0.345 Pf
a) Pdyn= CT Vdd2 f
CT = C1 + C2 + C3 + CLoad
CT = 0.345 pF + 1.38 pF+ 5.52 pF + 200 pF = 207.215 pF
Pdyn= 207.215 × 10-12 × (5)2 × (10 × 106) = 51.8 mW
b)
Idynamic = Pdyn/V = 51.8 mW/5 =10.36 mA
J = 1.5 mA/μm
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Width of bus = 10.36mA/1.5(mA/μm) = 6.9 μm
Better approximation
⎯ The Vdd bus should handle the peak current.
The peak current can be approximate by using ipeak = C.dV/dt ≅ C. ΔV/Δt
where ΔV =5V
Δt = tr or tf
tr stage 4 = 20 ns
tr stage 3 = (4)(5.52p)/12×10-6×500μ × 5/3μ = 2.21 ns
tr stage 2 = (4)(1.38p)/12×10-6×125μ × 5/3μ = 2.21 ns
tr stage 1 = (4)(0.345p)/12×10-6×31.25μ × 5/3μ = 2.21 ns
When all outputs switch
4
ipeak = ΔV ∑ Ci/tri
i=1
= 5[200pF/20ns + 5.52pF/2.21ns + 1.38pF/2.21ns + 0.345pF/2.21ns]
= 66.39 mA
bus size = 66.39mA/1.5mA/μm = 44.26 μm better approx.
2. 3 input CMOS NAND
a) minimum area Wp = Wn = 3μm
Lp = Ln = 3μm
Vdd
A
B
WnA = WnB =WnC = WpA= WpB =WpC = 3μm
LnA = LnB =LnC = LpA= LpB =LpC = 3μm
C
OUT
A
B
C
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Vdd
b) minimum propagation delay
Wp = √μn/μp Wn = 1.7Wn
5.1 μm
Equivalent inverter
3 μm
WnA = WnB =WnC = (3)(3μ) = 9 μ
WpA= WpB =WpC = 5.1μm
All lengths = 3 μm
Vdd
c) equal rise and fall times
βp = βn ⇒ Wp = 3Wn
9 μm
equivalent inverter
3 μm
WnA = WnB =WnC = (3)(3μ) = 9 μ
WpA= WpB =WpC = 9μm
All lengths = 3 μm
d) Worst case rise time
Vdd
A
B
C
OUT
A
Charging
0.1pF
B
C
The worst case rise time will be when only one input is low and the other two
are high. ( one PMOS “ON” and top twoNMOS “ON ‘a and B’).
tr = 2.2 τcharge
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τcharge = Rp (3 Cd⏐PMOS + 3 Cd⏐NMOS + 2Cs⏐NMOS + CL)
Assume all transistors are minimum size and that
Cd⏐PMOS + Cd⏐NMOS + Cs⏐NMOS = C
tr⏐worst = 2.2 Rp [8C +CL]
Rp = 1/βp(⏐Vgs -Vt⏐) = 1/[Kp’ Wp/Lp(⏐Vgs -Vt⏐) ] = 1/Kp’(4.2)
Rp = 1/(12 × 10-6)(4.2) = 19.8 kΩ
Cd = Cj×AD + CjSW×PD + CGSO × W
Assume a drain capacitance of 40fF
tr⏐worst = (2.2)(19.8k)[8×40x10-15 + 0.1 × 10-12]
tr⏐worst = 18.3 ns
Worst case fall time
Vdd
A
B
C
OUT
A
0.1pF
B
C
Assume minimum size transistors Wn = Ln = 3μm
tf = 2.2 τdischarge
τdischarge = (3Rn)(3Cd⏐PMOS + 3Cd⏐NMOS +2Cs⏐NMOS +CL]
Again assume Cd⏐PMOS + Cd⏐NMOS + Cs⏐NMOS = C
τdischarge = 3Rn (8C +CL)
Rn = 1/βn(Vgs –Vt) = 1/40×10-6(4.3) = 5.8 kΩ
Assume C = 40fF
tf = (2.2)(3)(5.8k)(8×40×10-15 + 0.1 × 10-12)
tf = 16.1 ns
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3. F = (AB + CD)’
Vdd = 5 V
When the function equal 1 there is no problem
Since there is no path to ground and the PMOS
charge the output node to Vdd.
Voff = Vdd
When the output is to be low we have a
problem since there will be a path from
Vdd to ground, and hence the output
voltage will depend on the ratio Zpu/Zpd
M5
F
A
M1
M3
C
B
M2
M4
D
⎯ Consider on inverter
when the output is low the PMOS is saturated
since Vds < Vgs-Vtp
assuming that VOL =0.5 V which is a good
value since it is less than Vtn. VOL < Vtn
the NMOS will be in linear region
Vds < Vgs – Vt
Vdd
Vout
Idp(sat) = In (linear)
βp/2[Vgs –Vtp]2 = βn[(Vgs – Vt)VOL – VOL2/2]
assuming Vgs =5V and ⏐Vtp⏐=Vtn = 1V
Vin
βp/2 (4)2 = βn[(4) VOL – VOL2/2] we can neglect VOL2/2
βp/2 (4)2 = βn(4) VOL
VOL ≅ 2βp/βn = 2 (Kp’ Wp/Lp)/(Kn’ Wn/Ln)
=2 (Kp’ /(Kn’)(Wp/Wn)
Let Lp= Ln =3μm
VOL = (2/3) (Wp/Wn)
Let VOL = 0.5V ⇒ Wp/Wn = (3/2)(1/2) =3/4 ⇒ Wp = (3/4)Wn
Let Wn = 4 μm ⇒ Wp = 3 μm
Vdd
3μ
Vout
Vin
4μ
We can use this equivalent inverter to size the gate
Vdd = 5 V
3μ
F
Voff = Vdd
VOL ≅ 0.5V
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VOH = 5 V
VOL = 0.5 V
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
4. 4 input AND gate
Vdd
Vdd
Φ
OUT
N1
Cin
A
B
C
D
Φ
C1
C2
C3
of inverter
⎯ Cin = Cd⏐PMOS + Cd⏐NMOS +Cg⏐PMOS +Cg⏐NMOS
⎯ C1, C2, C3 and C4 are modeling the source
plus drain capacitance.
C4
When Φ is low, the PMOS will charge up the output node to Vdd. Also during this time
the inputs can change.
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When the clock is low the PMOS is charging the output node towards Vdd. However, if
A goes high then the N1 node voltage will drop due to charge sharing. The worst case
would be if all the input go high since there will be charge sharing between Cin and C1,
C2, C3 and C4.
Vk
Cin
5V
C
V(0-) = 0 V
When one of the inputs goes high we have charge sharing and the N1 voltage will be
VN1 = (Cin(5) + C(0v))/(Cin + C)
VN1 = 5Cin(5)/(Cin + C)
To make sure that VN1 does rate decrease very much Cin >> C
Let Cin = 10C ⇒ V = (10/11)(5)= 4.5 V
To achieve this we should make the width of the PMOS large so as to increase the
capacitance at node N1.
The frequency of operation is given by 1/td where td =(tr + tf)/4
tr⏐worst = 2.2 Rp (Cin + C1 + C2 + C3)
tf⏐worst = 2.2 (RnA + RnB + RnC + RnD + RnΦ)(Cin + C1 + C2 + C3 + C4)
assume C1 =C2 = C3 =C
tr = 2.2 Rp (Cin + 3C)
tf = 2.2 Rneg(Cin + 3C + C4) where Rneg = RnA + RnB + RnC + RnD + RnΦ
f = 4/{2.2[Rp(Cin + 3C) + Rneg(Cin + 3C + C4)}
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
Question 5.
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a) Set up time: the setup time is required to allow the input signal to propagate through
G4, G5 and G6 to setup at G3. However inorder to turn off G4 and turn on G3 when
the clock is going high the clock signal must pass through the two inverters. (Which
are working in parallel with the setup time). Therefore the setup time will be less
than TG4 +TG5 +TG6. The setup time will be given by
tsetup = TG4 + TG5 + TG6 – (TG1 − TG2)
where T denotes the delay time of the gate.
b) Hold time: the input must remain stable as the clock is going from low to high. The
clock signal must pass through G1 and G2. Therefore
thold = TG1 + TG2
c) The high clock period:
The clock must remain high long enough to let the signal from the master propagate
through G8, G9 and G10 to setup at G7. Therefore
tclock⏐high = TG8 + TG9 + TG10
d) The low clock period:
The clock must remain low long enough to let the input signal to propagate through
G4, G5 and G6 to setup at G3. Therefore
tclock⏐low = TG4 + TG5 + TG6
e) fmax:
fmax = 1/(Tclock⏐low + Tclock⏐high)
fmax = 1/(TG8 +TG9 + TG10 + TG4 + TG5 + TG6)
Let TTRAN denote transmission gate propagation delay
Let TINV denote inverter gate propagation delay
fmax = 1/(2TTRAN + 4TINV)
fmax = (1/2)[1/(TTRAN + 2TINV)]