4.10
MOSFET circuit symbols and model
summary
D
D
G
G
B
B
S
S
(a) NMOS enhancement-mode device
(b) PMOS enhancement-mode device
D
D
G
G
B
B
S
(c) NMOS depletion-mode device
S
(d) PMOS depletion-mode device
Arrow points in Dthe direction of
G
S
(e) Three-terminal NMOS transistor
D
G
S
(f) Three-terminal PMOS transistor
Arrow points in the direction of positive current
Figure 4.18 - IEEE Standard MOS transistor circuit symbols
Mathematical Model Summary
NMOS Transistor model summary
For all regions
Cutoff region:
K n = µn Cox''
W
L
iG = 0
iB = 0
i DS = 0 for vGS ≤ VTN
Linear region:
iDS = K N (vGS − VTN −
vDS
)vDS for
2
v GS − VTN ≥ v DS ≥ 0
Saturation region:
iDS
KN
=
(vGS − VTN ) 2 (1 + λv DS )
for
2
v DS ≥ vGS − VTN ≥ 0
Threshold voltage:
VTN = VTO + γ ( v SB + 2φ F − 2φ F )
PMOS transistor mathematical model summary
For all regions
'' W
K n = µ n C ox
L
iG = 0
iB = 0
Cutoff region:
iSD = 0 for vSG ≤ −VTP (vGS ≥ VTP )
Linear region:
iSD = K P (vSG + VTP −
for
vSD
)vSD
2
vSG + VTP ≥ vSD ≥ 0
Saturation region:
K
iSD = P (vSG + VTP ) 2 (1 + λvSD ) for vSD ≥ vSG + VTP ≥ 0
2
Threshold voltage:
VTP = VTO − γ ( vBS + 2φF − 2φF )
D
S
+
i DS
G
B
+
v DS
SG
G -
v BS
+
+
B
-
v SB
vGS
-
v
+
v SD
-
-
i SD
+
S
D
PMOS
transistor
NMOS transistor
Figure 4.19 - NMOS and PMOS transistor circuit symbols
Table 4.1 - Categories of MOS Transistors
NMOS Device
PMOS Device
Enhancement-mode
VTN > 0
VTP < 0
Depletion-mode
VTN <= 0
VTP >=0
4.11
Biasing the MOSFET
An example biasing circuit
I DS
70 kΩ
R2
RL
100 kΩ
VDD
10 V
D
VGG
G
10 V
S
30 kΩ
R1
V
TN
=1V
Kn= 25 µA/V
2
Figure 4.20 - Constant gate voltage bias using a voltage divider
Example 4.1
Find the Q-point using the mathematical model for
the NMOS transistor
We replace the gate-bias network consisting of
VGG , R1 and R2 with its Thevenin equivalent circuit
R
R
D
EQ
G
21 kΩ
VEQ
Q
3V
I
+
+
L
100 kΩ
VDS
S
-
I DS
VDD
VGS
G
10 V
-
Figure 4.21 - Simplified MOSFET bias circuit
with
VEQ
=
R1R2
R1
=
R
VGG
and EQ R1 + R2
R1 + R2
We can determine the Q-point by using Kirchhoff’s
voltage law (KVL) in the loops with VGS and VDS
VEQ = I G REQ + VGS (*)
VDD = I DS RL + VDS
We know for the MOSFET, however that I G = 0 so
that VGS = VEQ = 3V and we get
Kn
(V GS − V TN ) 2 = 50 µ A
I DS =
2
and
VDS = VDD − I DS RL = 5V
VGS − VTN = 2V
We see that VDS exceeds VGS − VTN so that the
transistor is indeed saturated. Thus, the Q-point is
(50 µA,5V ) , with VGS = 3V .
Example 4.2
The Q-point for the MOSFET circuit in Fig.4.20 can
also be found graphically with a load-line method.
The second expression in Eq.(*) represents the load
line for this MOSFET circuit:
VDD = I DS RL + VDS
or
10 = 105 I DS + VDS
The load-line is constructed by finding two points:
for VDS = 0, I DS = 100µA , and for I DS = 0,VDS = 10V .
The resulting line is drawn on the output
characteristics of the MOSFET in Fig.4.22
1.50e-4
Drain Current (A)
1.25e-4
VGS= 4 V
1.00e-4
7.50e-5
Q-Point
VGS = 3 V
5.00e-5
2.50e-5
VGS= 2 V
Load Line
0.00e+0
-2.50e-5
0
2
4
6
8
10
12
Drain-Source Voltage (V)
Figure 4.22 - Load line for the circuit in Figs. 4.20 and 4.21
Example 4.3
The I-v characteristic of an ideal current source is
shown in Fig.4.23 which provides a constant output
current regardless of the polarity of the voltage across
the source.
If the value of VDD is chosen to be larger than the
value needed to pinch off the MOSFET [in this
case, VDD ≥ (VGS − VTN ) = 3 − 1 = 2V ], then the output
current will be constant at 50 µA . For V DD ≥ 2V , the
MOSFET represents an electronic current source
with a 50 µA output current.
100
80
Current I
DC
(µA)
Ideal 50 uA Current Source (Sink)
60
Pinchoff Point
40
20
NMOSFET
V =3V
GS
0
-20
-8
-6
-4
-2
0
2
Voltage V
DC
4
6
8
(V)
Figure 4.23 - Output characteristics for an ideal current source and the
MOSFET current source
Figure 4.24 shows the NMOS transistor biased with a
3-V dc source. This simple two-terminal MOSFET
circuit will behave as an electronic current source
I DC = I DS = 50 µA
over a limited range of terminal voltage, as long as
the external voltage VDC exceeds 2V.
Here, the current enters the source and it is often
referred to as a current sink.
I DC
D
I DS
+
+
G
+
VGS =3 V
VDC
IDC
S
-
VDC
V
DC
vDSAT
Figure 4.24 - NMOS transistor as an electronic current source
Example 4.4
150 k Ω
R
75 k Ω
2
R
D
(18 k Ω)
(100 k Ω)
G
D
VDD
+
10 V
S
100 k Ω
R1
39 k Ω
R
S
V
TN
(150 k Ω)
(22 k Ω)
=1V
Kn= 25 µA/V 2
Figure 4.25(a) - Four resistor bias network for a M OSFET
The four-resistor bias circuit in Fig.4.25(a) will
stabilize the MOSFET Q-point in the face of many
types of circuit parameter variations. A single voltage
source VDD is now used to supply both the gate-bias
voltage and drain current.
A Thevenin transformation is applied to this circuit,
resulting in the equivalent circuit given in Fig.4.26.
This is the final circuit to be analyzed.
150 kΩ
10 V
75 kΩ
R
R
D
2
G
VDD
D
VDD
+
10 V
S
100 kΩ
R
1
39 kΩ
R
S
Figure 4.25(b) - Equivalent circuit with replicated sources
Note that this circuit uses the three-terminal
representation for the MOSFET in which it is
assumed that the bulk terminal is tied to the source. If
the bulk terminal were grounded, the analysis would
become more complex because the threshold voltage
would then be a function of the voltage developed at
the source terminal of the device.
To determine the Q-point for the circuit in Fig.4.26,
we write the following two loop equations:
VEQ = I G REQ + VGS + ( I G + I DS ) RS
VDD = I DS RD + VDS + ( I G + I DS ) RS
Because we know that I G= 0 ,these equations reduce to
VEQ = VGS + I DS RS
VDD = I DS ( RD + RS ) + VDS
Again assuming that the transistor is operating in the
saturation region with
Kn
(VGS − VTN ) 2
I DS =
2
the input loop equation becomes
Kn R
(VGS − VTN )2
VEQ = VGS +
2
and we have a quadratic equation to solve for VGS .For
the values in Fig.4.25 with VTN = 1V and
K n = 25µA / V 2
VGS = ± 2.66V For VGS = − 2.66V ,the
So we get
MOSFET would be cut off because vGS < VTN . So,
VGS = + 2.66V is the answer, and I DS = 34.4 µA . VDS is
then found to be 6.08V. We have
VDS = 6.08V, VGS −VTN =1.66V
VDS ≥ (VGS −VTN )
The saturation region assumption is consistent with
(34.4µA,6.08V ) with
the
resulting
Q-point:
VGS = 2.66V
R
R
D
EQ
G
60 kΩ
DS
+
S
EQ
I
G
S
V
R
39 kΩ
I
DS
+
GS
4V
+
V
V
V
75 kΩ
D
VDD
10 V
S
-
Figure 4.26 - Equivalent circuit for the four resistor bias network
Example 4.5
Let us redesign the four-resistor bias network in the
previous example to increase the current while
keeping VDS approximately the same: the desired Qpoint will be (100µA,6V ) . We can see that the sum of
and RS in the bias network of Fig.4.26 is
determined by the Q-point values
RD
VDD − VDS
= 40 KΩ
I DS
The required value of RS
RD + RS =
RS =
VEQ − VGS
I GS
=
VS
I DS
But we must first find the value of VGS
The gate-source voltage needed to establish
I DS = 100 µA can be found by rearranging the
expression for the MOSFET drain current,
VGS = VTN +
So Rs=1.7 KΩ
2 I DS
= 3.83V
Kn