HW#3 Solution
Dr. Parker
Spring 2014
Assume for the problems below that Vdd = 1.8 V, Vtp0 is -.7 V. and Vtn0 is .7 V. Vtpbodyeffect is -.9 V. and
Vtnbodyeffect is .9 V.
Assume ßn (kn)= 219.4 W/L µ A(microamps)/V2 and ßp (kp)= 51 W/L µ A/V2
1. (10%) A PMOS transistor has Vs = 1.8 V , Vd = .9 V. Vg = .6 V. What region of operation is it in?
Vgs= .6 – 1.8= -1.2 V
Vtp= -.7 V (there is no body effect since the source is tied to the highest potential)
Vds=.9-1.8= -.9 V
Vds > Vgs-Vtp?
-.9 > -1.2 –(-.7)?
-.9 > -.5? False, transistor is in SATURATION region
2. (10 %) An NMOS transistor has Vg = 1.8 V. Vd = .9 V. Is the transistor in the linear region of
operation when Vgs =1.3 V?
Vg-Vs=Vgs
1.8 –Vs=1.3 V
Vs=1.8-1.3 = .5 V
There is body effect since the transistor source is not connected to the lowest potential.
Vds= .9-.5=.4 V
Vds< Vgs –Vtnbodyeffect?
.4 < 1.3 - .9?
.4 < .4? The transistor is in the border between linear a saturation region since Vds=Vgs-Vtnbodyeffect.
The channel is said to be pinched-off.
3. a) (5 %) A PMOS transistor is used as a pass transistor (switch). The input voltage is Vin = 1.1 V.
The gate voltage Vg=.4 V. The voltage Vout = 1.7 V at time t = 0. What is the final output voltage at t =
infinity?
The source is at the output. At t=infinity, the minimum voltage that it can be transferred to the output is
Vg+|Vtpbodyeffect|, so Vout=.4 V+.9 V= 1.3 V.
Note that Vgs ≤ Vtpbodyeffect (condition for the transistor to be ON) ! Vg-Vs ≤ Vtpbodyeffect !
Vs ≥ Vg-Vtpboyeffect ! Vs ≥ .4 –(-.9) !Vs ≥ 1.3 V
b) (3%) Does the PMOS transistor have body effect when t approaches infinity?
Yes, it does have body effect because the source terminal is different from the maximum potential.
c) (10%) Assume the transistor width is 8 lambda and the length is twice minimum size. Compute
the drain current flow IDS at t=0 and at t = infinity.
First we need to determine the region of operation of the transistor at t=0 and at t=infinity.
at t=0
Vds= 1.1-1.7= -.6 V
Vgs= .4-1.7= -1.3 V
Vtpbodyeffect= -.9 V (the source is lower than the highest potential)
Vgs ≤ Vtpbodyeffect? If this condition is true, the transistor is ON.
-1.3≤ -.9? The condition is true, so the transistor is ON.
Vds > Vgs-Vtpbodyeffect?
-.6 > -1.3 – (-.9)?
-.6 > -.4? False, so the transistor is in SATURATION
Idsp = µp*Cox*W/L*(Vgs-Vtpbodyeffect)^2
=(51x10^-6)(8/4)(-1.3-(-.9))^2
= -16.32 uA (negative sign indicates the current flow direction)
At t=infinity
Vds= 1.1-1.3= -.2 V
Vgs= .4 – 1.3= -.9 V
Vtpbodyeffect= -.9 V
Vgs ≤ Vtpbodyeffect? If this condition is true, the transistor is ON
-.9 ≤ -.9? The condition is true, so the transistor is ON.
Vds > Vgs-Vtpbodyeffect? If the condition is true the transistor is in linear region
-.2 > -.9 – (-.9)?
-.2 > 0? False, so the transistor is in SATURATION
Idsp = µp*Cox*W/L*(-.9-(-.9))^2
Idsp= 0 A
4. a) (7 %) Identify the sources and drains in a transmission gate at t=0+ when Vin = 1.1 V and Vout
= .3 V. Vgn = 1.4 V, and Vgp = .4 V.
b) (8 %) What regions are the two transistors in when t approaches infinity? Be sure to justify your
answers.
PMOS:
Vgs = .4 -1.1 = -.7 V
Vgs ≤ Vtpbodyeffect?
-.7 V ≤ -.9 V? False, thus the transistor is in cutoff
NMOS:
A t= infinity the output voltage is Vg-Vtnbodyeffect = 1.4 - .9= .5 V
Vgs= 1.4 -.5 = .9 V
Vds= 1.1 - .5 =.6 V
Note that if the output voltage we to rise any further, the NMOS transistor would have Vgs <.9v so the
transistor is cutoff.
5. (10%) Assume we have N NMOS transistors connected in series. If at t=0 the input voltage is Vdd and
all internal nodes are 0 V (V1, V2,..., VN), what is the maximum voltage at the output VN at t=infinity?
A t= infinity, the maximum voltage that can be transfered at VN is Vdd – Vtnbodyeffect, so
VN= 1.8-.9= .9 V
6. (10%) Find the voltages V1, V2, and V3 at t=infinity. Assume that at t=0, V1,V2, and V3 are equal to 0
V.
D S D S D S V1MAX= 2*Vdd- Vtnbodyeffect = 2*1.8-.9= 2.7 V
V2MAX= (2*Vdd- Vtnbodyeffect) – Vtnbodyeffect = 2.7 – .9 = 1.8 V
V3MAX = (2*Vdd- Vtnbodyeffect) – Vtnbodyeffect – Vtnbodyeffect = 1.8 -.9 = .9 V
V1 = 1.5 V
V2 = 1.5 V - Vtnbodyeffect = .6V
V3 = 0.0V
7. (5%) You might need to solve this problem after Thurs. lecture. What is the effective channel
resistance of a 3 times width of a unit size PMOS transistor? Assume Vg=0.2V, Vs= 1.5V, Vd=1.4V.
Vgs = .2 -1.5 =-1.3 V
Vds = 1.4 – 1.5 = -.1 V
Vds> Vgs – Vtpbodyeffect ?
-.1 > -1.3 – (-.9)?
-.1 > -.4? This is true, so the transistor is in linear region.
Rchp = 1/( ßp*W/L*(Vgs-Vtpbodyeffect))
Rchp = |1/(51X10^-6*((3*4)/2)*(-1.3-(-.9))| = 8.17 KΩ
8. (5%) What is the parasitic effect that is created when we have current flowing between Vdd and
ground away from the transistor channels in a CMOS process?
Latchup
How can we avoid it? 1) build guard rings around transistors. 2) For NMOS! p+ guard rigns, for
PMOS! n+ guard rings. 3) Trench in isolation with SiO2. 4) Turn off Vdd. 5) Change the technology
(SOI, SOS, FinFET).
9. (5%) Does the threshold increase or decrease if we use thick oxide instead of thin oxide under the poly
in the gate region? Why?
It increases
because
an increase
in or
thedecrease
thicknessifdecreases
the oxide
oxide instead
capacitance
which
inversely
9. (5%)
Does the
threshold
increase
we use thick
of thin
oxideisunder
the poly
proportional
to the
body-effect coefficient (equation 3.23 and 3.24)
in the
gate region?
Why?
10. (7%) because
Why is the
substrateininthe
NMOS
connected
to ground
and capacitance
in PMOS towhich
Vdd? is inversely
It increases
an increase
thickness
decreases
the oxide
proportional to the body-effect coefficient (equation 3.23 and 3.24)
In an NMOS transistor, substrate is connected to ground to reverse bias the pn junctions that are formed
p- substrate
and n+ in
diffusions,
so that notocurrent
between
the substrate and the n+
10.between
(7%) Why
is the substrate
NMOS connected
groundflow
and occurs
in PMOS
to Vdd?
diffusions. In a PMOS transistor, substrate is connected to Vdd to reverse bias the pn junctions that are
between
p+ diffusions
n-well. to ground to reverse bias the pn junctions that are formed
In formed
an NMOS
transistor,
, substrate and
is connected
between p- substrate and n+ diffusions
diffusions, so that no current flow occurs between the substrate and the n+
11.
(5%)
Sketch
the
crossection
of a PMOS
transistorto
when
< Vgs-V
Show
thethat
shape
tp0. the
diffusions. In a PMOS transistor, su
substrate
is connected
VddVds
to reverse
bias
pnclearly
junctions
areof the
channel.
formed between p+ diffusions and nn-well.
11. (5%) Sketch
etch the crossection of a PMOS transistor when Vds < Vgs-Vtp0. Show clearly the shape of the
channel.
Note that the PMOS transistor is in saturati
saturation when Vds < Vgs-Vtp0. If Vds is lower than Vgs-Vtp0, the
Note that
the PMOS
is in saturation
when
Vds < Vgs-Vtp0. If Vds is lower than Vgs-Vtp0, the
channel
pinch-off
point transistor
slightly moves
away from
the drain.
channel pinch-off point slightly moves away from the drain.
12. (10%) In an inverter, if Vin rises slowly, so there is a subthreshold current through the NMOS
12. (10%)
In Vin<Vthn,
an inverter,will
if Vin
slowly,
so there
a subthreshold
through
the NMOS
transistor
when
the rises
NMOS
transistor
sstill
tillismove
from cutoffcurrent
to saturation
when
Vin=Vthn?
transistor when Vin<Vthn, will the NMOS transistor still move from cutoff to saturation when Vin=Vthn?
The transistor is in saturation.. By definition if Vgs is greater than or equal to Vthn, then
n the NMOS
The transistor
in saturation.
Bysaturation
definitionisif true,
Vgs issince
greater
or-V
equal
transistor
is ON. isThe
condition for
Vdsnthan
> Vgs
thn. to Vthn, then the NMOS
transistor is ON. The condition for saturation is true, since Vdsn> Vgs-Vthn.