ECE380 Digital Logic
Implementation Technology:
NMOS and PMOS Transistors,
CMOS logic gates
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-1
Logic values as voltage levels
• Vss is the minimum
voltage that can exist
in the system. We
will use Vss=0V.
• VDD is the power
supply voltage. We
will use VDD =+5V.
VDD =+3.3V is also
common.
• Exact levels of V0,max
and V1,min depend on
the implementation
technology
Electrical & Computer Engineering
VDD
Logic value 1
V1,min
Undefined
V0,max
Logic value 0
Vss (Gnd)
Dr. D. J. Jackson Lecture 13-2
1
Transistor switches
• Logic circuits are built with transistors
• We will assume a transistor operates as a simple
switch controlled by a logic signal x
• The most popular type of transistor for implementing
a simple switch is the metal oxide semiconductor
field effect transistor (MOSFET)
• Two types of MOSFETs
– N-channel (NMOS)
– P-channel (PMOS)
• Early circuits relied on NMOS or PMOS transistors,
but not both
• Current circuits use both NMOS and PMOS
transistors in a configuration called complementary
MOS (CMOS)
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-3
NMOS transistor as a switch
x=“low”
x=“high”
A simple switch controlled by the input x
Gate
Source
Drain
Substrate (Body)
NMOS transistor
Electrical & Computer Engineering
V
G
VS
VD
Simplified NMOS symbol
Dr. D. J. Jackson Lecture 13-4
2
NMOS transistor as a switch
V = “low”
G
VD
VS
V = “high”
G
VD
VS
• The transistor operates by
controlling the voltage VG at
the gate terminal
• If VG is low, there is no
connection between the
source and the drain
terminals. The transistor is
turned off.
• If VG is high, the transistor is
turned on and acts as a
closed switch between the
source and drain terminals.
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-5
PMOS transistor as a switch
x=“high”
x=“low”
A simple switch controlled by the input x
Gate
Drain
Substrate (Body)
V
DD
PMOS transistor
Electrical & Computer Engineering
VG
Source
VS
VD
Simplified PMOS symbol
Dr. D. J. Jackson Lecture 13-6
3
PMOS transistor as a switch
VG = “high”
VS
VD
VG = “low”
VS
VD
• The transistor operates by
controlling the voltage VG at
the gate terminal
• If VG is high, there is no
connection between the
source and the drain
terminals. The transistor is
turned off.
• If VG is low, the transistor is
turned on and acts as a
closed switch between the
source and drain terminals.
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-7
NMOS and PMOS in logic
circuits
VD
VD
V
G
NMOS transistor
VS = 0 V
PMOS transistor
VD = 0 V
Closed switch
when VG=VDD
Open switch
when VG=0V
VS=VDD
VDD
VDD
VD
Open switch
when VG=VDD
VG
Electrical & Computer Engineering
VD=VDD
Closed switch
when VG=0V
Dr. D. J. Jackson Lecture 13-8
4
NMOS and PMOS in logic
circuits
• When the NMOS transistor is turned on, its
drain is pulled down to Gnd
• When the PMOS transistor is turned on, its
drain is pulled up to VDD
• Because of the way transistors operate:
– An NMOS transistor cannot be used to pull its
drain terminal completely up to VDD
– A PMOS transistor cannot be used to pull its drain
terminal completely down to Gnd
• Therefore, NMOS and PMOS transistors are
commonly used in pairs in CMOS circuits
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-9
CMOS logic gates
• A CMOS logic gate involves NMOS transistors
in a pull-down network (PDN) and PMOS
transistors in a pull-up network (PUN)
• The functions realized by the PDN and PUN
networks are complements of one another
• The PDN and PUN have equal numbers of
transistors, which are arranged so that the
two networks are duals of one another
– Wherever the PDN has NMOS transistors in series,
the PUN has PMOS transistors in parallel, and vice
versa
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-10
5
CMOS logic gates
VDD
• For any given valuation
of the input signals,
either the PDN pulls Vf
down to Gnd or the PUN
pulls Vf up to VDD
Pull-up network
(PUN)
PMOS transistors
Vf
VX1
VXn
Pull-down network
(PDN)
NMOS transistors
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-11
CMOS NOT gate
V DD
V DD
T1
Vx
V DD
Vf
T2
0
x
T1 T2
f
0
On Off
1
1
Off On
0
Electrical & Computer Engineering
1
1
0
2 transistors
Dr. D. J. Jackson Lecture 13-12
6
CMOS NAND gate
VDD
T1
T2
Vf
VX1
T3
VX2
T4
X1
X2
T1
T2
T3
T4
f
0
0
On On Off Off 1
0
1
On Off Off On 1
1
0
Off On On Off 1
1
1
Off Off On On 0
4 transistors
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-13
CMOS NOR gate
VDD
VX1
T1
VX2
T2
Vf
T3
T4
X1
X2
T1
T2
T3
T4
f
0
0
On On Off Off 1
0
1
On Off Off On 0
1
0
Off On On Off 0
1
1
Off Off On On 0
4 transistors
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-14
7
CMOS AND gate
VDD
VDD
T2
T1
Vf
VX1
T3
VX2
T4
6 transistors
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-15
CMOS OR gate
VDD
VX1
T1
VX2
T2
VDD
Vf
T3
T4
6 transistors
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-16
8
CMOS non-inverting buffer
VDD
x
Vx
f
Vf
f=x
A non-inverting buffer
4 transistors
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-17
CMOS transmission gate
s’
s’
x
f
s
x
f
s
0
1
f
Z
x
s
2 transistors
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 13-18
9
CMOS tri-state buffer
e
e
x
f
e
x
f
0 0
Z
0 1
Z
1 0
0
1 1
1
Electrical & Computer Engineering
x
f
8 transistors
Dr. D. J. Jackson Lecture 13-19
10