Lecture #24 Gates to circuits
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EE 42 fall 2004 lecture 24
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Topics
Today:
• Implementing gates with MOS transistors
• Gate delays
• Glitches
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EE 42 fall 2004 lecture 24
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CMOS and complementary logic
• Complementary PMOS and NMOS switches in
parallel or in series with complementary logic to
form high speed, low power logic
• PMOS devices turn on with low voltages, so we
use them in the pull up circuit for a gate
• NMOS devices turn on with high voltages, so we
use them in the pull down circuit for a gate
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EE 42 fall 2004 lecture 24
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Pull up/Pull down
Using CMOS, which has
both NMOS and PMOS
transistors, we can build
gates which turn on a
connection to +V when
the output is supposed A
to be high, and another B
connection to ground C
when the output is
supposed to be low.
+V
(PMOS)
Output
(NMOS)
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CMOS NOR
VDD
A
B
A B
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CMOS NOR
IF both A and B are low, then
both pull up transistors are
on
VDD
A
B
A+B
IF neither A or B are high
then both of the pull down
transistors are off
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EE 42 fall 2004 lecture 24
And the output
Goes high
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CMOS NOR
IF either A and B are low,
then at least one of the
pull up transistors is off
VDD
A
B
A+B
IF either A or B are high then
at least one of the pull
down transistors is on
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EE 42 fall 2004 lecture 24
And the output
goes low
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CMOS NAND
VDD
A
AB
B
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CMOS NAND
VDD
A
A B  C
B
C
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CMOS logic transitions
• If we look at CMOS with static inputs, it will
pull up high logic levels all the way to the
supply
• Low logic levels are pulled all the way
down to ground.
• We will now look at the behavior of the
circuits as they are switching, which will
determine the performance of the logic
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EE 42 fall 2004 lecture 24
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NMOS current vs. Voltage
(Drain) current
saturation values
IOUT(mA)
100
State 5 or VIN = 5V
Current is flat
(saturated) beyond
VOUT-SAT-D
State 3 or VIN = 3V
60
The maximum
voltage is VDD
Current is zero until VIN
is larger than VTD
20
State 1 or VIN = 1V
0
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VOUT-SAT-D
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EE 42 fall 2004 lecture 24
VDD =5 VOUT(V)
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PMOS current vs. Voltage
(Drain) current
State 5 or VIN = 5V saturation values
IOUT(mA)
100
Current is flat
(saturated) below
VOUT-SAT-D
State 3 or VIN = 3V
60
Current is zero until VIN
is below VTD
20
0
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3 VOUT-SAT-DVDD =5 VOUT(V)
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CMOS Inverter
• Since CMOS uses one or more PMOS
devices to pull up, and one or more NMOS
devices to pull down, we can get most of
the dynamics from an inverter.
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CMOS inverter
VDD
A
A
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• Since +V is the sum of the voltage across
the NMOS device and the PMOS device,
we can draw a composite IV plot for the
two devices, showing the current which is
available from each of the two devices.
• On the next slide, notice that when one
device is turned on, and able to provide a
lot of current, the other device is off
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EE 42 fall 2004 lecture 24
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Composite IOUT vs. VOUT for CMOS
PU current is flat
(saturated) below
VDD - VOUT-SAT-D
IOUT(mA)
100
PD current is flat
(saturated) beyond
VOUT-SAT-D
60
Pull-Down NMOS IOUT-SAT-D
State 3 or VIN = 3V
Solution
Pull-Up PMOS IOUT-SAT-U
20
0
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The maximum
voltage is VDD
VOUT-SAT-D
3
EE 42 fall 2004 lecture 24
VDD =5 VOUT(V)
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Output Propagation Delay High to Low
VOUT(0) = 5V
IOUT-SAT-D
= 100 mA
VIN = 5V
100
IOUT(mA)
60
COUT = 50 fF 2
0
IOUT-SAT-D = 100 mA
0
V3OUT(V) 5
When VOUT > VOUT-SAT-D the available current is IOUT-SAT-D
For this circuit when VOUT > VOUT-SAT-D the available current
is constant at IOUT-SAT-D and the capacitor discharges.
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Output Propagation Delay High to Low
(Cont.)
The propagation delay is thus
t 
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COUT V
I OUT  SAT  D
COUTVDD
50 fF  2.5V


 1.25 ns
2 I OUT  SAT  D
100 mA
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RD = ¾ VDD/ISAT has a Physical
Interpretation
VOUT(0) = 5V
IOUT-SAT-D
= 100 mA
VIN = 5V
100
IOUT(mA)
60
COUT = 50 fF 2
0
IOUT-SAT-D = 100 mA
0
V3OUT(V) 5
¾ VDD is the average value of VOUT
Approximate the NMOS device curve by a straight line
from (0,0) to (IOUT-SAT-D, ¾ VDD ).
Interpret the straight line as a resistor with
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slopeEE=421/R
= lecture
¾ V24DD/ISAT
fall 2004
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Switched Equivalent Resistance
Values
The resistor values depend on the properties of silicon,
geometrical layout, design style and technology node.
n-type silicon has a carrier mobility that is 2 to 3 times
higher than p-type.
The resistance is inversely proportion to the gate
width/length in the geometrical layout.
Design styles may restrict all NMOS and PMOS to be of a
predetermined fixed size.
The current per unit width of the gate increases nearly
inversely with the gate width.
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Inverter Propagation Delay
Discharge (pull-down)
VDD
VDD
VOUT
VOUT
VIN =
Vdd
COUT = 50fF
VIN =
Vdd
RD
COUT = 50fF
t = 0.69RDCOUT = 0.69(10kW)(50fF) = 345 ps
Discharge (pull-up)
t = 0.69RUCOUT = 0.69(10kW)(50fF) = 345 ps
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Example using resistor model
• Using the resistor model, we can calculate
the approximate rise and fall times for
more complex gates, such as
A  BC  A  B  C  A( B  C )
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NMOS and
PMOS use the
same set of
input signals
CMOS Logic Gate
VDD
PMOS only in pull-up
PMOS conducts when input is low
A
B
PMOS do not conduct when
A +(BC)
C
VOUT
NMOS only in pull-down
B
A
NMOS conduct for A + (BC)
C
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NMOS conduct when input is high.
Logic is Complementary and
produces Vout = A + (BC)
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CMOS Logic Gate: Example Inputs
VDD
A=0
B=0
C=0
PMOS all conduct
A
Output is High
B
C
VOUT
B
= VDD
NMOS do not conduct
A
C
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Logic is Complementary and
produces Vout = 1
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CMOS Logic Gate: Example Inputs
VDD
A=0
B=1
C=1
PMOS A conducts; B and C Open
A
Output is High
B
C
VOUT
B
=0
NMOS B and C conduct; A open
A
C
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Logic is Complementary and
produces Vout = 0
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Switched Equivalent Resistance
Network V
VDD
DD
RU
A
A
RU
RU
B
C
VOUT
C
B
Switches
close when
input is low.
VOUT
RD
B
A
RD
B
A
RD
C
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Switches
close when
input is high.
C
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